EDA课程设计课件

Example: Design a single bit full adder with
carry 带进位的一位全加器
Specifications
Sub Block 1
Sub Block 1
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Design Methodology 设计方法
Bottom-Up Design Methodology
identify building block that are available for us build a bigger cells using these block continue build a cell until we build the top-level
CPLD: Complex Programmable Logic Device 复杂可编程逻辑器件
Based on the and or array structure基于与 或阵列结构
FPGA: Field Programmable Gate Array 现场可编程门阵列
Based on the gate array structure基于门阵 列结构
Modern Electronic Technologies& EDA
现代电子技术与EDA
授课教师: 授课教师 臧淼
Dept. of Telecom.
EDA (Electronic Design Automation)
Electronics: Analog & Digital computer-aided design (CAD)/design automation (DA) / electronic design automation (EDA) Synthesis 综合: 综合:
Define top-level block and identify the sub-blocks topsubdivide sub-block until we come to leaf cells sub-
Top-Down Design Methodology
Top Level Block
Sub Block 1
Entity Declarations
Port Clause (cont.)
The port mode of the interface describes the direction in which data travels with respect to the component The four available port modes are: In - data comes in this port and can only be read Out - data travels out this port Buffer - data may travel in either direction, but only one signal driver may be on at any one time但输入只允许内部回读输出的信号 Inout - data may travel in either direction with any number of active drivers allowed
a specification an actual implementation of the design
Simulation 仿真 仿真:
the implementation can be exercised in order to verify correct operation.
Design Entry 设计输入
Comments Basic Identifiers
Only alphabetic letters ( A-Z, a-z ), or Decimal digits ( 0-9 ), or Underline character ( _ ) Must start with alphabetic letter ( MyVal ) Not case sensitive ( LastValue = = lAsTvALue ) May NOT end with underline ( MyVal_ ) May NOT contain sequential underlines (My__Val) Do NOT use Reserved Words as identifiers e.g. --this is a comment two dashes to end of line is a comment
Entity Declaration
The words shown in bold are reserved words. VHDL is not case-sensitive Entity declaration
entity ex_and2 is port (a, b: in bit ; c: out bit) ; end entity [ex_and2];
PLD Manufacturer

最大的PLD供应商之一

FPGA的发明者，最大的PLD供应 FPGA PLD 商之一

ISP技术的发明者

提供军品及宇航级产品
Classification of PLD 分类
Another architecture for Ex1
architecture ex2 of and_2 is signal xy: bit_vector(1 downto 0); begin xy <= x&y; process(xy) begin case xy is when "00" => z<='0'; when "01" => z<='0'; when "10" => z<='0'; when "11" => z<=‘1'; end case; end process; end architecture ex2
Architecture Description
Signal assignments: pass the value of one signal directly to another.
Example: c<=a and b; z<= not ((x and y) or (a and b);
Descriptions
Schematic capture 图形输入 Textual capture: hardware description language (HDL)
Quartus II Installation
Implementing setup.exe License setup
Quartus II Development Flow开发流程
Description
Entity & Architecture实体与结构体
Entity describes the inputs and outputs, together with types, of the circuit Architecture describes the function and/or structure of the circuit it is possible to have more than one architecture for each entity
Macro Cell 3
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Example 4-bit Ripple Carry Counter
q0 q1 q2 q3
D Clock
SET
Q
D
SET
Q
D
SET
Q
D
SET
Q
tff0
CLR
tff1
CLR
Design Entry 设计输入 Full Compilation 全编译
Logic Synthesis Place & Route Timing & Analysis
Simulation 仿真 Device Programming 器件编程
PLD (Programmable Logic Device)
tff2
tff3
Q
Q
CLR
Q
CLR
Q
Reset
Design Hierachy
Ripple Carry Counter
T_FF (tff0)
T_FF (tff1)
T_FF (tff2)
T_FF (tff3)
D_FF
Inverter
D_FF
Inverter
D_FF
Inverter
D_FF
Inverter
可编程逻辑器件
LD(逻辑器件)：用来实现某种特定逻辑功能的 电子器件，最简单的逻辑器件是与、或、非门 （74LS00，74LS04等），在此基础上可实现 复杂的时序和组合逻辑功能。 PLD可编程逻辑器件：器件的功能不是固定不 变的，而是可根据用户的需要而进行改变，即 由编程的方法来确定器件的逻辑功能。
Two version: 1987, 1993
Entity Declarations
Port Clause
PORT clause declares the interface signals of the object to the outside world Three parts of the PORT clause