CAT24C03WI-GT3中文资料
CAT4104V-GT3;CAT4104VP2-GT3;中文规格书,Datasheet资料
CAT4104700 mA Quad ChannelConstant Current LED DriverDescriptionThe CAT4104 provides four matched low dropout current sinks to drive high −brightness LED strings up to 175 mA per channel. The LED channel current is set by an external resistor connected to the RSET pin. The LED pins are compatible with high voltage up to 25 V supporting applications with long strings of LEDs.The EN/PWM logic input supports the device enable and high frequency external Pulse Width Modulation (PWM) dimming control.Thermal shutdown protection is incorporated in the device to disable the LED outputs whenever the die temperature exceeds 150°C.The device is available in the 8−pad TDFN 2 mm x 3 mm package and the SOIC 8−Lead 150 mil wide package.Features•4 Matched LED Current Sinks up to 175 mA •Up to 25 V Operation on LED Pins•Low Dropout Current Source (0.4 V at 175 mA)•LED Current Set by External Resistor•High Frequency PWM Dimming via EN/PWM •“Zero” Current Shutdown Mode •Thermal Shutdown Protection•TDFN 8−pad 2 x 3 mm and SOIC 8−lead Packages•These Devices are Pb −Free, Halogen Free/BFR Free and are RoHS CompliantApplications•Automotive Lighting•General and Architectural Lighting •LCD BacklightFigure 1. Typical Application Circuit768 WONOFFSOIC −8V SUFFIX CASE 751BD PIN CONNECTIONSMARKING DIAGRAMSCAT4104V = CAT4104VHC = CAT4104VP2SOIC 8−lead (Top View)Device Package Shipping ORDERING INFORMATIONCAT4104V −GT3(Note 1)SOIC −8(Pb −Free)3,000/Tape & Reel 1.Lead Finish is NiPdAuCAT4104V TDFN −8VP SUFFIX CASE 511AKCAT4104VP2−GT3(Note 1)TDFN −8(Pb −Free)3,000/Tape & ReelGNDVIN RSET LED4LED3LED2LED11EN/PWM GNDVINRSET LED4LED3LED2LED1EN/PWM TDFN 8−pad (Top View)HC1Table 1. ABSOLUTE MAXIMUM RATINGSParameter Rating Unit VIN, RSET, EN/PWM Voltages−0.3 to 6V LED1, LED2, LED3, LED4 Voltages−0.3 to 25V Storage Temperature Range−65 to +160_C Junction Temperature Range−40 to +150_C Lead Temperature300_C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.Table 2. RECOMMENDED OPERATING CONDITIONSParameter Rating Unit VIN 3.0 to 5.5V Voltage applied to LED1 to LED4, outputs off up to 25V Voltage applied to LED1 to LED4, outputs on up to 6 (Note 2)V Ambient Temperature Range−40 to +85_CI LED per LED pin10 to 175mA2.Keeping LEDx pin voltage below 6 V in operation is recommended to minimize thermal dissipation in the package.NOTE:Typical application circuit with external components is shown on page 1.Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Min and Max values are over the recommended operating conditions= 25°C.)unless specified otherwise. Typical values are at VIN = 5.0 V, TTable 4. RECOMMENDED EN/PWM TIMING (Min and Max values are over the recommended operating conditions unless specified otherwise. Typical values are at VIN = 5.0 V, T AMB = 25°C.)Symbol NameConditions MinTyp MaxUnits T PS Turn −On time, EN/PWM rising to I LED from shutdownI LED = 175 mA I LED = 80 mA 1.51.3m s T P1Turn −On time, EN/PWM rising to I LED I LED = 175 mA 600ns T P2Turn −Off time, EN/PWM falling to I LED I LED= 175 mA I LED = 80 mA 400300ns T R LED rise time I LED = 175 mA I LED = 80 mA 700440ns T F LED fall time I LED = 175 mA I LED = 80 mA360320ns T LO EN/PWM low time 1m s T HI EN/PWM high time5m s T PWRDWNEN/PWM low time to shutdown delay48msFigure 2. CAT4104 EN/PWM TimingEN/PWM OperationThe EN/PWM pin has two primary functions. One function enables and disables the device. The other function turns the LED channels on and off for PWM dimming control. The device has a very fast turn −on time (from EN/PWM rising to LED on) and allows “instant on” when dimming LED using a PWM signal.Accurate linear dimming is compatible with PWM frequencies from 100 Hz to 5 kHz for PWM duty cycle down to 1%. PWM frequencies up to 50 kHz can be supported for duty cycles greater than 10%.When performing a combination of low frequencies and small duty cycles, the device may enter shutdown mode.This has no effect on the dimming accuracy, because the turn −on time T PS is very short, in the range of 1 m s.To ensure that PWM pulses are recognized, pulse width low time T LO should be longer than 1 m s. The CAT4104enters a “zero current” shutdown mode after a 4 ms delay (typical) when EN/PWM is held low.Figure 3. Quiescent Current vs. Input Voltage(RSET Open)Figure 4. Quiescent Current vs. RSET CurrentINPUT VOLTAGE (V)RSET CURRENT (mA)5.55.04.54.03.53.00.40.60.81.01.22.01.51.00.5002468Figure 5. Quiescent Current vs. Input Voltage(Full Load)Figure 6. LED Dropout vs. LED Pin VoltageINPUT VOLTAGE (V)LED PIN VOLTAGE (V)5.55.04.54.03.53.05.05.56.06.57.0 1.00.80.60.40.2004080120160200Figure 7. LED Line RegulationFigure 8. LED Current Change vs.TemperatureVIN (V)TEMPERATURE (°C)5.55.04.54.03.53.00408012016020012080400−4004080120160200Q U I E S C E N T C U R R E N T (m A )Q U I E S C E N T C U R R E N T (m A )Q U I E S C E N T C U R R E N T (m A )L E D C U R R E N T (m A )L E D C U R R E N T (m A )L E D C U R R E N T (m A )No LoadFull LoadFigure 9. LED Current vs. RSET ResistorFigure 10. LED Current vs. LED Pin VoltageRSET (k W )LED PIN VOLTAGE (V)1010.1101001000654321004080120160200Figure 11. RSET Pin Voltage vs. Input VoltageFigure 12. RSET Pin Voltage vs. TemperatureINPUT VOLTAGE (V)TEMPERATURE (°C)5.55.04.54.03.53.01.101.151.201.251.3012080400−401.101.151.201.251.30Figure 13. LED Off Current vs. LED PinVoltageLED PIN VOLTAGE (V)0.20.40.60.81.0L E D C U R R E N T (m A )L E D C U R R E N T (m A )R S E T V O L T A G E (V )R S E T V O L T A G E (V )L E D O F F C U R R E N T (m A )Figure 14. EN/PWM Pull −down Current vs.V EN/PWMFigure 15. EN/PWM Threshold vs. VINENABLE VOLTAGE (V)INPUT VOLTAGE (V)54321005101520250.40.60.81.01.21.4Figure 16. Power Up from Shutdown Figure 17. Power DownFigure 18. PWM 200 Hz, 1% Duty CycleE N A B L E C U R R E N T (m A )E N A B L E T H R E S H O L D (V )Table 5. PIN DESCRIPTIONSNamePinSOIC 8−LeadPinTDFN 8−Lead FunctionLED111LED1 cathode terminalLED222LED2 cathode terminalLED333LED3 cathode terminalLED444LED4 cathode terminalGND5 5 and TAB Ground referenceEN/PWM66Device enable input and PWM control VIN77Device supply pinRSET88LED current set pin for the LED channels Pin FunctionVIN is the supply pin for the device. A small 0.1 m F ceramic bypass capacitor is optional for noisy environments. Whenever the input supply falls below the under−voltage threshold, all LED channels are automatically disabled. EN/PWM is the enable and one wire dimming input for all LED channels. Guaranteed levels of logic high and logic low are set at 1.3 V and 0.4 V respectively. When EN/PWM is initially taken high, the device becomes enabled and all LED currents are set at a gain of 100 times the current in RSET. To place the device into zero current shutdown mode, the EN/PWM pin must be held low for 4 ms typical.LED1 to LED4 provide individual regulated currents for each of the LED cathodes. There pins enter a high impedance zero current state whenver the device is placed in shutdown mode.RSET pin is connected to an external resistor to set the LED channel current. The ground side of the external resistor should be star connected to the GND of the PCB. The pin source current mirrors the current to the LED sinks. The voltage at this pin is regulated to 1.2 V.GND is the ground reference for the device. The pin must be connected to the ground plane on the PCB.TAB (TDFN 8−Lead Only) is the exposed pad underneath the package. For best thermal performance, the tab should be soldered to the PCB and connected to the ground plane.Block DiagramFigure 19. CAT4104 Functional Block Diagram4 Current Sink RegulatorsVINBasic OperationThe CAT4104 has four tightly matched current sinks to regulate LED current in each channel. The LED current in the four channels is mirrored from the current flowing through the RSET pin according to the following formula:I LED ^1001.2V R SETTable 6 shows standard resistor values for RSET and the corresponding LED current.Table 6. RSET RESISTOR SETTINGSLED Current [mA]RSET [k W ]20 6.3460 2.10100 1.271750.768Tight current regulation for all channels is possible over a wide range of input voltages and LED voltages due to independent current sensing circuitry on each channel.Each LED channel needs a minimum of 400 mV headroom to sink constant regulated current up to 175 mA.If the input supply falls below 2 V , the under −voltage lockout circuit disables all LED channels. Any unused LED channels should be left open.For applications requiring more than 175 mA current,LED channels can be tied together to sink up to a total of 700 mA from the one device.The LED channels can withstand voltages up to 25 V . This makes the device ideal for driving long strings of high power LEDs from a high voltage source.Application InformationSingle 12 V SupplyThe circuit shown in Figure 20 shows how to power the LEDs from a single 12 V supply using the CA T4104. Three external components are needed to create a lower voltage necessary for the VIN pin (below 5.5 V). The resistor R2 and zener diode Z provide a regulated voltage while the quiescent current runs through the N −Channel transistor M.The recommended parts are ON Semiconductor MM3Z6V2zener diode (in SOD −323 package), and 2N7002L N −Channel transistor (in SOT23).Figure 20. Single Supply Driving 12 LEDsDaylight DetectionThe circuit in Figure 21 shows how to use CA T4104 in an automatic light sensor application. The light sensor allows the CAT4104 to be enabled during the day and disabled during the night. Two external components are required to configure the part for ambient light detection and conserve power. Resistor R1 sets the bias for the light sensor. The recommended part is Microsemi LX1972 light sensor. For best performance, the LED light should not interfere with the light sensor.Figure 21. Daylight DetectionNightlight DetectionThe circuit shown in Figure 22 illustrates how to use the CAT4104 in an automatic night light application. The light sensor allows the CA T4104 to be disabled during the day and enabled during the night. Five external components are needed to properly configure the part for night detection.Resistor R3 limits the quiescent current through the N −Channel transistor M. Resistors R1 and R2 act as a voltage divider to create the required voltage to turn ontransistor M, which disables the CAT4104. The recommended parts are ON Semiconductor 2N7002L N −Channel transistor (in SOT23) and the Microsemi LX1972 light sensor. For best performance, the LED light should not interfere with the light sensor.Figure 22. Nightlight DetectionLED Current DeratingThe circuit shown in Figure 23 provides LED temperature derating to avoid over −driving the LED under high ambient temperatures, by reducing the LED current to protect the LED from over −heating. The positive thermo coefficient (PTC) thermistor RPTC is used for temperature sensing and should be located near the LED. As the temperature of RPTC increases, the gate voltage of the MOSFET M1decreases. This causes the transistor M1 on −resistance to increase which results in a reduction of the LED current. The circuit is powered from a single VCC voltage of 5 V . The recommended parts are Vishay 70°C thermistor PTCSS12T071DTE and ON Semiconductor 2N7002L N −Channel transistor (in SOT23).The PCB and heatsink for the LED should be designed such that the LED current is constant within the normal temperature range. But as soon as the ambient temperature exceeds a max threshold, the LED current drops to protect the LEDs from overheating.Figure 23. LED Current DeratingPower DissipationThe power dissipation (P D) of the CAT4104 can be calculated as follows:P D+(V IN I IN))S(V LEDN I LEDN)where V LEDN is the voltage at the LED pin, and I LEDN is theLED current. Combinations of high V LEDN voltage and high ambient temperature can cause the CAT4104 to enter thermal shutdown. In applications where V LEDN is high, a resistor can be inserted in series with the LED string to lower the power dissipation P D.Thermal dissipation of the junction heat consists primarily of two paths in series. The first path is the junction to the case (q JC) thermal resistance which is defined by the package style, and the second path is the case to ambient (q CA) thermal resistance, which is dependent on board layout. The overall junction to ambient (q JA) thermal resistance is equal to:q JA+q JC)q CAFor a given package style and board layout, the operating junction temperature T J is a function of the power dissipation P D, and the ambient temperature, resulting in the following equation:T J+T AMB)P D(q JC)q CA)+T AMB)P D q JA When mounted on a double−sided printed circuit board with two square inches of copper allocated for “heat spreading”, the resulting q JA is about 90°C/W for the TDFN−8 package, and 160°C/W for the SOIC−8 package. For example, at 60°C ambient temperature, the maximum power dissipation for the TDFN−8 is calculated as follow: P Dmax+T Jmax*T AMBq JA+150*6090+1WRecommended LayoutA small ceramic capacitor should be placed as close as possible to the driver VIN pin. The RSET resistor should have a Kelvin connection to the GND pin of the CAT4104. The board layout should provide good thermal dissipation through the PCB. In the case of the CAT4104VP2 in the TDFN package, a via can be used to connect the center tab to a large ground plane underneath as shown on Figure 24.Figure 24. CAT4104 Recommended Layout分销商库存信息:ONSEMICAT4104V-GT3CAT4104VP2-GT3。
CAV24C32WE-GT3;CAV24C32YE-GT3;中文规格书,Datasheet资料
CAV24C3232-Kb I2C CMOS Serial EEPROMDescriptionThe CA V24C32 is a 32−Kb CMOS Serial EEPROM devices, internally organized as 4096 words of 8 bits each.It features a 32−byte page write buffer and supports the Standard (100kHz) and Fast (400 kHz) I2C protocol.External address pins make it possible to address up to eight CA V24C32 devices on the same bus.Features•Automotive Temperature Grade 1 (−40°C to +125°C)•Supports Standard and Fast I2C Protocol•2.5 V to 5.5 V Supply V oltage Range•32−Byte Page Write Buffer•Hardware Write Protection for Entire Memory•CA V Prefix for Automotive and Other Applications Requiring Site and Change Control•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA)•Low Power CMOS Technology•1,000,000 Program/Erase Cycles•100 Year Data Retention•SOIC, TSSOP 8−lead Packages•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS CompliantFigure 1. Functional Symbol SDASCL WPV CC SSA2, A1, APIN CONFIGURATIONSSDAWPV CCV SSA2A1A01See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.ORDERING INFORMATIONSOIC−8W SUFFIXCASE 751BDSCLSOIC (W), TSSOP (Y)TSSOP−8Y SUFFIXCASE 948ALFor the location of Pin 1, please consult thecorresponding package drawing.Device Address Input A0, A1, A2Serial Data Input/OutputSDASerial Clock InputSCLWrite Protect InputWPPower SupplyV CCGroundV SSFunctionPin NamePIN FUNCTIONDEVICE MARKINGS(SOIC−8) (TSSOP−8)C32FAYMXXXC32F= Specific Device CodeA= Assembly LocationY= Production Year (Last Digit)M= Production Month (1-9, O, N, D)XXX= Last Three Digits of Assembly Lot Number G= Pb−Free Package 24C32F= Specific Device CodeA= Assembly LocationY= Production Year (Last Digit)M= Production Month (1-9, O, N, D)XXX= Last Three Digits of Assembly Lot Number G= Pb−Free Package24C32FAYMXXXGGTable 1. ABSOLUTE MAXIMUM RATINGSParameters Ratings Units Storage Temperature–65 to +150°C Voltage on any Pin with Respect to Ground (Note 1)–0.5 to +6.5V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2and WP should not exceed V CC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of V CC.Table 2. RELIABILITY CHARACTERISTICS (Note 2)Symbol Parameter Min UnitsN END (Note 3)Endurance1,000,000Program/Erase Cycles T DR Data Retention100Years2.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.3.Page Mode, V CC = 5 V, 25°C.Table 3. D.C. OPERATING CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max UnitsI CCR Read Current Read, f SCL = 400 kHz1mAI CCW Write Current Write, f SCL = 400 kHz2mAI SB Standby Current All I/O Pins at GND or V CC T A = −40°C to +125°C5m AI L I/O Pin Leakage Pin at GND or V CC2m AV IL Input Low Voltage−0.50.3 x V CC V V IH Input High Voltage A0, A1, A2 and WP0.7 x V CC V CC + 0.5VSCL and SDA0.7 x V CC 5.5 V OL Output Low Voltage V CC > 2.5 V, I OL = 3 mA0.4VTable 4. PIN IMPEDANCE CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Conditions Max Units C IN (Note 4)SDA I/O Pin Capacitance V IN = 0 V, T A = 25°C, V CC = 5.0 V8pF C IN (Note 4)Input Capacitance (other pins)V IN = 0 V, T A = 25°C, V CC = 5.0 V6pF I WP (Note 5)WP Input Current V IN< V IH, V CC = 5.5 V130m AV IN < V IH, V CC = 3.3 V120V IN < V IH, V CC = 2.5 V80V IN < V IH2I A (Note 5)Address Input Current(A0, A1, A2)Product Rev F V IN< V IH, V CC = 5.5 V50m A V IN < V IH, V CC = 3.3 V35V IN < V IH, V CC = 2.5 V25V IN > V IH24.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.5.When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relativelystrong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. T o conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC), the strong pull−down reverts to a weak current source.Table 5. A.C. CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = −40°C to +125°C, unless otherwise specified.) (Note 6)Symbol ParameterStandard FastUnits Min Max Min MaxF SCL Clock Frequency100400kHzt HD:STA START Condition Hold Time40.6m s t LOW Low Period of SCL Clock 4.7 1.3m s t HIGH High Period of SCL Clock40.6m s t SU:STA START Condition Setup Time 4.70.6m s t HD:DAT Data In Hold Time00m s t SU:DAT Data In Setup Time250100ns t R SDA and SCL Rise Time1000300ns t F (Note 6)SDA and SCL Fall Time300300ns t SU:STO STOP Condition Setup Time40.6m s t BUF Bus Free Time Between STOP and START 4.7 1.3m s t AA SCL Low to Data Out Valid 3.50.9m s t DH Data Out Hold Time100100ns T i (Note 6)Noise Pulse Filtered at SCL and SDA Inputs100100ns t SU:WP WP Setup Time00m s t HD:WP WP Hold Time 2.5 2.5m s t WR Write Cycle Time55ms t PU (Notes 7, 8)Power−up to Ready Mode11ms6.Test conditions according to “AC Test Conditions” table.7.Tested initially and after a design or process change that affects this parameter.8.t PU is the delay between the time V CC is stable and the device is ready to accept commands.Table 6. A.C. TEST CONDITIONSInput Drive Levels0.2 x V CC to 0.8 x V CCInput Rise and Fall Time≤ 50 nsInput Reference Levels0.3 x V CC, 0.7 x V CCOutput Reference Level0.5 x V CCOutput Test Load Current Source I OL = 3 mA; C L = 100 pFPower-On Reset (POR)Each CA V24C32 incorporates Power-On Reset (POR)circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after V CC exceeds the POR trigger level and will power down into Reset mode when V CC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power.Pin DescriptionSCL: The Serial Clock input pin accepts the clock signal generated by the Master.SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.A 0, A 1 and A 2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally.WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally.Functional DescriptionThe CA V24C32 supports the Inter-Integrated Circuit (I 2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CA V24C32operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles.I 2C Bus ProtocolThe 2-wire I 2C bus consists of two lines, SCL and SDA,connected to the V CC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH.START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH.Device AddressingThe Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CA V24C32, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A 2, A 1 and A 0, must match the logic state of the similarly named input pins. The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3).AcknowledgeDuring the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5.START CONDITIONSTOP CONDITIONSDASCLFigure 2. Start/Stop TimingFigure 3. Slave Address BitsDEVICE ADDRESSFigure 4. Acknowledge TimingSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVER≥ t SU:DAT )Figure 5. Bus TimingSCLSDA INSDA OUTWRITE OPERATIONSByte WriteTo write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (t WR ), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 7).Page WriteThe Byte Write operation can be expanded to Page Write,by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (t WR ).Acknowledge PollingAs soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (t WR ) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK.Hardware Write ProtectionWith the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 9). If the WP pin is HIGH during the strobe interval,the Slave will not acknowledge the data byte and the Write request will be rejected.Delivery StateThe CA V24C32 is shipped erased, i.e., all bytes are FFh.SLAVE ADDRESSSA ****C KA C KA C KS T O P PST ARTA CKBUS ACTIVITY:MASTER SLAVEADDRESS BYTE ADDRESS BYTE DAT A BYTE Figure 6. Byte Write Sequence*a 15 − a 12 are don’t care bitsa 15 − a 8a 7 − a 0d 7 − d 0Figure 7. Write Cycle TimingSTOPCONDITIONSTARTCONDITIONADDRESSSCLSDASLAVE ADDRESSSA C K A C K C K ST ARTC K S T O C KC K C K BUSACTIVITY:MASTER SLAVEn = 1ADDRESS BYTE ADDRESS BYTEDATA BYTE DATA BYTE DATA BYTE Figure 8. Page Write SequenceP ≤ 31Figure 9. WP TimingADDRESS BYTE DATA BYTESCLSDA WPREAD OPERATIONSImmediate ReadTo read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address.After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode.Selective ReadTo read data residing at a speci fic address, the selected address must first be loaded into the internal address register.This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the ByteWrite sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11).Sequential ReadIf, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory.Figure 10. Immediate Read Sequence and TimingSCL SDA 8th Bit STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KDATA BYTEN OA C K S T O P PS T A R T BUS ACTIVITYMASTERSLAVEFigure 11. Selective Read SequenceSLAVE ADDRESS SA C KA C KA C K ST ARTSLAVE SA C KS T A R T PS T O P ADDRESS BYTE ADDRESS BYTE ADDRESSN O A C KBYTEBUS ACTIVITY:MASTER SLAVEFigure 12. Sequential Read SequenceS T O SLAVE C KA C A C N O A C A C BYTE n BYTE n+1BYTE n+2BYTE n+xBUS ACTIVITY:MASTERSLAVESOIC 8, 150 mils CASE 751BD −01ISSUE OIDENTIFICATIONTOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters. Angles in degrees.(2) Complies with JEDEC MS-012.SYMBOLMIN NOMMAX θA A1b cD E E1e h 0º8º0.100.330.190.254.805.803.801.27 BSC1.750.250.510.250.505.006.204.00L0.40 1.271.35TSSOP8, 4.4x3CASE 948AL −01ISSUE OA1TOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters. Angles in degrees.(2) Complies with JEDEC MO-153.SYMBOLθMINNOM MAXA A1A2bc D E E1e L10º8ºL 0.050.800.190.090.502.906.304.300.65 BSC 1.00 REF1.200.151.050.300.200.753.106.504.500.900.603.006.404.40Example of Ordering InformationCAV24C32WE −GT3 (Note 11)Prefix Device #Suffix 9.All packages are RoHS-compliant (Lead-free, Halogen-free).10.The standard lead finish is NiPdAu.11.The device used in the above example is a CAV24C32WE −GT3 (SOIC, Automotive Temperature, NiPdAu, Tape & Reel, 3,000/Reel).12.For other package options, please contact your nearest ON Semiconductor Sales office.13.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.ON Semiconductor is licensed by Philips Corporation to carry the I 2C Bus Protocol.PUBLICATION ORDERING INFORMATION分销商库存信息:ONSEMICAV24C32WE-GT3CAV24C32YE-GT3。
和泉GT3系列定时器
电源
2-7 设置时间 （POWER）
5-8
定时（NC）
触点 6-8
（NO）
• 定时触点由设置的时 间重复动作 - 复位。 （负荷比 1 ∶ 1）
• 启动时 NO 触点 ON。 • 瞬时触点施加电源时，
动作。
指示 POW 器 OUT
动作
GT3 系列 多模式型·模拟设定式
动作特性图 GT3A-2∗ 定时 SPDT ＋瞬时 SPDT 输出 3 4 6 5 7（～）／（＋）
闪烁（OFF 启动）
项目 端子号
电源
2-7 设置时间 （POWER）
5-8
定时（NC）
触点 6-8
（NO）
• 定时触点由设置的时 间重复动作 - 复位。 （负荷比 1 ∶ 1）
• 启动时 NO 触点 OFF。 • 瞬时触点施加电源时，
动作。
指示 POW 器 OUT
动作
闪烁 ON（ON 启动） 项目 端子号
绝缘电阻
耐电压
耐振动 抗冲击性 保护等级
0.1 秒～ 180 小时 2（IEC60664-1） III（IEC60664-1） 100 ～ 240V AC（50/60Hz） 24V AC（50/60Hz）/24V DC 85 ～ 264V AC（50/60Hz） 20.4 ～ 26.4V AC（50/60Hz）/21.6 ～ 26.4V DC 额定电压 X 10% 以上 － 10 ～ ＋ 50℃（无结冰） － 30 ～ ＋ 70℃（无结冰） 35 ～ 85%RH（无结露） 0 ～ 2,000m（使用时）、0 ～ 3,000m（运输时） 60ms 以下 ±0.2%、±10ms 以内（注） ±0.2%、±10ms 以内（注） ±0.2%、±10ms 以内（注） ±10% 以内 100MΩ 以上（500V DC 兆欧表） 电源电压端子和输出触点间 ：2,000V AC · 1 分钟 输出继电器的异极触点间 ：2,000V AC · 1 分钟 输出继电器的同极触点间 ： 750V AC · 1 分钟（GT3A-1, -2）
twincat3使用手册
twincat3使用手册【最新版】目录1.TwinCAT3 简介2.TwinCAT3 的功能3.TwinCAT3 的使用方法4.TwinCAT3 的优点与局限性5.总结正文1.TwinCAT3 简介TwinCAT3 是一款由德国倍福自动化有限公司开发的高级工业自动化软件平台，主要用于工业控制、监控和数据采集。
它具有强大的实时性和开放性，可以运行在各种常见操作系统上，支持多种编程语言，如 C、C++和 Python 等。
TwinCAT3 广泛应用于工厂自动化、过程控制、机器人控制等领域，为用户提供了全面的解决方案。
2.TwinCAT3 的功能TwinCAT3 具有以下主要功能：(1) 实时控制：TwinCAT3 支持实时控制，可以对工业现场的设备进行精确控制，响应速度快，适用于高速、高精度的工业生产环境。
(2) 数据采集：TwinCAT3 可以实时采集工业现场的数据，并将数据传输到上位机进行分析和处理，有助于优化生产过程和提高产品质量。
(3) 通讯功能：TwinCAT3 支持多种通讯协议，如 Profibus、Profinet、CAN、EtherCAT 等，可以实现设备间的数据交换和信息共享。
(4) 远程控制：TwinCAT3 支持远程控制功能，可以通过网络对工业现场的设备进行控制，便于设备的监控和管理。
(5) 强大的扩展性：TwinCAT3 具有丰富的软件库和工具，支持多种编程语言，可以根据用户需求进行定制和扩展。
3.TwinCAT3 的使用方法(1) 安装 TwinCAT3：首先需要在官方网站下载 TwinCAT3 软件，并按照安装指南进行安装。
(2) 配置 TwinCAT3：根据实际应用场景，对 TwinCAT3 进行配置，包括设置通讯协议、数据采集、设备连接等。
(3) 编写控制程序：使用 TwinCAT3 提供的编程工具，编写控制程序，实现设备的实时控制和数据采集。
(4) 调试和运行：将编写好的控制程序下载到现场设备，进行调试和运行。
Victron EM24 Ethernet 三相功率能量计手册说明书
ENGLISHEnergy Meter ManualEM24 Ethernetrev 05 - 08/2023This manual is also available in HTML5Table of Contents1. Introduction (1)1.1. Features (1)2. Installation and configuration (2)2.1. AC wiring (2)2.1.1. Configuration options (2)2.1.2. System examples (2)2.2. GX device configuration (4)3. FAQ (6)The Victron EM24 Ethernet is a standard device to measure the power and energy of a 3-phase application, for example at the distribution box or to measure the output of a PV Inverter, AC Genset or the output of an inverter and inverter/charger.Its data will be displayed on a GX device and our VRM portal.1.1. FeaturesThe EM24 Ethernet can be configured for four different roles in a GX device such as the Cerbo GX:1.As a Grid meter and used as control input for an ESS System.2.To measure the output of a PV Inverter.3.To measure the output of a AC Genset.4.As a AC meter to measure the output of an inverter or inverter/charger.It offers one option for connection to a GX device:1. A wired ethernet connection to the local network in such a way that the GX device can reach it.2.1. AC wiring2.1.1. Configuration optionsThe configuration option of either Grid Meter, PV Inverter, Generator or AC Meter is set in the GX device. For details on GX device configuration see the GX device configuration [4] chapter. This selection will effect how the system should be wired and how the information received from the meter is displayed on the screen.See below diagrams for the different wiring options:2.1.2. System examplesExample diagramsL1L2L3NPEL1L2L3NPEEM24 3-phase wiringWhen used to measure a PV Inverter, terminals 1, 4 and 7 should face the PV inverter to ensure correctdirection of current and power.Single-phase, single functionL1NL1NEM24 connected as a single-phase, single function grid meterNote the jumper between terminals 1 and 4. You do not need this connection if you have the version AV2 of the sensor.The diagrams show the wiring when used as a grid meter.To measure a single-phase PV inverter in a 3-phase system, connect all 3 phases to the grid phasing terminals (3, 6 and 9). Now you can chose on which phase you want the PV inverter by connecting the L1 line of the PV inverter to terminal 1, 4 or 7.Single-phase, dual functionIf you want to use a three-phase meter in a single-phase installation to measure the grid on one input of the meter and the output of the PV inverter on another input of the energy meter, make sure that the energy meter uses L1 and the PV inverter uses L2.Front selectorChange the front selector so it is not in the locked state. This allows it to be automatically configured by the GX Device. The front selector is located next to the display as indicated in the image above.2.2. GX device configurationAfter proper connection and powering up, the meter(s) will be visible on the GX device in the Settings → Energy meters menu:Single Energy Meter in the Energy meters menu Two Energy Meters in the Energy meters menuAfter selecting an Energy Meter, you have to set the Role and Phase type. Press the space bar or right click to get to the Phase type and Role menu:For the ET112 only Single phase option is displayed Depending on the application, the role is set hereSelect either Role or Phase type and press the space bar to make changes:Select the Role according to the application Selection menu for Single and Multi phase typeSingle-phase, single function and single-phase, dual function mode setup:Single-phase, single function Single-phase, dual function to measure grid on L1 and a PVInverter on L2After all settings have been made, the Energy Meter now appears with the relevant data in the device list of the GX device:Or configured to measure energy consumption from the grid Energy meter set to measure AC loads on the AC output ofthe inverter/chargerRight-click or press the spacebar to get to the Energy Meter overview with all relevant data on energy consumption and its generation in all phases. At the bottom of the menu, the role of the Energy Meter can be set via the Setup menu. The data used for communication can be read out via the Device menu. You can also set up a custom name for the Energy Meter there:Detailed overview page of a 3-phase Grid meter Always be informed about all details, to the second Custom name configuration Quickly change rolesQ1: Can I combine three ET112s for a 3-phase system?No. Use a real 3-phase meter.Q2: Can I use other meters, for example from other brands?No.Q3: I already have a Fronius SmartGrid meter, can I use that?No.Q4: What are the differences between the various 3-phase meters?•EM540 - REL200100100 - Carlo Gavazzi EM540DINAV23XS1X•ET112 - REL300100000 - Carlo Gavazzi ET112-DIN.AV01.X.S1.X•ET340 - REL300300000 - Carlo Gavazzi ET340-DIN.AV23.X.S1.XDifferences:•The ET meters have no display. The only thing they have is an LED, which blinks in case of active communication.•The ET meters have two RJ45 sockets, but they are not used with the Victron RS485 to USB interface. Note the possible confusion because of yet another RJ45 socket in the Victron world though. Don't mix that with VE.Bus, VE.Can or . Besides the RJ45 sockets, the meters still also have screw terminals access below the sockets for the RS485 wiring, which is how we advise to connect a meter to the RS485 to USB interface and then a GX device.•Since there is no display, the modbus address can no longer be changed on the meter. Combining multiple of those meters on one RS485 network is therefore not supported by Victron. You are advised to use multiple RS485 to USB interfaces.3-phase meter only:•Measuring energy from single-phase PV Inverter on the second phase of a 3-phase meter actually works.Q5: Will you keep shipping both 3-phase meters? (ET340 & EM540)Yes. There are still situations suitable for each. See Q8.Q6: Can I buy those meters directly from Carlo Gavazzi instead of from you?Yes. That is also why we make no secret of the CG part numbers.Q7: I want to use Current Transformers (CTs), is that possible?Yes. You can buy a CG EM24DINAV53DISX or a CG EM530DINAV53XS1X directly from Carlo Gavazzi or one of their distributors. Even though Victron does not stock that type of meter, we do support it in our software.Q8: What’s the difference between ET340 and EM540 in 3-phase systems?These meters have a different way of calculating the total of energy imported and exported.In the ET340, the energy imported and exported is counted at each individual phase and then the Total is provided from the sum of those values.In the EM540, the energy imported and exported is counted as a total power, with net differential readings from each phase cancelling each other out.Which Energy Meter is most suitable depends on the measuring configuration in your country. It is most common in Austria and Germany for example to only be billed for the total in a 3-phase system. So it is more accurate to use an EM540 to match the billing.So if you are exporting from one phase and importing from another phase after the energy meter, but before the billing meter, then you will not be charged for this, and the meter should not count it as an import and an export.This is also how Victron’s phase compensation feature works, to make the most of the cost savings for an ESS system when there is a differential in generation and load across different phases.Q9: Can I use an isolated USB-RS485 interface?Yes. The interfaces we sell are non isolated; suitable for most use cases.In case an isolated one is needed; purchase it directly from Hjelmslund Electronics.•USB485-STIXL : Isolated USB to RS485 converterQ10: Can I use Victron Energy Meters instead of a Victron Inverter/Charger to make use of a GX device (e.g. Cerbo GX), VRM and other features?Energy Meters are intended to supplement a Victron Inverter/Charger in the system. Energy Meters are currently limited in their potential applications. Each Energy Meter is only intended to provide a specific piece of additional information - total loads on AC input and grid import/export, or AC PV inverter and AC generator production without network communications.However, it is perfectly possible to initially use just a GX device together with an Energy Meter to determine and record the consumption, for example of houses/buildings, heating systems with heat pumps, ventilating and air conditioning or production facilities. Afterwards, the collected data can be evaluated and a decision can be made about the dimensioning of the required Victron inverter/charger(s), the solar system and the type, size and number of batteries.With GX device firmware version 2.80 and later, they can also be used for other purposes e.g. to measure specific, arbitrary AC loads or circuits for example. But this should not be considered a replacement to having a Victron Inverter/Charger. Attempting to use other brand battery inverters and trying to substitute their lack of data connectivity to the GX device by using Energy Meters will not work as expected.。
CAT1023WI-25-GT3资料
CAT1021, CAT1022, CAT1023Supervisory Circuits with I 2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog TimerFEATURESPrecision Power Supply Voltage Monitor — 5V, 3.3V and 3V systems — Five threshold voltage options Watchdog TimerActive High or Low Reset— Valid reset guaranteed at V CC = 1V 400kHz I 2C Bus 2.7V to 5.5V Operation Low power CMOS technology 16-Byte Page Write BufferBuilt-in inadvertent write protection — WP pin (CAT1021)1,000,000 Program/Erase cycles Manual Reset Input 100 year data retentionIndustrial and extended temperature ranges 8-pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm foot-print) packages — TDFN max height is 0.8mmFor Ordering Information details, see page 19.DESCRIPTIONThe CAT1021, CAT1022 and CAT1023 are complete memory and supervisory solutions for microcontroller-based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I 2C bus.The CAT1021 and CAT1023 provide a precision V CC sense circuit and two open drain outputs: one (RESET)drives high and the other (RESET¯¯¯¯¯¯) drives low whenever V CC falls below the reset threshold voltage. TheCAT1022 has only a RESET¯¯¯¯¯¯ output and does not have a Write Protect input. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high.All supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. For the CAT1021 and CAT1022, the watchdog timer monitors the SDA signal. The CAT1023 has a separate watchdog timer interrupt input pin, WDI.The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers andother ICs is simple. In addition, the RESET¯¯¯¯¯¯ pin or a separate input, MR¯¯¯, can be used as an input for push-button manual reset capability.The on-chip, 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a V CC sense circuit that prevents writes to memory whenever V CC falls below the reset threshold or until VCC reaches the reset threshold during power up.Available packages include an 8-pin DIP and surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP packages. The TDFN package thickness is 0.8mm maximum. TDFN footprint options are 3x3mm.CAT1021, CAT1022, CAT1023BLOCK DIAGRAMTHRESHOLD VOLTAGE OPTIONPart DashNumberMinimum ThresholdMaximum Threshold-45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70PIN CONFIGURATIONDIP Package (L ) SOIC Package (W ) TSSOP Package (Y ) MSOP Package (Z )MR ¯¯¯ 1 8V CC RESET¯¯¯¯¯¯ 2 7 RESET WP 3 6 SCLV SS 45 SDACAT1021MR ¯¯¯ 1 8 V CC RESET¯¯¯¯¯¯ 2 7 NC NC 3 6 SCLV SS 45 SDACAT1022MR ¯¯¯ 1 8 V CC RESET¯¯¯¯¯¯ 2 7 WDI RESET 3 6 SCLV SS 45 SDACAT1023(Bottom View)TDFN Package: 3mm x 3mm 0.8mm maximum height - (ZD4)V CCMR ¯¯¯ RESET RESET ¯¯¯¯¯¯ SCL WPSDA V SSV CC MR ¯¯¯ RESET ¯¯¯¯¯¯ SCL NCSDA V SSV CCMR ¯¯¯ WDI RESET ¯¯¯¯¯¯ SCL RESETSDA V SSEXTERNAL LO ADSCLRESET(CAT1021/23)CAT1021, CAT1022, CAT1023PIN DESCRIPTIONRESET/RESET¯¯¯¯¯¯: RESET OUTPUT(RESET CAT1021/23 Only)These are open drain pins and RESET¯¯¯¯¯¯ can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET¯¯¯¯¯¯ pin must be connected through a pull-up resistor.SDA: SERIAL DATA ADDRESSThe bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.SCL: SERIAL CLOCKSerial clock input.MR¯¯¯: MANUAL RESET INPUTManual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor.WP (CAT1021 Only): WRITE PROTECT INPUT When WP input is tied to V SS or left unconnected write operations to the entire array are allowed. When tied to V CC, the entire array is protected. This input has an internal pull down resistor.WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or lowto high does not occur every 1.6 seconds, the RESET outputs will be driven active. PIN FUNCTIONPinNameFunctionNC No ConnectRESET¯¯¯¯¯¯Active Low Reset Input/OutputV SS GroundSDA Serial Data/AddressSCL Clock InputRESET Active High Reset Output (CAT1021/23) V CC Power SupplyWP Write Protect (CAT1021 only)MR¯¯¯Manual Reset InputWDI Watchdog Timer Interrupt (CAT1023) OPERATING TEMPERATURE RANGEIndustrial-40ºC to 85ºCExtended -40ºC to 125ºCCAT102X FAMILY OVERVIEWDeviceManualResetInput PinWatchdogWatchdogMonitorPinWriteProtectionPinIndependentAuxiliaryVoltage SenseRESET:Active Highand LOWEEPROMCAT1021 SDA 2k CAT1022 SDA 2k CAT1023 WDI 2k CAT1024 2k CAT1025 2k CAT1026 2k CAT1027 WDI 2kFor supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.CAT1021, CAT1022, CAT1023ABSOLUTE MAXIMUM RATINGS(1)Parameters Ratings UnitsTemperature Under Bias –55 to +125 ºCStorage Temperature –65 to +150 ºCVoltage on any Pin with Respect to Ground(2)–2.0 to V CC + 2.0 VV CC with Respect to Ground –2.0 to 7.0 VPackage Power Dissipation Capability (T A = 25°C) 1.0 WLead Soldering Temperature (10 secs) 300 ºCOutput Short Circuit Current(3) 100mA D.C. OPERATING CHARACTERISTICSV CC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.Symbol Parameter TestConditions Min Typ Max UnitsI LI Input Leakage Current V IN = GND to Vcc -2 10 µAI LO Output Leakage Current V IN = GND to Vcc -10 10 µAI CC1Power Supply Current (Write) f SCL = 400kHzV CC = 5.5V3 mAI CC2Power Supply Current (Read) f SCL = 400kHzV CC = 5.5V1 mAI SB StandbyCurrent Vcc = 5.5V,V IN = GND or Vcc60 µAV IL(4)Input Low Voltage -0.5 0.3 x Vcc V V IH(4)Input High Voltage 0.7 x Vcc Vcc + 0.5 VV OL Output Low Voltage(SDA, RESET¯¯¯¯¯¯)I OL = 3mAV CC = 2.7V0.4 VV OH Output High Voltage(RESET)I OH = -0.4mAV CC = 2.7VVcc - 0.75 VCAT102x-45(V CC = 5.0V)4.50 4.75 VCAT102x-42(V CC = 5.0V)4.25 4.50CAT102x-30(V CC = 3.3V)3.00 3.15CAT102x-28(V CC = 3.3V)2.853.00V TH ResetThresholdCAT102x-25(V CC = 3.0V)2.55 2.70V RVALID Reset Output Valid V CC Voltage 1.00 V V RT(5)Reset Threshold Hysteresis 15 mV Notes:(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC +2.0V for periods of less than 20 ns.(3) Output shorted for no more than one second. No more than one output shorted at a time.(4) V IL min and V IH max are reference values only and are not tested.(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.CAT1021, CAT1022, CAT1023CAPACITANCET A = 25ºC, f = 1.0MHz, V CC = 5VSymbol Test TestConditions Max Units Capacitance V OUT = 0V 8 pFC OUT(1) OutputC IN(1)Input Capacitance V IN = 0V 6 pFAC CHARACTERISTICSV CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.Memory Read & Write Cycle(2)Symbol Parameter Min Max Units Frequency 400 kHzf SCL Clockt SP Input Filter Spike Suppression (SDA, SCL) 100 ns t LOW Clock Low Period 1.3 µsPeriod 0.6 µs t HIGH ClockHight R(1)SDA and SCL Rise Time 300 ns t F(1)SDA and SCL Fall Time 300 ns t HD; STA Start Condition Hold Time 0.6 µs t SU; STA Start Condition Setup Time (for a Repeated Start) 0.6 µs t HD; DAT Data Input Hold Time 0 ns t SU; DAT Data Input Setup Time 100 ns t SU; STO Stop Condition Setup Time 0.6 µs t AA SCL Low to Data Out Valid 900 ns t DH Data Out Hold Time 50 ns t BUF(1)Time the Bus must be Free Before a New Transmission Can Start 1.3 µs t WC(3)Write Cycle Time (Byte or Page) 5 ms Notes:(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.(2) Test Conditions according to “AC Test Conditions” table.(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During thewrite cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.CAT1021, CAT1022, CAT1023RESET CIRCUIT AC CHARACTERISTICSConditions Min Typ Max Units Symbol Parameter Testt PURST Power-Up Reset Timeout Note 2 130 200 270 ms t RDP V TH to RESET output Delay Note 3 5 µs t GLITCH V CC Glitch Reject Pulse Width Note 4, 5 30 nsMR Glitch Manual Reset Glitch Immunity Note 1 100 ns t MRW MR Pulse Width Note 1 5 µs t MRD MR Input to RESET Output Delay Note 1 1 µs t WD Watchdog Timeout Note 1 1.0 1.6 2.1 sec POWER-UP TIMING (5), (6)Symbol Parameter Test Conditions Min Typ Max Units t PUR Power-Up to Read Operation 270 ms t PUW Power-Up to Write Operation 270 msAC TEST CONDITIONSParameter Test ConditionsInput Pulse Voltages 0.2V CC to 0.8V CCInput Rise and Fall times 10nsInput Reference Voltages 0.3V CC , 0.7V CCOutput Reference Voltages 0.5V CCOutput Load Current Source: I OL = 3mA; C L = 100pFRELIABILITY CHARACTERISTICSSymbol Parameter Reference Test Method Min Max Units N END(5)Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte T DR(5)Data Retention MIL-STD-883, Test Method 1008 100 Years V ZAP(5)ESD Susceptibility MIL-STD-883, Test Method 3015 2000 VoltsI LTH(5)(7)Latch-Up JEDEC Standard 17 100 mA Notes:(1) Test Conditions according to “AC Test Conditions” table.(2) Power-up, Input Reference Voltage V CC = V TH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table(3) Power-Down, Input Reference Voltage V CC = V TH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table(4) V CC Glitch Reference Voltage = V THmin; Based on characterization data(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.(6) t PUR and t PUW are the delays required from the time V CC is stable until the specified memory operation can be initiated.(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V CC + 1V.CAT1021, CAT1022, CAT1023DEVICE OPERATIONReset Controller DescriptionThe CAT1021/22/23 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs.During power-up, the RESET outputs remain active until V CC reaches the V TH threshold and will continue driving the outputs for approximately 200ms (t PURST) after reaching V TH. After the t PURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors.During power-down, the RESET outputs will be active when V CC falls below V TH. The RESET¯¯¯¯¯¯ output will be valid so long as V CC is >1.0V (V RVALID). The device is designed to ignore the fast negative going V CC transient pulses (glitches).Reset output timing is shown in Figure 1.Manual Reset OperationThe RESET¯¯¯¯¯¯ pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET¯¯¯¯¯¯ input will initiate a reset timeout after detecting a high to low transition.When RESET¯¯¯¯¯¯ I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200ms, Reset outputs will remain active at least 200ms.The CAT1021/22/23 also have a separate manual reset input. Driving the MR¯¯¯ input low by connecting a pushbutton (normally open) from MR¯¯¯ pin to GND will generate a reset condition. The input has an internal pull up resistor.Reset remains asserted while MR¯¯¯ is low and for the Reset Timeout period after MR¯¯¯ input has gone high. Glitches shorter than 100ns on MR¯¯¯ input will not ge-nerate a reset pulse. No external debouncing circuits are required. Manual reset operation using MR¯¯¯ input is shown in Figure 2. Hardware Data ProtectionThe CAT1021/22/23 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before V CC reaches the minimum value of 2V.In addition, the CAT1021 includes a Write Protection Input which when tied to V CC will disable any write operations to the device.Watchdog TimerThe Watchdog Timer provides an independent protection for microcontrollers. During a system failure, CAT1021/22/23 devices will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. The CAT1023 is designed with the Watchdog timer feature on the WDI pin. The CAT1021 and CAT1022 monitor the SDA line. If WDI or SDA does not toggle within a 1.6 second interval, the reset condition will be generated on the reset outputs. The watchdog timer is cleared by any transition on a monitored line.As long as reset signal is asserted, the watchdog timer will not count and will stay cleared.CAT1021, CAT1022, CAT1023Figure 1. RESET Output TimingFigure 2: MR¯¯¯ Operation and TimingCAT1021, CAT1022, CAT1023EMBEDDED EEPROM OPERATIONThe CAT1021/22/23 feature a 2-kbit embedded serial EEPROM that supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I 2C BUS PROTOCOLThe features of the I 2C bus protocol are defined as follows:(1) Data transfer may be initiated only when the busis not busy.(2) During a data transfer, the data line must remainstable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START CONDITIONThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition ofSDA when SCL is HIGH. The CAT1021/22/23 monitor the SDA and SCL lines and will not respond until this condition is met. STOP CONDITIONA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.DEVICE ADDRESSINGThe Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the Master sends a START condition and the slave address byte, the CAT1021/22/23 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1021/22/23 then perform a Read orWrite operation depending on the R/W¯¯ bit.Figure 3. Bus TimingFigure 4. Write Cycle TimingSCLSDA INSDA OUTSTOPCONDITIONSTARTCONDITIONADDRESSSCLSDACAT1021, CAT1022, CAT1023ACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.All devices respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte.When a device begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the device will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W¯¯ bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknow-ledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The device acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.Figure 5. Start/Stop TimingFigure 6. Acknowledge TimingFigure 7: Slave Address BitsSTART BITSDASTOP BITSCLACKNOWLEDGESTARTSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVER1010000R/WDefault ConfigurationCAT1021, CAT1022, CAT1023Page WriteThe CAT1021/22/23 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1021/22/23 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten.When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1021/22/23 in a single write cycle.Figure 8. Byte Write TimingFigure 9: Page Write TimingBYTEADDRESSSLAVEADDRESSSACKACKDA T AACKSTOPPBUS ACTIVITY:MASTERSDA LINE S T A R TBUS ACTIVITY:MASTERSDA LINEBYTECKCKCKSTOCKCKSTARSLAVECAT1021, CAT1022, CAT1023Doc. No. 3009 Rev. L12© 2007 Catalyst Semiconductor, Inc.Acknowledge PollingDisabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1021/22/23 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation.WRITE PROTECTION PIN (WP)The Write Protection feature (CAT1021 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to V CC , the entire memory array is protected and becomes read only. The CAT1021 will accept both slave and byte addre-sses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ OPERATIONSThe READ operation for the CAT1021/22/23 is initiated in the same manner as the write operation with oneexception, the R/W¯¯ bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.Figure 10. Immediate Address Read TimingSCL SDA 8TH BI T STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KDA TAN O A C K S T O P PBUS ACTIVIT Y:MASTERSDA LINES T A R TCAT1021, CAT1022, CAT1023Immediate/Current Address ReadThe CAT1021/22/23 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1021/22/23 receives its slave address infor-mation (with the R/W¯¯ bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random ReadSelective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1021/22/23 acknowledges, the Master device sends the START condition and the slave addressagain, this time with the R/W¯¯ bit set to one. The CAT1021/22/23 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.Sequential ReadThe Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1021/22/23 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1021/22/23 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition.The data being transmitted from the CAT1021/22/23 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1021/22/23 address bits so that the entire memory array can be read during one operation.Figure 11. Selective Read TimingFigure 12. Sequential Read TimingSLAVE ADDRESSSA C KN O A C KS T O P PBUS ACTIVITY:MASTERSDA LINES T A R T BYTE ADDRESS (n)SA C KDA T A nSLAVE ADDRESSA C KS T A RT BUS ACTIVITY:MASTERSDA LINEC KC KC KS T O O A C KC KSLAVECAT1021, CAT1022, CAT1023 Doc. No. 3009 Rev. L14© 2007 Catalyst Semiconductor, Inc.PACKAGE OUTLINES8-LEAD 300 MIL WIDE PLASTIC DIP (L)Notes :(1) All dimensions are in millimeters.(2) Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.ecSYMBOLA A1b b2D E E1e eB LMIN 0.380.369.027.626.09 6.357.872.923.81NOM 0.46 1.771.147.872.54 BSCMAX 4.57A2 3.05 3.810.56c 0.210.260.3510.168.257.119.65CAT1021, CAT1022, CAT10238-LEAD 150 MIL SOIC (W)Notes:(1) All dimensions are in millimeters.(2) Complies with JEDEC specification MS-012 dimensions.SYMBOLA1A b C D E E1h L MIN 0.101.350.334.805.803.800.250.40NOM 0.250.19MAX 0.251.750.515.006.204.00e 1.27 BSC0.501.27q10°8°eCCAT1021, CAT1022, CAT1023Doc. No. 3009 Rev. L16© 2007 Catalyst Semiconductor, Inc.8-LEAD TSSOP (V)Notes:(1) All dimensions are in millimeters. (2) Complies with JEDEC Standard MO-153q1SEE DETAIL AcSYMBOL A A1A2b c D E E1e L q1MIN 0.050.800.092.906.30 6.44.300.008.00NOM 0.900.300.19 3.004.400.600.750.50MAX 1.200.151.050.203.106.504.500.65 BSCCAT1021, CAT1022, CAT10238-LEAD MSOP (Z)Notes:(1) All dimensions are in millimeters.(2) This part is compliant with JEDEC Specification MO-187 Variations AA.SYMBOLMIN NOMMAX A 1.1A10.050.100.15A20.750.850.95b 0.280.330.38c D 2.90 3.00 3.10E 4.80 4.90 5.00E1 2.903.00 3.10e 0.65BSCL 0.350.450.55L1L2Ө0º6ºCAT1021, CAT1022, CAT1023Doc. No. 3009 Rev. L18© 2007 Catalyst Semiconductor, Inc.TDFN 3 x 3 PACKAGE (ZD4)Notes: (1) All dimentions in mm. Angels in degrees. (2) Complies to JEDEC MO-229 / WEEC. (3) Coplanarity shall not exceed 0.10mm. (4) Warpage shall not exceed 0.10mm.(5)Package lenght / package width are considered as special characteristic(s).。
诺瓦科技WIFI-LED控制卡T3规格书
诺瓦科技WIFI-LED控制卡T3规格书Taurus SeriesMultimedia PlayersT 3Specifications Document Version:V1.3.2Document Number:NS120100345Table of Contents Table of Contents (ii)1 Overview (1)1.1 Introduction ..................................................................................................................................................1 1.2Application (1)2 Features (3)2.1 Synchronization mechanism for multi-screenplaying (3)2.2 Powerful Processing Capability (3)2.3 Omnidirectional Control Plan (3)2.4 Dual-Wi-Fi Mode ..........................................................................................................................................4 2.4.1 Wi-Fi APMode .......................................................................................................................................... 5 2.4.2 Wi-Fi Sta Mode .. (5)2.4.3 Wi-Fi AP+Sta Mode (5)2.5 Redundant Backup (6)3 Hardware Structure (7)3.1 Appearance (7)3.2 Dimensions (9)4 Software Structure (10)4.1 System Software (10)4.2 Related Configuration Software (10)5 Product Specifications (11)6 Audio and Video Decoder Specifications (13)6.1 Image .........................................................................................................................................................6.1.1 Decoder (13)6.1.2 Encoder (13)6.2 Audio (14)6.2.1 Decoder (14)6.2.2 Encoder (14)6.3 Video (15)6.3.1 Decoder (15)6.3.2 Encoder ..................................................................................................................................................16www.novastar.techiiTaurus Series Multimedia PlayersT3 Specifications 1 Overview1 Overview 1.1 IntroductionTaurus series products are NovaStar'ssecond generation of multimedia playersdedicated to small and medium-sizedfull-color LED displays.T3 of the Taurus series products(hereinafter referred to as “T3”) featurefollowing advantages, better satisfyingu sers’ requirements:●Loading capacity up to 650,000 pixels●Synchronization mechanism formulti-screen playing●Powerful processing capability●Omnidirectional control plan●Dual-Wi-Fi mode ●Redundant backupNote:If the user has a high demand onsynchronization, the time synchronizationmodule is recommended. For details,please consult our technical staff.In addition to solution publishing andscreen control via PC, mobile phones andLAN, the omnidirectional control plan alsosupports remote centralized publishingand monitoring.1.2 ApplicationTaurus series products can be widelyused in LED commercial display field,such as bar screen, chain store screen,advertising machine, mirror screen, retailstore screen, door head screen, on boardscreen and the screen requiring no PC.Classification of Taurus’application cases is shown in1 OverviewT3 Specifications2 Features 2.1 Synchronization mechanism for multi-screen playingThe T3 support switching on/off functionof synchronous display.When synchronous display is enabled, thesame content can be played on differentdisplays synchronously if the time ofdifferent T3 units are synchronous withone another and the same solution isbeing played.2.2 Powerful Processing CapabilityThe T3 feature powerful hardwareprocessing capability:● 1.5 GHz eight-core processor●Support for H.265 4K high-definition●Support for 1080P video hardwaredecoding● 2 GB operating memory●8 GB on-board internal storage spacewith 4 GB available for users2.3 Omnidirectional Control Plancontrol plan featuring following advantages:●More efficient: Use the cloud service mode to process services through a uniform platform. For example, VNNOX is used to edit and publish solutions, and NovaiCare is used to centrally monitor display status.●More reliable: Ensure the reliability based on active and standby disaster recovery mechanism and data backup mechanism of the server.●More safe: Ensure the system safety through channel encryption, data fingerprint and permission management.●Easier to use: VNNOX and NovaiCare can be accessed through Web. As long as there is internet, operation can be performed anytime and anywhere.●More effective: This mode is moresuitable for the commercial mode ofadvertising industry and digital signageindustry, and makes informationspreading more effective.2.4 Dual-Wi-Fi ModeThe T3 have permanent Wi-Fi AP andsupport the Wi-Fi Sta mode, carryingadvantages as shown below:●Completely cover Wi-Fi connectionscene. The T3 can be connected tothrough self-carried Wi-Fi AP or theexternal router.●Completely cover client terminals.Mobile phone, Pad and PC can be usedto log in T3 through wireless network.●Require no wiring. Display managementcan be managed at any time, havingimprovements in efficiency.T3’s Wi-Fi AP signal strength is related tothe transmit distance and environment.Users can change the Wi-Fi antenna asrequired.2.4.1 Wi-Fi AP ModeUsers connect the Wi-Fi AP of a T3 todirectly access the T3. The SSID is “AP + Configure an external router for a T3 and users can access the T3 by connecting theexternal router. If an external router is configured for multiple T3 units, a LAN can becreated. Users can access any of the T3 via the LAN.www.novastar.tech 10the last 8 digits of the SN”, for example,“AP10000033”, and the default passwordis “12345678”.2.4.2 Wi-Fi Sta Mode2.4.3 Wi-Fi AP+Sta ModeIn Wi-Fi AP+ Sta connection mode, userscan either directly access the T3 oraccess internet through bridgingconnection. Upon the cluster solution,VNNOX and NovaiCare can realize remotesolution publishing and remotemonitoring respectively through theInternet.2.5Redundant BackupT3 support network redundant backup and Ethernet port redundant backup.●Network redundant backup: The T3 automatically selects internet connectionmode among wired network or Wi-Fi Sta network according to the priority.●Ethernet port redundant backup: The T3 enhances connection reliability throughactive and standby redundant mechanism for the Ethernet port used to connectwith the receiving card.www.novastar.tech 12T3 Specifications3 Hardware Structure 3.1 AppearanceFigure 3-1 Appearance of T3Note: All product pictures shown in this document are for illustration purpose only.Actual product may vary.Table 3-1 Connectors and buttons of theName Description time: The unit is connected to Gigabit Ethernet cable and the status is normal. USB USB 2.0 portAUDIO OUT Audio output RESET Factory reset button Press and hold the button for 5 seconds to reset the unit to factory settings. 1 Output Ethernet port BACKUP1 Backup for output Ethernet port Name Description PWR Power status indicator Always on: Power input is normal. System status indicator ● Flashing once every other 2 seconds: The system is operating normally. ● Flashing once every other second: The system is installing the upgrade package. ●Flashing once every other 0.5 second: The system is SYSInternet or copying the upgrade package. ● Always on/off: The system isoperating abnormally.CLOUD Internet connection statusindicator● Always on: The unit isconnected to the Internetand the connection status isnormal.●Flashing once every other 2seconds: The unit isconnected to VNNOX andthe connection status is normal. RUN FPGA status indicatorSame as the signal indicatorstatus of the sending card: Note: All product pictures shown in this document are for illustration purpose only. Actual product may vary.Table 3-2 Indicators of the T3T3 SpecificationsThe total thickness (board thickness +thickness of the components on the frontand back side) is no greater than 25.0mm.Unit of the dimension chart is “mm”.Ground connection is enabled for locationhole (GND).T3 Specifications 4 Software Structure4 Software Structure 4.1 System SoftwareSoftware DescriptionViPlex Handy Mobile phone clientsoftware of the T3 includesAndroid and iOS which aremainly used for screenmanagement, editing, andsolution publishing.ViPlex ExpressPC client software of the T3erating system software●Android terminal application software●FPGA programNote: The third-party applications are notsupported.4.2 Related Configuration SoftwareTable 4-1 Related configuration softwareT3 Specifications 5 Product Specifications5 Product Specificationspower consumptio nStorage Space OperatingmemoryInternalstoragespace8 GB on-boardwith 4 GBavailable forusersStorage Environmen t Temperature 0ºC-50ºC Humidity 0% RH-80%RHOperating Environmen t Temperature -40ºC-80ºC Humidity 0% RH-80%RH200 mm × 120mm × 40 mm2GBPackinginformationDimension s(H×W×D)5 Product SpecificationsAntennaTaurus Series Multimedia PlayersAntenna extension mastTaurus Series Multimedia Players 6 Audio and Video DecoderSpecifications T3 Specifications6Image Size48×48pixels~8176×8176pixel sformaNoAudio and Video Decoder 6.1.2 EncoderTyp e CodecSupportedImage SizeMaximumData RateFileFormatRemarksJP EG JPEGBaseline96×32pixels~8176×8176 pixels90Mpixels/SecondJFIFfileformatN/A RestrictionGIF GIF NoRestrictionGIF N/APNG PNG NoRestrictionPNG N/AWEB P WEBPNoRestrictionWEBP N/ASpecifications6.1Image6.1.1Decoder 271.02 6.2 AudioType Codec Channel Bit rate SamplingrateFileFormatRemarksMPE G MPEG1/2/2.5AudioLayer1/2/32 8kbps~320Kbps, CBRand VBR8KHZ~48KHzMP1,MP2,MP3N/AWind ows Medi a Audi o WMAVersion4,4.1, 7, 8,9,wmapro2 8kbps~320Kb ps8KHZ~48KHzWMANon-supportWMAPro,lossless andMBRWAV MS-ADPCM,IMA-ADPCM,PCM 2 N/A 8KHZ~48KHzSupport4bitMS-ADPCM,IMA-ADPCMWAV 28OGG Q1~Q10 2 N/A 8KHZ~48KHz OGG,OGAN/AFLAC Compress Level0~8 2 N/A FLACN/AAAC ADIF,ATDSHeaderAAC-LCandAAC-HE,AAC-ELD 5.1 8KHZ~48KHzAAC,M4AN/AAMR AMR-NB,AMR-WBAMR-NB4.75~12.2kbps@8kHzAMR-WB6.60~23.85kbps@16k8KHZ,16KHz3GP N/A8K HZ~48KHzN/A1 29Taurus Series Multimedia Players6 Audio and Video Decoder T3 Specifications Specifications 35Gand YUV400(monochrome) is also supported for H.264.Type Cod ec Supported Image Size Maxi mum FrameRate MaximumBit Rate(IdealCase)Rema rksH.264/AVC H.264 144×96 pixels~1920×108 8 pixels 30fps 20Mb ps MO V, 3GP Not supportMBAFFGoogl e VP8 VP8 96×96 pixels~1920×1088 pixels30fps WE BMN/AFile Format 10 M bps。
AMX24-3-T 非坚持故障型漏斗遥控器技术数据表说明书
AMX24-3-TFootnotesCustomizable Non Fail-Safe actuator for controlling dampers in typical commercial HVAC applications.• Torque motor 180 in-lb [20 Nm]• Nominal voltage AC/DC 24 V • Control On/Off, Floating pointTechnical dataElectrical dataNominal voltageAC/DC 24 V Nominal voltage frequency 50/60 HzNominal voltage rangeAC 19.2...28.8 V / DC 21.6...28.8 V Power consumption in operation 2.5 W Power consumption in rest position 0.2 W Transformer sizing 5.5 VAElectrical Connection Screw terminal (for 26 to 14 GA wire)Overload Protectionelectronic throughout 0...95° rotation Functional dataTorque motor180 in-lb [20 Nm]Direction of motion motor selectable with switch 0/1Manual override external push button Angle of rotation Max. 95°Angle of rotation note adjustable with mechanical stop Running Time (Motor)90 s / 90°Running time motor note constant, independent of load Running time motor variable 90 or 150 s Noise level, motor 45 dB(A)Position indicationMechanical, 30...65 mm stroke Safety dataPower source ULClass 2 Supply Degree of protection IEC/EN IP20Degree of protection NEMA/UL NEMA 1Enclosure UL Enclosure Type 1Agency ListingcULus acc. to UL60730-1A/-2-14, CAN/CSA E60730-1:02CE acc. to 2014/30/EU and 2014/35/EU Quality Standard ISO 9001UL 2043 CompliantSuitable for use in air plenums per Section 300.22(C) of the NEC and Section 602 of the IMCAmbient humidity Max. 95% RH, non-condensing Ambient temperature -22...122°F [-30...50°C]Storage temperature -40...176°F [-40...80°C]Servicingmaintenance-free Weight Weight1.4 lb [0.64 kg]MaterialsHousing material UL94-5VA†Rated Impulse Voltage 800V, Type action 1.B, Control Pollution Degree 3.AMX24-3-TApplicationOperationTypical specificationProduct featuresFor on/off and floating point control of dampers in HVAC systems. Actuator sizing should be done in accordance with the damper manufacturer’s specifications.The actuator is mounted directly to a damper shaft up to 1.05” in diameter by means of itsuniversal clamp, self-centered default. A crank arm and several mounting brackets are available for applications where the actuator cannot be direct coupled to the damper shaft.The actuator is not provided with and does not require any limit switches, but is electronically protected against overload. The anti-rotation strap supplied with the actuator will preventlateral movement. The actuator provides 95° of rotation and a visual indicator indicates position of the actuator. When reaching the damper or actuator end position, the actuator automatically stops. The gears can be manually disengaged with a button on the actuator cover. The actuators use a sensorless brushless DC motor, which is controlled by an Application Specific Integrated Circuit (ASIC). The ASIC monitors and controls the actuator’s rotation and provides a digital rotation sensing (DRS) function to prevent damage to the actuator in a stall condition. Power consumption is reduced in holding mode. The -S version is provided with 1 built-in auxiliary switch. This SPDT switch is provided for safety interfacing or signaling, for example, for fanstart-up. The switching function is adjustable 0 to 95°. The auxiliary switch is double insulated so an electrical ground connection is not necessary. Add-on auxiliary switches or feedbackpotentiometers are easily fastened directly onto the actuator body for signaling and switching functions.Floating point, on/off control damper actuators shall be electronic direct-coupled type, which require no crank arm and linkage and be capable of direct mounting to a shaft up to 1.05”diameter. Actuators shall have brushless DC motor technology and be protected from overload at all angles of rotation. Actuators shall have reversing switch and manual override on the cover. If required, actuators shall be provided with one adjustable SPDT auxiliary switch. Actuators with auxiliary switches must be constructed to meet the requirements for double insulation so an electrical ground is not required to meet agency listings. If required, actuators will be provided with a screw terminal strip for electrical connections (AMX24-3-T). Run time shall be constant and independent of torque. Actuators shall be cULus listed, have a 5-year warranty, and be manufactured under ISO 9001 International Quality Control Standards. Actuators shall be as manufactured by Belimo.AccessoriesElectrical accessoriesDescriptionType Battery backup system, for non-spring return models NSV24 US Battery, 12 V, 1.2 Ah (two required)NSV-BAT Auxiliary switch 2 x SPDT add-onS2AAMX24-3-TMechanical accessoriesDescriptionType Clamp NM/AM 1/2", 3/4", 1"K-AM25Shaft clamp reversible, clamping range ø10...20 mm K-SA Mounting bracket for AF..ZG-100Mounting bracket ZG-101Mounting bracket ZG-103Mounting bracketZG-104Mounting kit for linkage operation for flat installation ZG-NMA 1" diameter jackshaft adaptor (11" L).ZG-JSA-11-5/16" diameter jackshaft adaptor (12" L).ZG-JSA-21.05" diameter jackshaft adaptor (12" L).ZG-JSA-3Base plate extension for SM..A to SM../AM../SMD24R Z-SMA Weather shield 13x8x6" [330x203x152 mm] (LxWxH)ZS-100Weather shield 406x213x102 mm [16x8-3/8x4"] (LxWxH)ZS-150Explosion proof housing 16x10x6.435" [406x254x164 mm] (LxWxH), UL and CSA, Class I, Zone 1&2, Groups B, C, D, (NEMA 7), Class III, Hazardous (classified) LocationsZS-260Weather shield 17-1/4x8-3/4x5-1/2" [438x222x140 mm] (LxWxH), NEMA 4X, with mounting bracketsZS-300Weather shield 17-1/4x8-3/4x5-1/2" [438x222x140 mm] (LxWxH), NEMA 4X, with mounting bracketsZS-300-5Terminal-strip cover for NEMA 2 rating (-T models).ZS-T Shaft extension 240 mm ø20 mm for damper shaft ø8...22.7 mm AV8-25Actuator arm for standard shaft clampAH-GMA Wrench 0.32 in and 0.39 in [8 mm and 10 mm]TOOL-06Linkage kitJackshaft Retrofit Linkage with Belimo Rotary ActuatorsZG-JSLElectrical installationActuators with appliance cables are numbered.Provide overload protection and disconnect as required.Actuators may also be powered by DC 24 V.Actuators Hot wire must be connected to the control board common. Only connect common toneg. (-) leg of control circuits. Terminal models (-T) have no-feedback.Actuators may be connected in parallel if not mechanically linked. Power consumption andinput impedance must be observed.Actuators are provided with a numbered screw terminal strip instead of a cable.Floating Point - Triac SourceAMX24-3-T Wiring diagramsOn/Off Floating PointFloating Point - Triac Source Floating Point - Triac SinkDimensions。
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PIN CONFIGURATIONFUNCTIONAL SYMBOLFEATURES■ Supports Standard and Fast I 2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range ■ 16-Byte Page Write Buffer■ Hardware Write Protection for upper half ofmemory■ Schmitt Triggers and Noise Suppression Filterson I 2C Bus Inputs (SCL and SDA).■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ RoHS compliant&8-pin PDIP ■ Industrial temperature rangePDIP (L)SOIC (W)TSSOP (Y)TDFN (VP2)V CCV SSSD ASCLWPA 2, A 1, A 0DEVICE DESCRIPTIONThe CAT24C03 is a 2-Kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each.It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I 2C protocol.Write operations can be inhibited by taking the WP pin High (this protects the upper half of the memory).The CAT24C03 is available in RoHS compliant “Green” and “Gold” 8-lead PDIP , SOIC, TSSOP and TDFN packages.8765V CC WP SCL SDAA 2A 0A 1V SS1234For the location of Pin 1, please consult the corresponding package drawing.PIN FUNCTIONSA 0, A 1, A 2Device Address SDA Serial Data SCL Serial Clock WP Write Protect V CC Power Supply V SSGround* Catalyst carries the I 2C protocol under a license from the Philips Corporation.ABSOLUTE MAXIMUM RATINGS*Storage Temperature-65°C to +150°C Voltage on Any Pin with Respect to Ground(1)-0.5 V to +6.5 V* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS(2)Symbol Parameter Min UnitsN END(*)Endurance1,000,000Program/ Erase Cycles T DR Data Retention100Years(*) Page Mode, V CC = 5 V, 25°CD.C. OPERATING CHARACTERISTICSV CC = 1.8 V to 5.5 V, T A = -40°C to 85°C, unless otherwise specified.Symbol Parameter Test Conditions Min Max UnitsI CC Supply Current Read or Write at 400 kHz1mAI SB Standby Current All I/O Pins at GND or V CC2μAI L I/O Pin Leakage Pin at GND or V CC2μAV IL Input Low Voltage-0.5V CC x 0.3V V IH Input High Voltage V CC x 0.7V CC + 0.5V V OL1Output Low Voltage V CC > 2.5 V, I OL = 3.0 mA0.4V V OL2Output Low Voltage V CC > 1.8 V, I OL = 1.0 mA0.2VPIN IMPEDANCE CHARACTERISTICST A = 25°C, f = 400 kHz, V CC = 5 VSymbol Parameter Conditions Min Max UnitsC IN(2)SDA I/O Pin Capacitance V IN = 0 V8pFC IN(2)Input Capacitance (other pins)V IN = 0 V6pFZ WPL WP Input Low Impedance V IN < 0.5 V570kΩI LWPH WP Input High Leakage V IN > V CC x 0.72μA Note:(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin mayundershoot to no less than -1.5 V or overshoot to no more than V CC + 1.5 V, for periods of less than 20 ns.(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100and JEDEC test methods.A.C. CHARACTERISTICSV CC = 1.8 V to 5.5 V, T A = -40°C to 85°C, unless otherwise specified.Symbol Parameter1.8 V - 5.5 V2.5 V - 5.5 VUnits Min Max Min MaxF SCL Clock Frequency100400kHzT I(1)Noise Suppression Time Constant atSCL, SDA Inputs0.10.1μst AA(2)SCL Low to SDA Data Out 3.50.9μs t BUF(1)Time the Bus Must be Free Before aNew Transmission Can Start4.7 1.3μst HD:STA Start Condition Hold Time40.6μs t LOW Clock Low Period 4.7 1.3μs t HIGH Clock High Period40.6μs t SU:STA Start Condition Setup Time 4.70.6μs t HD:DAT Data In Hold Time00μs t SU:DAT Data In Setup Time0.250.1μs t R(1)SDA and SCL Rise Time10.3μs t F(1)SDA and SCL Fall Time0.30.3μs t SU:STO Stop Condition Setup Time40.6μs t DH Data Out Hold Time0.10.1μs t WR Write Cycle Time55ms t PU(1), (3)Power-up to Ready Mode11ms Note:(1) This parameter is tested initially and after a design or process change that affects the parameter.(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/Ois pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of V CC. Output level reference levels are 30% and respectively 70% of V CC.(3) t PU is the delay required from the time V CC is stable until the device is ready to accept commands.Power-On Reset (POR)The CAT24C03 incorporates Power-On Reset (POR)circuitry which protects the internal logic againstpowering up in the wrong state.The CAT24C03 will power up into Standby mode afterV CC exceeds the POR trigger level and will powerdown into Reset mode when V CC drops below the PORtrigger level. This bi-directional POR feature protectsthe device against ‘brown-out’ failure following atemporary loss of power.The POR circuitry triggers at the minimum V CC levelrequired for proper initialization of the internal statemachines. The POR trigger level automatically tracks theinternal CMOS device thresholds, and is naturally wellbelow the minimum recommended V CC supply voltage.PIN DESCRIPTIONSCL:The Serial Clock input pin accepts the Serial Clock generated by the Master.SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.A0, A1 and A2: The Address pins accept the device ad-dress. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write opera-tions to the upper half of the memory array, when pulled HIGH. (locations 80H to FFH)This pin has an on-chip pull-down resistor.FUNCTIONAL DESCRIPTIONThe CAT24C03 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C03 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.I2C BUS PROTOCOLThe I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the V CC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics).During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1).STARTThe START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. A bsent a START, a Slave will not respond to commands. STOPThe STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when follow-ing a Write command) or sends the Slave into standby mode (when following a Read command).Device AddressingThe Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write opera-tions (Figure 2). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed.AcknowledgeAfter processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 4.Figure 1. Start/Stop TimingFigure 2. Slave Address BitsFigure 3. Acknowledge TimingFigure 4. Bus TimingWRITE OPERATIONSByte WriteIn Byte Write mode the Master sends a START, followed by Slave address, byte address and data to be written (Figure 5). The Slave acknowledges all 3 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 6). During internal Write, the Slave will not acknowledge any Read or Write request from the Master.Page WriteThe CAT24C03 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. A page is selected by the 4 most significant bits of the address byte following the Slave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 7).The internal byte address counter is automatically in-cremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap-around’ fashion (within the selected page). The internal Write cycle starts immediately following the STOP.Acknowledge PollingAcknowledge polling can be used to determine if the CAT24C03 is busy writing or is ready to accept com-mands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS).The CAT24C03 will not acknowledge the Slave address, as long as internal Write is in progress.Hardware Write ProtectionWith the WP pin held HIGH, the entire memory is pro-tected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C03.Figure 5. Byte Write TimingFigure 6. Write Cycle TimingFigure 7. Page Write TimingREAD OPERATIONSImmediate Address ReadIn standby mode, the CAT24C03 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that ‘previous’ byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc.When, following a START, the CAT24C03 is presented with a Slave address containing a ‘1’ in the R/W bit position (Figure 8), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition.Selective ReadThe Read operation can also be started at an address different from the one stored in the internal address coun-ter. The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 9). Here the START is followed by the Slave address (with the R/W bit set to ‘0’) and the desired byte address. Instead of follow-ing up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier.Sequential ReadIf the Master acknowledges the 1st data byte transmitted by the CAT24C03, then the device will continue trans-mitting as long as each data byte is acknowledged by the Master (Figure 10). If the end of memory is reached during sequential Read, then the address counter will ‘wrap-around’ to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address.Figure 8. Immediate Address Read TimingFigure 9. Selective Read TimingFigure 10. Sequential Read Timing8-LEAD 300 MIL WIDE PLASTIC DIP (L)eSYMBOL A A1b b2D D2E E1e eB LMIN 0.1200.0150.0140.3550.3000.3000.3100.2400.1150.1300.150NOM 0.0180.0600.0700.0450.3650.2500.430MAX 0.210A20.1150.1300.1950.0220.4000.3250.3250.2800.100 BSC Notes:1. Complies with JEDEC Standard MS001.2. All dimensions are in inches.3. Dimensioning and tolerancing per ANSI Y14.5M-198211Doc No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice8-LEAD 150 MIL WIDE SOIC (W)SYMBOLA1A2b C D E E1e f MIN 0.00400.05320.0130.1890022840.1490.0099NOM 0.00980.00750.050 BSCMAX 0.00980.06880.0200.19680.24400.15740.0196θ10°8°eNotes:1. Complies with JEDEC specification MS-012 dimensions.2. All linear dimensions in millimeters.12Doc. No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice8-LEAD TSSOP (Y)θ1SEE DETAIL AcSYMBOLA A1A2b c D E E1e L θ1MIN 0.050.800.092.906.30 6.44.300.008.00NOM 0.900.300.19 3.004.400.600.750.50MAX 1.200.151.050.203.106.504.500.65 BSC Notes:1. All dimensions in millimeters.13Doc No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice8-PAD TDFN 2X3 PACKAGE (VP2)14Doc. No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeORDERING INFORMATIONNotes:(1) The device used in the above example is a CAT24C03YI-GT3 (TSSOP , Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,Tape & Reel)(2) For additional package and temperature options, please contact your nearest Catalyst Semiconductor sales office.15Doc No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticePACKAGE MARKINGYMG 24C03IY = Production YearM = Production Month G = Die Revision 24C03 = Device Code I = Industrial Temperature Range8-Lead TSSOP 8-Lead TDFNE M = Device CodeN = Traceability Code Y = Production Year M = Production MonthE M N N N N Y MNotes:(1) The circle on the package marking indicates the location of Pin 1.8-Lead PDIP8-Lead SOICCSI = Catalyst Semiconductor, Inc.24C03W = Device Code I = Temperature Range YY = Production Year WW = Production Week G = Product RevisionYYWWG24C03WI CSI = Catalyst Semiconductor, Inc. 24C03L = Device Code I = Temperature Range YY = Production Year WW = Production Week G = Product Revision YYWWG24C03LI16Doc. No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeTAPE AND REELDirection of FeedDevice OrientationReel Dimensions (1)Embossed Carrier Dimensions Tape Size AB MinC D* Min N Min G T Max Max Qty/Reel 8MM 330 (13.00)30001.5 (0.059)12.80 (0.504) 13.20 (0.5200)20.2 (0.795)50 (1.969)8.4 (0.328) 9.9 (1.389)14.4 (0.566)12MM12.4 (0.488) 14.4 (0.558)18.4(0.724)Embossed Carrier DimensionsComponentPackage TypeTape Size (W)Part Pitch (P)8L SOIC W, Y 12mm 8mm 8L TDFN 2x3mmVP28mm4mmNote:(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.1)SOIC TSSOPTDFN17Doc No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeEmbossed Tape—Constant Dimensions (1)Tape Sizes D E P 0T Max.D 1 Min.A 0 B 0 K 0(2)12mm1.5 (0.059) 1.6 (0.063)1.65 (0.065) 1.85 (0.073)3.9 (0.153)4.1 (0.161)400 (0.016)1.5 (0.059)Embossed Carrier Dimensions (12 Tape Only)Tape Sizes B 1 Max.F K Max.P 2R Min.W P 12mm8.2 (0.0323)5.45 (0.0215) 5.55 (0.219)4.5 (0.177)1.95 (0.077)2.05 (0.081)30 (1.181)11.7 (0.460) 12.3 (0.484)7.9 (0.275) 8.1 (0.355)Note:(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.(2) A0 B0 K0 are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for 24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.Embossed Carrier Dimensions (12 Tape Only)INCLUDING DRAFT AND RADII CONCENTRIC ABOUT B 0USER DIRECTION OF FEED18Doc. No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeREVISION HISTORYDate Revision Comments03/08/06AInitial Issue19Doc No. 1113, Rev. A© 2006 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeCopyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™AE 2 ™MiniPot™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089Phone: 408.542.1000 Fax: 408.542.1200 Publication #: 1113 Revison: AIssue date: 03/08/06。