VHDL洗衣机设计

EDA课程实训报告一、实训课题：洗衣机控制器的设计二、设计的内容及要求：1．设计一个洗衣机控制器，要求为：1) 洗衣机控制器可以驱动洗衣机进行洗涤、漂洗或烘干；2) 洗衣机控制器可以设置洗衣机的工作时间，工作时间最短1分钟，最长30分钟，在工作过程中，工作时间以倒计时显示，若时间为0洗衣机停止工作；3) 洗衣机在待机状态时，洗衣机控制器可以设置洗衣机的工作方式和工作时间；4) 可以暂停或停止洗衣机工作；5) 利用四个数码管显示洗衣机待机时的设置时间和工作时的运行时间，利用一位数码管显示洗衣机待机时所设置的工作方式运行时的工作方式；6）利用三个LED分别表示驱动洗衣机进行洗涤、漂洗或烘干。

2．洗衣机控制器可以划分为状态机模块、计时器模块、设置模块和显示选择模块。

在QuartusII 中输入各个模块的代码，编译综合，仿真，完成各个模块的软件设计；4．把各个模块组合起来，综合编译，仿真，完成整个交通灯控制器系统的软件设计；5. 选择电路方案锁定管脚，把程序下载到实验箱中，利用实验箱进行硬件实现；6. 完成实训报告。

实训报告包括：1)设计的任务和要求；2)模块的划分和系统总框图；3)各个模块的实现，包括模块的作用，模块的输入与输出情况，模块状态图，模块的代码以及注释，模块的波形图；4)系统的实现，包括系统总原理图，系统的波形图；5)管脚的锁定关系；三．设计思路：◆状态切换>>>有限状态机◆按定时时间及时>>> 定时计数器◆显示时间>>> 数码管译码驱动器◆接收设置时间>>>时间设置键盘扫描器◆接收设置模式>>> 模式设置键盘扫描器◆切换显示运行时间和设置时间>>>二路选择器◆切换显示运行模式和设置模式>>>二路选择器整体设计示意图：四．系统组成以及系统各部分的设计：1.状态机的设计：状态机要完成的功能：●能设置工作模式；●控制洗涤、漂洗、干衣的驱动输出；●能启动、暂停、停止洗衣机控制器；●能重启、暂停和停止定时器；●能接收定时器的到时标志；●能使能键盘扫描计数器；●能控制二路选择器。

状态图分析设计如下：模块设计图如下：状态机仿真图如下：2. 定时器设计：定时器的功能：●能通过使能端暂停和允许定时器工作；●能停止并复位定时器；●能进行定时；●能输出定时标志模块设计图如下：定时器波形图如下：3.时间设置：时间设置键盘扫描器的功能：●能响应按键；●能在使能端的控制下工作模式设计图如下：波形图如下：4.模式设置:模式设置键盘扫描器的功能：预设工作模式，”000”为待机，”001”为洗涤，”010”为漂洗，”022”为干衣，”100”为暂停模式设计图如下：波形图如下：5.二路选择器二路选择器的功能：设置显示运行时间还是设置时间，显示运行模式还是设置模式。

模式设计图如下：整体结构图：整体波形图：五．下载时选择的开发系统模式以及管脚1.管教配置：2.实验电路结构图：D16D15D14D13D12D11D9D8PIO47D7PIO46D6PIO45D5PIO44D4PIO43D3PIO42D2PIO41PIO40D1NO.7实验电路结构图S P E A K E R扬声器FPGA/CPLD 目标芯片12345678PIO0PIO2PIO3PIO4PIO5PIO6PIO7单脉冲单脉冲单脉冲键1键2键3键4键5键6键7键8PIO47-PIO40PIO39-PIO36PIO35-PIO32PIO31-PIO28PIO27-PIO24PIO23-PIO20PIO19-PIO16译码器译码器译码器译码器译码器译码器附录 代码： 1.状态机LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY SHELL_WASHMACHINE ISPORT (CLK,modein0,modein1,modein2,pause,start,stop,tcin: IN std_logic; ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2 : OUTstd_logic);END;ARCHITECTURE BEHAVIOR OF SHELL_WASHMACHINE IS TYPE type_sreg IS (dry,ready,rinse,waitup,wash); SIGNAL sreg, next_sreg : type_sreg;SIGNAL next_ken,next_modeout0,next_modeout1,next_modeout2,next_sel,next_ten,next_tstop,next_wout0,next_wout1,next_wout2 : std_logic; SIGNAL modeout : std_logic_vector (2 DOWNTO 0);SIGNAL wout : std_logic_vector (2 DOWNTO 0);BEGINPROCESS (CLK, stop, next_sreg, next_ken, next_sel, next_ten, next_tstop, next_modeout2, next_modeout1, next_modeout0, next_wout2, next_wout1,next_wout0)BEGINIF ( stop='1' ) THENsreg <= ready;sel <= '0';ken <= '1';ten <= '1';tstop <= '1';modeout2 <= '0';modeout1 <= '0';modeout0 <= '0';wout2 <= '0';wout1 <= '0';wout0 <= '0';ELSIF CLK='1' AND CLK'event THENsreg <= next_sreg;ken <= next_ken;sel <= next_sel;ten <= next_ten;tstop <= next_tstop;modeout2 <= next_modeout2;modeout1 <= next_modeout1;modeout0 <= next_modeout0;wout2 <= next_wout2;wout1 <= next_wout1;wout0 <= next_wout0;END IF;END PROCESS;PROCESS (sreg,modein0,modein1,modein2,pause,start,tcin,modeout,wout)BEGINnext_ken <= '0'; next_modeout0 <= '0'; next_modeout1 <= '0'; next_modeout2 <= '0'; next_sel <= '0'; next_ten <= '0'; next_tstop <= '0'; next_wout0 <='0'; next_wout1 <= '0'; next_wout2 <= '0';modeout<=std_logic_vector'("000"); wout<=std_logic_vector'("000");next_sreg<=dry;CASE sreg ISWHEN dry =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=dry;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("011"));wout <= (std_logic_vector'("100"));END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("100"));wout <= (std_logic_vector'("000"));END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1';next_tstop<='1';next_ken<='1';next_sel<='0';modeout <= (std_logic_vector'("000"));wout <= (std_logic_vector'("000"));END IF;WHEN ready =>IF ( modein1='0' AND modein0='0' ) OR ( modein2='1' ) OR ( start='0' ) THENnext_sreg<=ready;next_ten<='1';next_tstop<='1';next_ken<='1';next_sel<='0';modeout <= (std_logic_vector'("000"));wout <= (std_logic_vector'("000"));END IF;IF ( modein0='1' AND modein1='1' AND modein2='0' AND start='1' ) THEN next_sreg<=dry;next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("011"));wout <= (std_logic_vector'("100"));END IF;IF ( modein0='0' AND modein1='1' AND modein2='0' AND start='1' ) THEN next_sreg<=rinse;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("010"));wout <= (std_logic_vector'("010"));END IF;IF ( modein0='1' AND modein1='0' AND modein2='0' AND start='1' ) THEN next_sreg<=wash;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("001"));wout <= (std_logic_vector'("001"));END IF;WHEN rinse =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=rinse;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("010"));wout <= (std_logic_vector'("010"));END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0';next_tstop<='0';next_ken<='0';modeout <= (std_logic_vector'("100"));wout <= (std_logic_vector'("000"));END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1';next_tstop<='1';next_ken<='1';next_sel<='0';modeout <= (std_logic_vector'("000"));wout <= (std_logic_vector'("000"));END IF;WHEN waitup =>IF ( modein1='0' AND modein0='0' ) OR ( modein2='1' ) OR ( pause='1' ) THENnext_sreg<=waitup;next_ten<='0';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("100"));wout <= (std_logic_vector'("000"));END IF;IF ( modein0='1' AND modein1='1' AND modein2='0' AND pause='0' ) THEN next_sreg<=dry;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("011"));wout <= (std_logic_vector'("100"));END IF;IF ( modein0='0' AND modein1='1' AND modein2='0' AND pause='0' ) THEN next_sreg<=rinse;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("010"));wout <= (std_logic_vector'("010"));END IF;IF ( modein0='1' AND modein1='0' AND modein2='0' AND pause='0' ) THEN next_sreg<=wash;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("001"));wout <= (std_logic_vector'("001"));END IF;WHEN wash =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=wash;next_ten<='1';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("001"));wout <= (std_logic_vector'("001"));END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0';next_tstop<='0';next_ken<='0';next_sel<='1';modeout <= (std_logic_vector'("100"));wout <= (std_logic_vector'("000"));END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1';next_tstop<='1';next_ken<='1';next_sel<='0';modeout <= (std_logic_vector'("000"));wout <= (std_logic_vector'("000"));END IF;WHEN OTHERS =>END CASE;next_modeout2 <= modeout(2);next_modeout1 <= modeout(1);next_modeout0 <= modeout(0);next_wout2 <= wout(2);next_wout1 <= wout(1);next_wout0 <= wout(0);END PROCESS;END BEHAVIOR;LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY WASHMACHINE ISPORT (modein : IN std_logic_vector (2 DOWNTO 0);modeout : OUT std_logic_vector (2 DOWNTO 0);wout : OUT std_logic_vector (2 DOWNTO 0);CLK,pause,start,stop,tcin: IN std_logic;ken,sel,ten,tstop : OUT std_logic);END;ARCHITECTURE BEHAVIOR OF WASHMACHINE ISCOMPONENT SHELL_WASHMACHINEPORT (CLK,modein0,modein1,modein2,pause,start,stop,tcin: IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2 : OUTstd_logic);END COMPONENT;BEGINSHELL1_WASHMACHINE : SHELL_WASHMACHINE PORT MAP (CLK=>CLK,modein0=>modein(0) ,modein1=>modein(1),modein2=>modein(2),pause=>pause,start=>start,stop=>stop,tcin=>tcin,ken=>ken,modeout0=>modeout(0),modeout1=>modeout(1),modeout2=>modeout(2),sel=>sel,ten=>ten,tstop=>tstop,wout0=>wout(0),wout1=>wout(1),wout2=>wout(2));END BEHAVIOR;2．定时器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dingshi isport(clk,ten,tstop:in std_logic;ims:in std_logic_vector(3 downto 0);iss:in std_logic_vector(3 downto 0);img:in std_logic_vector(3 downto 0);isg:in std_logic_vector(3 downto 0);cin:out std_logic;omg, osg:buffer std_logic_vector(3 downto 0);oms:buffer std_logic_vector(3 downto 0);oss:buffer std_logic_vector(3 downto 0) );end;architecture cml of dingshi isbeginPROCESS(clk, ten, tstop)BEGINIF ten='1' THENIF tstop='1' THENosg<=isg;ELSIF clk'EVENT AND clk='1' THENIF osg="0000" THENIF oss>"0000" OR omg>"0000" OR oms>"0000" THENosg<="1001";ELSEosg<="0000";END IF;ELSEosg<=osg-1;END IF;END IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg)BEGINIF ten='1' THENIF tstop='1' THENoss<=iss;ELSIF clk'EVENT AND clk='1' THENIF osg="0000" THENIF oss=0 THENIF omg>"0000" OR oms>"0000" THENoss<="0101";ELSEoss<="0000";END IF;ELSEoss<=oss-1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg, oss)BEGINIF ten='1' THENIF tstop='1' THENomg<=img;ELSIF clk'EVENT AND clk='1' THENIF oss=0 and osg=0 THENIF omg=0 THENIF oms>0 THENomg<="1001";ELSEomg<="0000";END IF;ELSEomg<=omg-1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg, oss, omg) BEGINIF ten='1' THENIF tstop='1' THENoms<=ims;ELSIF clk'EVENT AND clk='1' THENIF omg=0 and osg=0 and oss=0 THENIF oms=0 THENoms<="0000";ELSEoms<=oms-1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg, oss, omg, oms)BEGINIF ten='1' THENIF tstop='0' THENIF clk'EVENT AND clk='1' THENIF oms=0 AND omg=0 AND oss=0 AND osg=1 THENcin<='1';ELSEcin<='0';END IF;END IF;END IF;END IF;END PROCESS;END cml;3.时间设置：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key ISport( kin: in std_logic;ken: in std_logic;ims,iss,img,isg: buffer std_logic_vector(3 downto 0));end key;ARCHITECTURE cml OF key ISBEGINPROCESS(kin, ken)BEGINIF ken='1' THENIF kin'EVENT AND kin='1' THENIF isg="1001" THENisg<="0000";ELSEisg<=isg+1;END IF;END IF;END IF;END PROCESS;PROCESS(kin, ken, isg)BEGINIF ken='1' THENIF kin'EVENT AND kin='1' THENIF isg=9 THENIF iss="0101" THENiss<="0000";ELSEiss<=iss+1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(kin, ken, isg, iss)BEGINIF ken='1' THENIF kin'EVENT AND kin='1' THENIF iss="0101" AND isg="1001" THENIF img="1001" THENimg<="0000";ELSEimg<=img+1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(kin, ken, isg, iss, img)BEGINIF ken='1' THENIF kin'EVENT AND kin='1' THENIF img="1001" AND iss="0101" AND isg="1001" THENIF ims="0010" THENims<="0000";ELSEims<=ims+1;END IF;END IF;END IF;END IF;END PROCESS;END cml;4.模式设置：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mode isport(kin :in std_logic;ken :in std_logic;modeset:buffer std_logic_vector(2 downto 0);LED:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); end mode;architecture cml of mode issignal a: std_logic_vector(2 downto 0);signal k: std_logic;beginprocess(kin,ken)beginif ken='1' thenif rising_edge(kin) thenif a="100" thena<="000";elsea<=a+1;end if;end if;end if;end process;modeset<=a;PROCESS(modeset)BEGINCASE modeset ISWHEN "001"=>LED<="001";WHEN "010"=>LED<="010";WHEN "011"=>LED<="100";WHEN OTHERS=>LED<="000";end case ;end process;end cml;5.二路选择器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mulsel isport(ims:in std_logic_vector(3 downto 0);iss:in std_logic_vector(3 downto 0);img:in std_logic_vector(3 downto 0);isg:in std_logic_vector(3 downto 0);oms:in std_logic_vector(3 downto 0);oss:in std_logic_vector(3 downto 0);omg:in std_logic_vector(3 downto 0);osg:in std_logic_vector(3 downto 0);msdis:out std_logic_vector(3 downto 0);mgdis:out std_logic_vector(3 downto 0);isdis:out std_logic_vector(3 downto 0);igdis:out std_logic_vector(3 downto 0);modedis:out std_logic_vector(2 downto 0);modeset:in std_logic_vector(2 downto 0);modeout:in std_logic_vector(2 downto 0);sel:in std_logic);end mulsel;architecture cml of mulsel isbeginprocess(sel,ims,iss,isg,oms,isg,oss,omg,osg)beginif sel='1' thenmsdis<=oms;mgdis<=omg;isdis<=oss;igdis<=osg;modedis<=modeout;elsemsdis<=ims;mgdis<=img;isdis<=iss;igdis<=isg;modedis<=modeset;end if;end process;end cml;。