PM3350-RC中文资料

PMC-970109ISSUE 38 PORT ETHERNET SWITCHPM3350ELAN 8X108 PORT ETHERNET SWITCHDATA SHEETISSUE 3: APRIL 1998PMC-970109ISSUE 38 PORT ETHERNET SWITCHPMC-970109ISSUE 38 PORT ETHERNET SWITCHCONTENTSFEATURES (5)BLOCK DIAGRAM (7)DESCRIPTION (8)DEVICE DATA (9)Introduction (9)Switch Processor (9)Multichannel DMA Processor (9)Ethernet/IEEE 802.3 MAC Interfaces (10)Expansion Port (10)Local Memory Controller (10)Clocking and Test (11)TYPICAL SYSTEM APPLICATIONS (12)Simple 8-Port Switch (12)Low-cost 10/100 Mbit/s Switch (12)PRIMARY FEATURES AND BENEFITS (14)Wire-speed Packet switching (14)Combined Input- and Output-buffered switch (14)Modular design (14)Advanced switching features (14)Spanning tree bridging capabilities (15)Management and monitoring support (15)Autoconfiguration via Local PROM/EEPROM (15)PIN DIAGRAM (16)256-Pin SBGA Pin Diagram (16)PIN DESCRIPTION (18)Functional Grouping (21)PCI Expansion Bus Interface (22)MAU Interface Pins (23)Local Memory Interface (24)PMC-970109ISSUE 38 PORT ETHERNET SWITCHClock Inputs and Outputs (25)Miscellaneous Inputs and Outputs (26)DC CHARACTERISTICS (28)Absolute Maximum Ratings (28)Recommended Operating Conditions (28)D.C. Characteristics (29)AC CHARACTERISTICS (30)PCI Bus Interface (31)MAC Interface (32)Memory Interface (34)60 ns EDO DRAM AC Timing (34)150 ns EEPROM/EPROM AC Timing (34)Clocking (38)Miscellaneous (38)FUNCTIONAL DESCRIPTION (39)Overview (39)System Components (39)System Block Diagram (41)System Memory Map (43)Device Internal Blocks (45)Switch Processor (45)Ethernet MAC Interfaces (46)Multichannel DMA Controller (49)Memory Controller (50)PCI Expansion Port (51)Watchdog Timer Facility (55)Configuration and Initialization (56)Two-step process (56)Four-step process (56)Device Configuration (57)System Bootstrap Image (59)Configuration Parameters (63)Stand-Alone System Boot (63)Master/Slave System Boot (63)Host-Controlled System Boot (63)Self Test and Error Reporting (64)Data Structures (65)PMC-970109ISSUE 38 PORT ETHERNET SWITCH Switch Processor Operating Environment (65)Packet Buffers (68)Data Descriptors (71)Local Port Descriptor Tables (76)Expansion Port Descriptor Tables (85)Address Hash Table (89)Work Queue (98)Free Pools (99)Spanning Tree Support Data Structures (100)RTOS Requirements (101)UDP/IP Protocol Stack Requirements (102)SNMP Requirements (102)Storage Requirements (102)Switching System Initialization (105)Switching Between Local Ports (105)Switching Via The Expansion Bus (112)Address Learning and Aging (124)Buffer and Queue Management (132)Statistics Collection (137)Messaging Protocol (141)Spanning Tree Operation (141)RTOS Operation (141)UDP/IP Protocol Stack Operation (141)SNMP Operation (141)Device Interface Via PCI (141)Frame Transfer to Non-ELAN Devices (141)Participation in Address Learning (141)Participation in the Messaging Protocol (141)Accessing Variables and Statistics (141)Byte Ordering (142)ELAN 1x100 / ELAN 8x10 Expansion Bus Data Transfer Rates (144)PCI REGISTER/MEMORY ACCESS (150)PCI Configuration Space (150)PCI Configuration Registers (151)PCI Memory Space (160)Local Memory Access (161)Device Control/Status Registers (162)Device Configuration Registers (164)Device Debug Registers (169)PMC-970109ISSUE 38 PORT ETHERNET SWITCH Request and Acknowledge Counter Registers (169)PROGRAMMER'S MODEL (170)Local Memory Map (170)Register Map (170)General-Purpose Registers (170)Special-Purpose Registers (170)Control Registers (172)Register Descriptions (175)CPU Special Registers (175)Device Control Registers (176)RPCIM Functional Block (PCI access DMA channel) (185)Serial Communications Controller logic (SCC module) (203)Interrupts (215)Coprocessor Condition Tests (216)General-Purpose Inputs (216)General-Purpose Outputs (217)Programming Notes (218)General Switching Firmware Structure (218)Local Port Interrupt Handlers (218)Work Queue Interrupt Handler (218)Expansion Port Counter Interrupt Handler (218)Expansion Port Data Transfer Interrupt Handler (218)Alarm Interrupt Handlers (218)Background Task Dispatcher (219)SYSTEM IMPLEMENTATION CONSIDERATIONS (220)Power Supply Sequencing (220)System Reset (220)Device Configuration (220)PCI Interfacing (220)PCI Bus Arbitration (220)Memory Bus Loading (220)ORDERING AND THERMAL INFORMATION (221)MECHANICAL INFORMATION (222)THERMALLY ENHANCED BALL GRID ARRAY(SBGA) (222)256 PIN SBGA -27x27 MM BODY - (B SUFFIX) (222)PMC-970109ISSUE 38 PORT ETHERNET SWITCHFEATURES•Single-chip, 8-port 10BaseT Ethernet switch device for low-cost unmanaged and managed networks.•On-chip 50 MHz RISC CPU processor core, multi-channel DMA controller, MAC-layer interface logic, FIFOs, PCI-based expansion port and a flexiblememory controller.•CPU supports background applications running on local OS (e.g., SNMP or RMON), and real-time data oriented applications (e.g., packet forwarding andfiltering decisions).•Concurrently switches packets between 8 independent half-duplex ports at the full Ethernet rate of 10 Mbit/s.•Fully compatible with the PM3351 1-port 10/100 Mbit/s switch device; may be used to create a compact and inexpensive mixed 10/100 Mbit/s switch.•Store-and-forward operation with full error checking and filtering.•Filtering and switching at wire rates (up to 14,880 packets per second per port), supporting a mix of Ethernet and IEEE 802.3 protocols.•Performs all address learning, address table management and aging functions for up to 32,768 MAC addresses (limited by external memory) with an addresslearning rate of up to 10,000 addresses per second.•Maximum broadcast/multicast rate of 14,880 packets per second per port with configurable broadcast storm rate limiting.•Low-latency operation in both unicast and broadcast modes.•Implements the Link Partition function to isolate malfunctioning segments or hosts.•IEEE 802.1d compliant spanning-tree transparent bridging supported on-chip, with configurable aging time and packet lifetime control.•On-chip user-enabled backpressure flow control with configurable per-port buffer thresholds and limits.•Expandable to 64 ports without loss in throughput using multiple PM3350 devices via an on-chip 1 Gbit/s expansion port.PMC-970109ISSUE 38 PORT ETHERNET SWITCH •Expansion port supports a peak system bandwidth of 1 Gbit/s, and is compatible with industry-standard PCI bus (version 2.1).•Interfaces directly to industry-standard 10BaseT Ethernet Medium Access Unit devices (LXT944 or similar) with no glue logic.•Configuration, management, MIB statistics and diagnostics available in-band or out-of-band.•Maintains and collects per-port and per-host statistics at wire rates, allowing a network switch comprised of PM3351 and PM3350 chips to implement RMONstatistics (EtherStats and HostStats) using supplied on-chip firmware.•Fully static CMOS operation at 50 MHz clock rates.• 3.3 Volt core, 5 Volt compatible I/O•256 pin SBGA package.PMC-970109ISSUE 38 PORT ETHERNET SWITCH BLOCK DIAGRAM External Memory InterfaceMulti-Channel DMA Controller 50 MHz Embedded Processor I Cache PCI Bus Interface P C I E x p a n s i o n B u s EDO DRAM / EPROMExpansion Registers FIFO 10BaseT MAC 10BaseT 10BaseT 10BaseT 10BaseT Q u a d E t h e r n e t I n t e r f a c e A d a p t e r 10BaseT 10BaseT 10BaseT10BaseT Q u a d E t h e r n e tI n t e r f a c e A d a p t e r D Cache FIFO10BaseT MAC FIFO10BaseT MAC FIFO 10BaseT MACFIFO 10BaseT MACFIFO 10BaseT MACFIFO 10BaseT MACFIFO 10BaseT MACPMC-970109ISSUE 38 PORT ETHERNET SWITCHDESCRIPTIONThe PM3350 is a low-cost, highly integrated, stand-alone, single-chip switching device for Ethernet/IEEE 802.3 switching and bridging applications. The device supports all processing required for switching Ethernet/IEEE 802.3 packets between eight independent half-duplex 10 Mbit/s ports. In addition, a switch built around the ELAN8x10 can be expanded simply by connecting up to 7 additional devices to the on-chip1 Gbit/s expansion port. Switch configuration and management can be performed either remotely (in-band), via the on-chip SNMP MIB, agent and integrated TCP/UDP/IP stack, or from a local CPU interfaced to the expansion port. The ELAN 8x10 also collects per-port and per-host RMON statistics at wire rates on all ports. The ELAN8x10 chip contains all the required elements of a high-performance Ethernet switch: MAC-layer interfaces, buffer FIFOs, a high-speed DMA engine for fast packet transfers, a local memory interface for up to 16 MB of external buffer memory, a compatible PCI bus master and slave unit for modular expansion, and a switch processing unit that implements the switching and bridging functions. The only additional components required to create a complete 8-port switch are Ethernet Medium Access Unit (MAU) devices, line transformers, a bank of external memory and a system clock.The ELAN 8x10 device is implemented in high-density CMOS technology for low cost and high performance. It is available in a 256-pin SBGA, and is ideally suited for compact, low-cost desktop, workgroup and departmental Ethernet switching applications.PMC-970109ISSUE 38 PORT ETHERNET SWITCHDEVICE DATAIntroductionThe PM3350 ELAN 8x10 offers a complete system-level solution, integrating all required elements (except packet-buffer/address-table memory and transceiver logic) in a single high-density VLSI chip. It is a true single-chip managed switch; all the required functions, including address learning/aging, management, RMON-level statistics collection, spanning tree support and self-configuration, are performed by the ELAN8x10 without need for external CPUs or logic. In addition, the functions required for expandability are also integrated into the device.The ELAN 8x10 is built around a RISC CPU based Switch Processor core, coupled with a multi-channel DMA controller, MAC-layer interface logic, FIFOs, a PCI-based expansion port and a flexible memory controller.Switch ProcessorAn on-chip Switch Processor is primarily responsible for performing the Ethernet / IEEE 802.3 packet switching functions, and can switch packets arriving simultaneously from the eight 10BaseT ports and the expansion port at full wire rates using address tables that it creates and maintains in external local memory. Store-and-forward switching is performed, allowing the Switch Processor to detect CRC, length and alignment errors and reject bad packets. The Switch Processor also supports IEEE 802.3group/functional address handling. Address aging, topology change updates, and statistics collection are performed by the Switch Processor as well.The Switch Processor unit allows the device to support high-level capabilities. In addition, it implements the full IEEE 802.1d spanning-tree transparent bridging protocol, which allows the ELAN 8x10 to act as a eight-port expandable learning bridge, performing learning, filtering and redirection at full speed. Finally, the Switch Processor can host an SNMP agent for powerful remote switch configuration and diagnostic capabilities, allowing systems built around the ELAN 8x10 to be managed in-band using standard management platforms. When additional switch devices are connected to the ELAN 8x10 expansion port, the Switch Processors in all ELAN 8x10s intercommunicate to transparently support a distributed SNMP MIB.In host-based applications, the host CPU may bypass the on-chip SNMP agent to communicate directly with the Switch Processor for configuration, control and monitoring purposes.Multichannel DMA ProcessorThe on-chip DMA Coprocessor contains eleven independent and concurrently operating channels, one for each of the eight 10BaseT ports and three dedicated to thePMC-970109ISSUE 38 PORT ETHERNET SWITCH expansion port. The DMA Coprocessor operates under the control of the Switch Processor unit to transfer packets and data at high speed between the 10BaseT ports, the local memory and the expansion port. It also computes 32-bit IEEE Frame Check Sequence (FCS) CRC remainders over the transferred data, allowing the Switch Processor to filter packets with errors and generate CRCs for transmitted packets as required.Ethernet/IEEE 802.3 MAC InterfacesEight independent Ethernet/IEEE 802.3 MAC-layer interfaces are built into the ELAN8x10 chip. These interfaces connect directly to external 10BaseT Medium Access Unit (MAU) devices via the industry-standard 7-wire serial interface, and perform most of the MAC-layer processing tasks required for CSMA/CD networks. In addition, each MAC interface contains a 32-byte FIFO buffer that enhances throughput and minimizes latency issues.The signaling protocol used on the 7-wire serial interfaces supported by the ELAN 8x10 chip follows that required by the Advanced Micro Devices, Inc (AMD) Am7990 LANCE device.Expansion PortA 32-bit parity-checked expansion port is provided to allow systems using the ELAN8x10 to be expanded transparently from 8 to 64 ports. The expansion port supports a peak throughput of 1 Gbit/s, and requires only a single external PAL or similar device (to serve as a bus arbiter). Packets received on an ELAN 8x10 MAC port that are destined for an external ELAN 8x10 are transferred over the expansion bus prior to transmission on the designated destination port. Broadcast and multicast packets are handled using a two-level replication scheme, in which the broadcast/multicast packet is first transferred to all of the external ELAN 8x10s, after which it is transmitted out the required destination ports without any further use of the expansion bus. In addition, ELAN 8x10s interconnected via the expansion port exchange information to maintain the distributed MIB.Local Memory ControllerAn external local memory is used for holding configuration information, MAC address tables and statistics tables, node management data, packet buffers, and host communication queues (if a local host CPU is present). The ELAN 8x10 integrates a memory controller that is capable of addressing and directly driving up to 16 Mbytes of external memory, divided into four banks of 4 Mbytes each, with decoded selects for each bank. Independent, software programmable access times may be set for each bank, allowing a glueless interface to a mix of EDO DRAM, EEPROM, EPROM and ROM in the same system. An external memory timing generator may also be used if desired. The memory controller accepts simultaneous requests from the SwitchPMC-970109ISSUE 38 PORT ETHERNET SWITCH Processor, the DMA processor, and the expansion port, and efficiently partitions the100 Mbytes/s peak memory port bandwidth among them.The ELAN 8x10 is capable of auto-configuring after power-up via an 8-bit EPROM or EEPROM connected to the memory port. Parameters (such as the MAC address, IP address, configuration options, etc.) may be placed in this EPROM or EEPROM, and will be loaded automatically by the ELAN 8x10.Clocking and TestThe ELAN 8x10 is implemented in fully-static CMOS technology, and is intended to operate at a device clock frequency of 50 MHz (40 MHz for the expansion port bus). The Switch Processor performs a comprehensive power on self test (POST), and can report failure conditions and device status, if necessary, via an 8-bit LED interface register connected to the local memory port.PMC-970109ISSUE 38 PORT ETHERNET SWITCHTYPICAL SYSTEM APPLICATIONS Simple 8-Port SwitchThe ELAN 8x10 chip can act as a stand-alone managed or unmanaged switching device in low-cost, compact switch applications. Such a switch can be created from ELAN 8x10 chips (one for every 8 ports), a bank of two 256k x 16-bit 60 nsec EDO chips per ELAN 8x10 chip, a 32k x 8-bit EPROM or EEPROM for initialization andconfiguration information, two LXT944 or similar quad Ethernet Interface Adapters, and suitable passive components (filters, transformers, crystal oscillators, etc.) A block diagram of a typical 8-port 10BaseT stackable switch is given below. The PCIexpansion bus allows multiple ELAN 8x10 switch assemblies to be easily stacked up to a maximum of 64 10Mbit/s ports.Managed 8-Port Ethernet SwitchThe above system will operate as a fully managed system simply by replacing the 32k x 8-bit EEPROM with a 256k x 8-bit EPROM or EEPROM containing the SNMP agent,support firmware, spanning tree, and TCP/IP stack.Low-cost 10/100 Mbit/s SwitchThe ELAN 8x10 chip can be part of a 10/100 switch using the ELAN 1x100 10/100Mbit/s switch chip. Together they can form a workgroup or desktop switch supporting a high-speed server or backbone port in low-cost, compact Ethernet switching hubapplications. Such a switch can be created from one or two PM3351 devices (one forEDO DRAM 10BaseT Ports 1-410BaseT Ports 5-8Quad 10BaseT Interface ELAN 8x10PM3350Quad 10BaseT InterfaceEEPROMPCI Bus Expansion BusPMC-970109ISSUE 38 PORT ETHERNET SWITCHevery 100 Mbit/s port required), 1 to 7 PM3350 chips (one for every eight 10 Mbit/s ports required), a bank of memory per device (60 nsec EDO DRAM for each PM3350,15 ns SRAM for each PM3351) for holding packet buffers and switching tables, a single 32k x 8-bit EEPROM device for configuration information, two LXT944 10BaseTinterface adapters per PM3350 chip, one LXT970 100 Mbit/s PHY device per PM3351,and suitable passive components (filters, transformers, crystal oscillators, etc.) A block diagram of a typical 32-port 10BaseT stackable switching hub with two 100 Mbit/sserver/backbone ports is given in the following diagram. The PCI expansion bus is used seamlessly to stack the ELAN 8x10s and ELAN 1x100s.Expandable 10/100 Mbit/s Ethernet SwitchELAN 8x108x10BaseT PM3350PCI Backplane8 x 10BaseT10/100BaseT8 x 10BaseTQuad PHY E D OD R A MELAN 8x108 x 10BaseT PM3350Quad PHYELAN 8x108x10BaseT PM3350ELAN 1x1001x10/100BaseT PM3351Quad PHY Quad PHY10/100PHYE D OD R A MS R A MELAN 8x108x10BaseT PM3350E D OD R A ME D OD R A ME E P R O MELAN 1x1001x10/100BaseT PM3351S R A MQuad PHY Quad PHY Quad PHY Quad PHY 10/100BaseT10/100PHY8 x 10BaseT 8 x 10BaseTPMC-970109ISSUE 38 PORT ETHERNET SWITCHPRIMARY FEATURES AND BENEFITSWire-speed Packet switchingEach ELAN 8x10 chip offers 8 separate Ethernet ports all capable of accepting and processing packets simultaneously at wire rates (ranging from 14,880 packets/sec per port with a packet length of 64 bytes to 813 packets/sec per port with 1518 byte packets), immediately multiplying the aggregate bandwidth of the target network by a factor of eight. In addition, the low cost and compact size permitted by the single-chip ELAN 8x10 solution makes micro-segmentation highly feasible, allowing even more improvement in bandwidth.Combined Input- and Output-buffered switchThe ELAN 8x10 implements a hybrid input-buffered/output-queued switching algorithm which minimizes packet loss, allows packet buffers to be allocated on a demand basis, and permits limits to be established to prevent any one port from consuming all system buffer memory. Buffer limits are configured on a per-port basis. Packet storage is allocated within the external memory by the ELAN 8x10 from a central pool using anon-demand method, employing linked lists of small, fixed-length buffers to hold variable sized packets in order to maximize memory utilization.Modular designMultiple ELAN 8x10 chips interconnect seamlessly, allowing transparent expansion of switching hubs from 8 to 64 ports without significant redesign. The 1 Gbit/s expansion port bandwidth ensures that network capacity grows linearly as more ELAN 8x10 chips are added (up to the maximum number of supported ports).Advanced switching featuresThe ELAN 8x10 directly implements backpressure flow control (as a user-selectable option), with configurable thresholds and limits, to minimize packet loss in heavily loaded networks. Backpressure is performed by jamming, or colliding with, incoming packets on an individual port when the port has run out of buffer space; all other ports continue to run normally, with no head-of-line blocking effects. The ELAN 8x10 also implements per-packet lifetime control to ensure that transmit queues are flushed properly in the event of bottlenecks at the output ports. Address aging is handled on-chip, as is purging of the address table in the event of a network reconfiguration. Broadcast storm rate limiting is implemented (with configurable rate limits) to reduce the effects of high broadcast rates on the traffic flowing through the switch.PMC-970109ISSUE 38 PORT ETHERNET SWITCH Spanning tree bridging capabilitiesThe ELAN 8x10 optionally implements the 802.1d spanning tree protocol, allowing it to interoperate with IEEE-standard transparent bridges. The spanning tree protocol is supported by the on-chip Switch Processor unit, and does not require an external CPU for implementation.Management and monitoring supportThe ELAN 8x10 maintains full RMON port and host statistics for all ports and all learned MAC addresses at wire rates. These statistics may be retrieved either in-band (via SNMP agent) or out-of-band (via the expansion bus).The ELAN 8x10 implements an optional on-chip SNMP agent on top of an integralUDP/IP protocol stack, supporting SNMP and the RFC1493 bridge MIB. When multiple ELAN 8x10 chips are present in a system, they may be configured to intercommunicate and create a distributed MIB in a transparent manner. Alternatively, the system vendor may elect to disable the SNMP agent and access the ELAN 8x10 statistics and configuration variables directly from the expansion port.Status codes may be displayed on a set of LEDs (Light Emitting Diodes) during self-test and operation at the system implementer's discretion. These status codes are output to a register mapped into the ELAN 8x10 memory data bus at a specific address location. Device failure during self-test, or specific operating conditions, may be displayed using front-panel LEDs connected to the register.Autoconfiguration via Local PROM/EEPROMThe ELAN 8x10 will automatically self-configure upon power-up using user-defined parameters supplied in an external EPROM or EEPROM. The EPROM/ EEPROM may be connected to the memory bus and mapped to any address range; the ELAN 8x10will automatically locate the EPROM or EEPROM and load the configuration parameters from it. The ELAN 8x10 also contains hardware that enables it to write to standard 3.3-volt EEPROM devices, thus permitting configuration information to be changed dynamically.PMC-970109ISSUE 38 PORT ETHERNET SWITCHPIN DIAGRAMThe ELAN 8x10 is packaged in a 256-pin cavity-down SBGA, with 188 signal pins and associated VDD (supply) and VSS (ground) pins.256-Pin SBGA Pin Diagram20191817161514131211A VSS VSS VSS MDATA_31MDATA_27MDATA_24MDATA_20VSSMDATA_14MDATA_1B VSS VDD VDD MRAS_MDATA_28MDATA_25MDATA_21MDATA_17MDATA_15MDATA_11C VSS VDD VDD MWEN_1_MDATA_30MDATA_26MDATA_23MDATA_19MDATA_16MDATA_12D MRDY_MRD_MWEN_2_VDD MWEN_0_MDATA_29VDDMDATA_22MDATA_18MDATA_13E MCS_3_MCS_2_MCS_0_MWEN_3_F MADDR_2MADDR_1MADDR_0MCS_1_256 BGAG MADDR_6MADDR_5MADDR_3VDDBOTTOM VIEWH MADDR_10MADDR_8MADDR_7MADDR_4J VSS MADDR_12MADDR_11MADDR_9K VSSMADDR_13MADDR_14VDDL MADDR_15MADDR_16MADDR_17MADDR_18M MADDR_19COL_7CD_7RXD_7N VSS RCLK_7TEN_7COL_6P TXD_7TCLK_7CD_6VDD R RCLK_6RXD_6TEN_6COL_5T TXD_6TCLK_6CD_5TEN_5U RCLK_5RXD_5TXD_5VDD COL_4RXD_4VDD RXD_3CD_2VDD V VSS VDD VDD TCLK_5LBK TCLK_4RCLK_3TCLK_3RXD_2TCLK_2W VSS VDD VDD CD_4TEN_4COL_3TEN_3COL_2TEN_2TXD_2YVSSVSSVSSRCLK_4TXD_4CD_3TXD_3RCLK_2VSSVSS20191817161514131211PMC-970109ISSUE 38 PORT ETHERNET SWITCH10987654321VSS VSS MDATA_5MDATA_1DBG_2PC_3PC_7VSS VSS VSS AMDATA_8MDATA_7MDATA_3MDATA_0DBG_1PC_4PC_8VDD VDD VSS BMDATA_9MDATA_6MDATA_2MINTR_DBG_0PC_6PC_10VDD VDD VSS CVDD MDATA_4MGWE_VDD PC_5PC_9VDD N/C N/C ERST_DN/C TST_RST_GNT_EINT_REQ_AD_31AD_30FVDD AD_29AD_27AD_26GAD_28AD_25CBE_3_VSS HAD_24VDD5IDEL_AD_23JAD_22AD_21AD_20AD_19KVDD AD_18AD_17VSS LIRDY_CBE_2_AD_16VSS MSERR_DEVSEL_TRDY_FRAME_N256 BGA VDD PAR PERR_STOP_PBOTTOM VIEW AD_11AD_14AD_15CBE_1_RAD_7AD_10AD_12AD_13TCOL_1TXD_1RCLK_0VDD AD_2AD_6VDD PCI_CLK AD_8AD_9UMCLK RXD_1TCLK_1RXD_0TCLK_0AD_3CBE_0_VDD VDD VSS VSYSCLK RCLK_1TEN_1CD_0TXD_0AD_1AD_5VDD VDD VSS WCLK20CD_1VSS COL_0TEN_0AD_0AD_4VSS VSS VSS Y10987654321PMC-970109ISSUE 38 PORT ETHERNET SWITCH PIN DESCRIPTIONPIN SIGNAL PIN SIGNAL PIN SIGNALD1ERST_R3AD_14W12TEN_2E3TST_T1AD_13V12RXD_2F4INT_T2AD_12Y13RCLK_2E2RST_R4AD_11U12CD_2E1GNT_T3AD_10W13COL_2F3REQ_U1AD_9V13TCLK_3F2AD_31U2AD_8Y14TXD_3F1AD_30T4AD_7W14TEN_3G3AD_29U3PCI_CLK U13RXD_3H4AD_28V4CBE_0_V14RCLK_3G2AD_27U5AD_6Y15CD_3G1AD_26W4AD_5W15COL_3H3AD_25Y4AD_4V15TCLK_4J4AD_24V5AD_3Y16TXD_4H2CBE_3_U6AD_2W16TEN_4J3VDD5W5AD_1U15RXD_4J2IDSEL_Y5AD_0V16LBKJ1AD_23V6TCLK_0Y17RCLK_4K4AD_22W6TXD_0W17CD_4K3AD_21Y6TEN_0U16COL_4K2AD_20V7RXD_0V17TCLK_5K1AD_19U8RCLK_0U18TXD_5L3AD_18W7CD_0T17TEN_5L2AD_17Y7COL_0U19RXD_5M2AD_16V8TCLK_1U20RCLK_5M3CBE_2_U9TXD_1T18CD_5N1FRAME_W8TEN_1R17COL_5M4IRDY_V9RXD_1T19TCLK_6N2TRDY_W9RCLK_1T20TXD_6N3DEVSEL_Y9CD_1R18TEN_6P1STOP_U10COL_1R19RXD_6P2PERR_V10MCLK R20RCLK_6N4SERR_W10SYSCLK P18CD_6P3PAR Y10CLK20N17COL_6R1CBE_1_V11TCLK_2P19TCLK_7R2AD_15W11TXD_2P20TXD_7PMC-970109ISSUE 38 PORT ETHERNET SWITCHPIN SIGNAL PIN SIGNAL PIN SIGNALN18TEN_7F17MCS_1_D11MDATA_13M17RXD_7E18MCS_0_C11MDATA_12N19RCLK_7D20MRDY_B11MDATA_11M18CD_7D19MRD_A11MDATA_10M19COL_7E17MWEN_3_C10MDATA_9M20MADDR_19D18MWEN_2_B10MDATA_8L17MADDR_18C17MWEN_1_B9MDATA_7L18MADDR_17D16MWEN_0_C9MDATA_6L19MADDR_16B17MRAS_A8MDATA_5L20MADDR_15A17MDATA_31D9MDATA_4K18MADDR_14C16MDATA_30B8MDATA_3K19MADDR_13D15MDATA_29C8MDATA_2J19MADDR_12B16MDATA_28A7MDATA_1J18MADDR_11A16MDATA_27B7MDATA_0H20MADDR_10C15MDATA_26D8MGWE_J17MADDR_9B15MDATA_25C7MINTR_H19MADDR_8A15MDATA_24A6DBG_2H18MADDR_7C14MDATA_23B6DBG_1G20MADDR_6D13MDATA_22C6DBG_0G19MADDR_5B14MDATA_21A5PC_3H17MADDR_4A14MDATA_20B5PC_4G18MADDR_3C13MDATA_19D6PC_5F20MADDR_2D12MDATA_18C5PC_6F19MADDR_1B13MDATA_17A4PC_7F18MADDR_0C12MDATA_16B4PC_8E20MCS_3_B12MDATA_15D5PC_9E19MCS_2_A12MDATA_14C4PC_10D3N/C E4N/C D2N/CPMC-970109ISSUE 38 PORT ETHERNET SWITCHPin Signal Pin SignalB2VDD A1VSSB3A2B18A3B19A9C2A10C3A13C18A18C19A19D4A20D7B1D10B20D14C1D17C20G4H1G17J20K17K20L4L1P4M1P17N20U4V1U7V20U11W1U14W20U17Y1V2Y2V3Y3V18Y8V19Y11W2Y12W3Y18W18Y19W19Y20All VDD and VSS lines must be connected to supply and ground respectively. Standard decoupling practices should be followed for proper device operation.。