AT45D041中文技术说明
8051 模拟spi读写 AT45DB041
/*参数： */
unsigned char i;
for(i=0;i<8;i++){
if((wByte<<i)&0x80){SPI_SI=1;}
else{SPI_SI=0;}
SPI_SCK=0;
/* bit1 */
/* bit0 - 这2位暂时无效 */
/* bit5 */
/* bit4 */
SPI_HostWriteByte((unsigned char)(PA>>7));
SPI_HostWriteByte((unsigned char)((PA<<1)|(BFA>>8)));
SPI_HostWriteByte((unsigned char)BFA);
/* continue reading back at the beginning of the first page of memory.As w-*/
/* ith crossing over page boundaries,no delays will be incurred when wrapp-*/
/* first. */
/* 2005-06-02*/
/* nd clocked out of the device on the falling edge of SCK.All instruction-*/
/* s,addresses and data are transferred with the most significant bit(MSB) */
电能表可靠性技术论文
电能表可靠性技术研究【摘要】针对电能表可靠性技术研究问题，文中介绍了电能表硬件设计技术，主要有电能表电源管理监测、电能表输入信号滤波，探讨了电能表数据存储技术操作，分析了电能表电源监测电路及其原理，讨论决定电能表存储寿命因素，给出电能表存储结构和算法以提高寿命和靠性。
【关键词】多功能电能表；数据可靠性；数据存储0 引言多功能电能表可靠性技术，主要是可以准确提供多功能电能表检测电力线路的电流、电压信号，计算电流、电压、有功功率、无功功率，从而得到多功能电能表有功电能、无功电能，并保存在存储器中，给多功能电能表用户计量结算、状态检测提供依据。
多功能电能表可靠性技术的计算结果分为两大类：一是，暂时的、无需掉电保持的数据保，如电流、电压、功率等参数，可保存在随机存取存储器 ram中。
二是，需要长期保存的、掉电保持的数据，主要是多功能电能表的电能数据，必须存储到非易失性存储器中—通常采用flash闪存。
为保证多功能电能表在检测、采样、存取过程中信号完整性及数据可靠性，尤其是多功能电能表数据存取可靠性技术，需要从硬件和软件两个方面都采取措施，相互配合共同实现。
本文基于多功能电能表专用电能计量芯片att7022b，采用单片机pic16f77以及存储器 at45d041，研制了三相多功能电能表，现就将相关多功能电能表数据可靠技术进行探讨。
1 多功能电能表硬件设计技术多功能电能表硬件方面的可靠性技术主要包括电源监测管理以及输入信号的滤波调理的相关技术。
1.1 多功能电能表电源管理监测多功能电能表应用的单片机、att7022b、存储器等器件都只能在可靠的、有效的电源下才能工作。
多功能电能表的要求标准高，电源方案包括变压、整流、滤波、稳压等电路。
在三相电能表中，只要有一相电源供电，多功能电能表就必须工作，故使用三个单相变压器分别对三相电源输入进行隔离变压，再经过三个单相桥整流后并联输入电源管理与监测电路，此时可以得到多功能电能表稳定的直流电压 vz。
AT45DB041D-SU-2.5中文资料
Features Array•Single 2.5V or 2.7V to 3.6V Supply•RapidS® Serial Interface: 66 MHz Maximum Clock Frequency–SPI Compatible Modes 0 and 3•User Configurable Page Size–256 Bytes per Page–264 Bytes per Page•Page Program Operation–Intelligent Programming Operation–2,048 Pages (256/264 Bytes/Page) Main Memory•Flexible Erase Options–Page Erase (256 Bytes)–Block Erase (2 Kbytes)–Sector Erase (64 Kbytes)–Chip Erase (4 Mbits)•Two SRAM Data Buffers (256/264 Bytes)–Allows Receiving of Data while Reprogramming the Flash Array•Continuous Read Capability through Entire Array–Ideal for Code Shadowing Applications•Low-power Dissipation–7 mA Active Read Current Typical–25 µA Standby Current Typical–5 µA Deep Power-down Typical•Hardware and Software Data Protection Features–Individual Sector•Sector Lockdown for Secure Code and Data Storage–Individual Sector•Security: 128-byte Security Register–64-byte User Programmable Space–Unique 64-byte Device Identifier•JEDEC Standard Manufacturer and Device ID Read•100,000 Program/Erase Cycles Per Page Minimum•Data Retention – 20 Years•Industrial Temperature Range•Green (Pb/Halide-free/RoHS Compliant) Packaging Options1.DescriptionThe AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB041D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies up to 66 MHz. Its 4,325,376 bits of memory are organized as 2,048 pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB041D also contains two SRAM buffers of 256/264 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-tained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a RapidS serial interface to sequentially access its data. The simplesequential access dramatically reduces active pin count, facilitates hardware layout,23595H–DFLASH–03/07AT45DB041Dincreases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential.To allow for simple in-system reprogrammability, the AT45DB041D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB041D is enabled through the Serial Output (SO), and the Serial Clock (SCK).All programming and erase cycles are self-timed.2.Pin Configurations and PinoutsTable 2-1.Pin ConfigurationsSymbolName and FunctionAsserted StateTypeCS Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.Low InputSCK Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.–InputSI Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input includingcommand and address sequences. Data on the SI pin is always latched on the rising edge of SCK. If the SER/BYTE pin is always driven low, the SI pin should be a “no connect”.–InputSO Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. If the SER/BYTE pin is always driven low, the SO pin should be a “no connect”.–OutputWPWrite Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP pin functions independently of the software controlled protection method. After the WP pin goes low, the content of the Sector Protection Register cannot be modified.If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore the command and perform no operation. The device will return to the idle state once the CS pin has been deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be recognized by the device when the WP pin is asserted.The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to V CC whenever possible.Low InputRESET Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level.The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally.Low InputV CC Device Power Supply: The V CC pin is used to supply the source voltage to the device.Operations at invalid V CC voltages may produce spurious results and should not be attempted.–Power GNDGround: The ground reference for the power supply. GND should be connected to the system ground.–Ground33595H–DFLASH–03/07AT45DB041D3.Block DiagramFigure 2-1.MLF Top ViewFigure 2-2.SOIC Top View43595H–DFLASH–03/07AT45DB041D4.Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block or page level.Figure 4-1.Memory Architecture Diagram5.Device OperationThe device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 15-1 through 15-7. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first.Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the datasheet using the terminology BEA8 - BFA0 to denote the 9 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA10 - PA0 and BA8 - BA0, where PA10 - PA0 denotes the 11 address bits required to desig-nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte address within the page.For the “Power of 2” binary page size (256 bytes), the Buffer addressing is referenced in the datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology A18 - A0, where A18 - A8 denotes the 11 address bits required to desig-nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte address within a page.53595H–DFLASH–03/07AT45DB041D6.Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode.6.1Continuous Array Read (Legacy Command – E8H): Up to 66 MHzBy supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read from the DataFlash standard page size (264 bytes), an opcode of E8H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The first 11 bits (PA10-PA0) of the 20-bit address sequence specify which page of the main mem-ory array to read, and the last 9 bits (BA8-BA0) of the 20-bit address sequence specify the starting byte address within the page. To perform a continuous read from the binary page size (256 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes and 4 don’t care bytes. The first 11 bits (A18 - A8) of the 19-bits sequence specify which page of the main memory array to read, and the last 8 bits (A7 - A0) of the 19-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,the device will continue reading back at the beginning of the first page of memory. As with cross-ing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f CAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.6.2Continuous Array Read (High Frequency Mode – 0BH): Up to 66 MHzThis command can be used with the serial interface to read the main memory array sequentially in high speed mode for any clock frequency up to the maximum specified by f CAR1. To perform a opcode 0BH must be clocked into the device followed by three address bytes and a dummy byte. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main memory array to read, and the last 9 bits (BA8 - BA0) of the 20-bit address sequence spec-ify the starting byte address within the page. To perform a continuous read with the page size set to 256 bytes, the opcode, 0BH, must be clocked into the device followed by three address bytes (A18 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.63595H–DFLASH–03/07AT45DB041DThe CS pin must remain low during the loading of the opcode, the address bytes, and the read-ing of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will con-tinue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f CAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.6.3Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHzThis command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to maximum frequencies specified by f CAR2. To perform a continuous 03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main memory array to read, and the last 9 bits (BA8 - BA0) of the 20-bit address sequence specify the starting byte address within the page. To perform a contin-uous read with the page size set to 256 bytes, the opcode, 03H, must be clocked into the device followed by three address bytes (A18 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.The CS pin must remain low during the loading of the opcode, the address bytes, and the read-ing of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will con-tinue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.6.4Main Memory Page ReadA main memory page read allows the user to read data directly from any one of the 2,048 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the DataFlash standard page size (264 bytes), an opcode of D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The first 11 bits (PA10-PA0) of the 20-bit address sequence specify the page in main memory to be read, and the last 9 bits (BA8-BA0) of the 20-bit address sequence specify the starting byte address within that page.To start a page read from the binary page size (256 bytes), the opcode D2H must be clocked into the device followed by three address bytes and 4 don’t care bytes. The first 11 bits (A18 - A8) of the 19-bits sequence specify which page of the main memory array to read, and the last 8 bits (A7 - A0) of the 19-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are sent to initialize the read opera-tion. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main73595H–DFLASH–03/07AT45DB041Dmemory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the f SCK specification. The Main Memory Page Read bypasses both data buffers and leaves the contents of the buffers unchanged.6.5Buffer ReadThe SRAM data buffers can be accessed independently from the main memory array, and utiliz-ing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to the maximum specified by f CAR1. The D1H and D3H opcode can be used for lower frequency read operations up to the maximum specified by f CAR2.To perform a buffer read from the DataFlash standard buffer (264 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 don’t care bits and 9buffer address bits (BFA8-BFA0). To perform a buffer read from the binary buffer (256 bytes),the opcode must be clocked into the device followed by three address bytes comprised of 16don’t care bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one don’t care byte must be clocked in to initialize the read operation. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning the output pin (SO).7.Program and Erase Commands7.1Buffer WriteData can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the DataFlash standard buffer (264 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2,must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits and 9 buffer address bits (BFA8-BFA0). The 9 buffer address bits specify the first byte in the buffer to be written. To load data into the binary buffers (256 bytes each), a 1-byte opcode 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). The 8 buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will con-7.2Buffer to Main Memory Page Program with Built-in EraseData written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the DataFlash standard page size (264 bytes), the opcode must be followed by three address bytes consist of 4 don’t care bits, 11 page address bits (PA10 - PA0) that specify the page in the main memory to be written and 9 don’t care bits. To perform a buffer to main memory page program with built-in erase for the binary page size (256 bytes), the opcode 83H for buffer 1 or 86H for buffer 2, must be clocked into the device followed by three address bytes consisting of 5 don’t care bits83595H–DFLASH–03/07AT45DB041D11page address bits (A18 - A8) that specify the page in the main memory to be written and 8don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t EP . During this time,the status register will indicate that the part is busy.7.3Buffer to Main Memory Page Program without Built-in EraseA previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device. For the DataFlash standard page size (264 bytes), the opcode must be followed by three address bytes consist of 4 don’t care bits, 11 page address bits (PA10-PA0) that specify the page in the main memory to be written and 9 don’t care bits. To perform a buffer to main memory page program without built-in erase for the binary page size (256 bytes), the opcode 88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address bytes consisting of 5 don’t care bits, 11 page address bits (A18 - A8) that specify the page in the main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main mem-ory. It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t P . During this time, the status register will indicate that the part is busy.7.4Page EraseThe Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the DataFlash standard page size (264bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of 4 don’t care bits, 11 page address bits (PA10-PA0) that specify the page in the main memory to be erased and 9 don’t care bits.To perform a page erase in the binary page size (256 bytes), the opcode 81H must be loaded into the device, followed by three address bytes consist of 5 don’t care bits, 11 page address bits (A18 - A8) that specify the page in the main memory to be erased and 8 don’t care bits. When a state is a logical 1). The erase operation is internally self-timed and should take place in a maxi-mum time of t PE . During this time, the status register will indicate that the part is busy.7.5Block EraseA block of eight pages can be erased at one time. This command is useful when large amounts of data has to be written into the device. This will avoid using multiple Page Erase Commands.To perform a block erase for the DataFlash standard page size (264bytes), an opcode of 50H must be loaded into the device, followed by three address bytes comprised of 4 don’t care bits,8page address bits (PA10 - PA3) and 12 don’t care bits. The 8 page address bits are used to specify which block of eight pages is to be erased. To perform a block erase for the binary page size (256 bytes), the opcode 50H must be loaded into the device, followed by three address bytes consisting of 5 don’t care bits, 8 page address bits (A18 - A11) and 11 don’t care bits. The 9 page address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t BE . During this time, the status register will indicate that the part is busy.93595H–DFLASH–03/07AT45DB041D7.6Sector EraseThe Sector Erase command can be used to individually erase any sector in the main memory.There are 8 sectors and only one sector can be erased at one time. To perform sector 0a or sec-tor 0b erase for the DataFlash standard page size (264 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 4 don’t care bits, 8 page address bits (PA10 - PA3) and 12 don’t care bits. To perform a sector 1-7 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of 4 don’t care bits, 3 page address bits (PA10 - PA8) and 17 don’t care bits. To perform sector 0a or sector 0b erase for the binary page size (256 bytes), an opcode of 7CH must be loaded into the device,followed by three address bytes comprised of 5 don’t care bit and 8 page address bits (A18 -A11) and 11 don’t care bits. To perform a sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of 5 don’t care bit and 3 page address bits (A18 - A16) and 17 don’t care bits. The page address bits are used to specify any valid address location within the sector which is to be erased. When a low-to-high transition self-timed and should take place in a maximum time of t SE . During this time, the status register will indicate that the part is busy.Table 7-1.Block Erase AddressingPA10/A18PA9/A17PA8/A16PA7/A15PA6/A14PA5/A13PA4/A12PA3/A11PA2/A10PA1/A9PA0/A8Block 00000000X X X 000000001X X X 100000010X X X 200000011X X X 3••••••••••••••••••••••••••••••••••••11111100X X X 25211111101X X X 25311111110X X X 25411111111XXX255103595H–DFLASH–03/07AT45DB041D7.7Chip Erase (1)The entire main memory can be erased at one time by using the Chip Erase command.To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deas-serted to start the erase process. The erase operation is internally self-timed and should take place in a time of t CE . During this time, the Status Register will indicate that the device is busy.The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased.The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes.Figure 7-1.Chip EraseNote: 1.Refer to the errata regarding Chip Erase on page 52.Table 7-2.Sector Erase AddressingPA10/A18PA9/A17PA8/A16PA7/A15PA6/A14PA5/A13PA4/A12PA3/A11PA2/A10PA1/A9PA0/A8Sector 00000000X X X 0a 00000001X X X 0b 001X X X X X X X X 1010X X X X X X X X 2••••••••••••••••••••••••••••••••••••100X X X X X X X X 4101X X X X X X X X 5110X X X X X X X X 6111XXXXXXXX7Command Byte 1Byte 2Byte 3Byte 4Chip EraseC7H94H80H9AHAT45DB041D7.8Main Memory Page Program Through BufferThis operation is a combination of the Buffer Write and Buffer to Main Memory Page Programwith Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI)and then programmed into a specified page in the main memory. To perform a main memorypage program through buffer for the DataFlash standard page size (264 bytes), a 1-byte opcode,82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by threeaddress bytes. The address bytes are comprised of 4 don’t care bits, 11 page address bits,(PA10-PA0) that select the page in the main memory where data is to be written, and 9 bufferaddress bits (BFA8-BFA0) that select the first byte in the buffer to be written. To perform amain memory page program through buffer for the binary page size (256 bytes), the opcode 82Hfor buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytesconsisting of 5 don’t care bits, 11 page address bits (A18 - A8) that specify the page in the mainmemory to be written, and 8 buffer address bits (BFA7 - BFA0) that selects the first byte in thebuffer to be written. After all address bytes are clocked in, the part will take data from the inputpins and store it in the specified data buffer. If the end of the buffer is reached, the device willpin, the part will first erase the selected page in main memory to all 1s and then program thedata stored in the buffer into that memory page. Both the erase and the programming of thepage are internally self-timed and should take place in a maximum time of t EP. During this time,the status register will indicate that the part is busy.8.Sector ProtectionTwo protection methods, hardware and software controlled, are provided for protection againstinadvertent or erroneous program and erase cycles. The software controlled method relies onthe use of software commands to enable and disable sector protection while the hardware con-that are to be protected or unprotected against program and erase operations is specified in thenonvolatile Sector Protection Register. The status of whether or not sector protection has beenenabled or disabled by either the software or the hardware controlled methods can be deter-mined by checking the Status Register.。
ROM的选型
ROM的选型ROM用来存储程序代码，系统配置参数及系统运行过程中需要记录的各种信息。
目前常用的存储类型有Serial Flash、串行F-RAM、NAND Flash等。
FLASH：在线进行电擦写，掉电后信息不丢失的存储器。
低功耗、大容量，可整片或分扇区在线编程和擦除，通常用于存放程序代码、常量表以及一些在系统掉电后需要保存的用户数据等。
NOR和NAND是现在市场上两种主要的非易失闪存技术。
NOR FLASH的特点是芯片内执行(XIP，Execute In Place就位执行)，这样应用程序可以直接在FLASH闪存内运行，不必再把代码读到系统RAM中。
NOR 的传输效率很高，在1～4MB的小容量时具有很高的成本效益，但是很低的写入和擦除速度大大影响了它的性能。
NAND结构能提供极高的存储单元密度，可以达到高存储密度，并且写入和擦除的速度也很快。
应用NAND的困难在于flash的管理和需要特殊的系统接口。
接口差别：NOR带有SRAM接口，有足够的地址引脚来寻址，可以很容易地存取其内部的每一个字节。
NAND器件使用复杂的I/O口来串行存取数据，各个产品或厂商的方法个不相同。
8个引脚用来传送控制、地址和数据信息。
NAND读和写操作采用512字节的块，这一点有点像硬盘管理此类操作，很自然地，基于NAND的存储器就可以取代硬盘或其他块设备。
容量和成本：NAND的单元尺寸几乎是NOR器件的一半，由于生产过程更为简单，NAND 结构可以在给定的模具尺寸内提供更高的容量，也就相应地降低了价格。
NOR占据了容量1-16MB闪存市场的大部分，而NAND只是用在8-128MB 的产品当中，这也就说明了NOR主要应用于代码存储介质中，NAND适合于数据存储，NAND在CompactFlash、Secure Digital、PC Cards和MMC存储卡市场上所占份额最大。
同时NAND受到位反转和坏块的影响其单元尺寸几乎是NOR FLASH的一半，由于生产过程更为简单，NAND结构可以在给定的模具尺寸内提供更高的容量，也就相应地降低了成本。
IC卡基础知识
所谓IC卡，就是集成电路卡，英文叫做Integrated Circuit Card。
目前市场上IC卡的种类很多，通常有以下几种分类方式：1.按组成结构分类：一般存储卡(Memory Card)、逻辑加密存储卡(Security Card)、CPU卡（Smart Card）。
一般存储卡实际上就是普通的EEPROM，不过是封装成module嵌入到卡片上了而已。
只要实现电气接触就可以对其内部数据进行无条件访问(当然需要根据该型号EEPROM的电气规范了)。
这种卡安全性几乎为0，所以只能用于一些对安全性不作要求的场合。
逻辑加密存储卡，这种IC卡中除了封装了上述EEPROM存储器外,还专设有逻辑加密电路,提供了硬件加密手段.因此不但存储量大,而且安全性强,不但可保证卡上存储数据读写安全, 而且能进行用户身份的认证. 由于密码不是在读写器软件中而是存储于IC卡上,所以几乎没有破密的可能性.例如:美国ATMEL1604逻辑加密卡,卡上设有三级保密功能.总密码用于身份的认证,非法用户三次密码核对错误即可使卡报废. 四个数据存储区可分别存储不同信息,又各和独立的读写密码.可以做到一卡多用, 在不同读写器件中核实相应密码进行某一业务操作,不会影响其它存储区.卡上信息不能随意改写,改写前需先擦除,而擦除需核对擦除需要核对擦除密码. 这样即使是持卡人自己也不能随意更改卡上数据.因此这种逻辑加密卡保密性极强,能自动识别读写器,持卡人和控制操作类型,常用于安全性要求高的场合。
CPU卡:又叫智能卡，Smart Card,这是真正的卡上单片机系统,CPU卡片内集成了中央处理器CPU, 程序存储器ROM, 数据存储器EEPROM 和RAM, 一般ROM 中还配有卡上操作系统软件COS(Chip operating system).CPU卡上的微处理器可以执行COS监控程序,接收从读写器送来的命令和数据, 分析命令后控制对存储器的访问.由于这种卡具有智能,读写器对卡的操作要经过卡上COS,所以保密性更强.而且微处理器具有数据加工和处理的能力,可以对读写数据进行逻辑和算术运算,能力很强.这种IC卡存储的数据对外相当于一个-黑盒子, 保密性极强.目前IC卡上用的微处理器一般为8位CPU,存储容量几十KB上下. 此种智能卡常用于重要场合,作为证件和信用卡。
几种常用IC卡的特性
几种常用IC卡的特性1. AT24C01A/02/04/08/16/64卡该系列IC卡均为非加密存储卡，容量分别为1K，2K，4K，8K，16K，64K bit，只有读、写两种操作。
2. AT45D041卡AT45D041卡是非加密存储卡，容量为4M bit，整卡分为2048页，每页有264 byte 。
只有读、写两种操作。
3. AT88SC102卡AT88SC102为加密存储卡，容量为1K bit。
整卡分两个应用区，容量均为64 byte。
熔丝熔断前，各区的读、写和擦除，受总密码和读写保护位的控制，数据按字节擦除；熔丝熔断后，各区的读、写和擦除，受总密码、读写属性控制位和擦除密码的控制，只要正确核对分区擦除密码，整区数据将自动擦除。
4. AT88SC1601/1604卡AT88SC1601是加密存储卡，容量为16K bit。
整卡分为一个公用区和四个应用区，个人化之前，整个卡的访问受总密码和读写保护位的控制。
个人化之后，各区的读、写和擦除都要受总密码、分区密码、分区擦除密码和读写保护位的控制。
1604 与1601卡基本相同，它们的区别是：各个分区的容量不同；1601只是1区有密码计数器，而1604的4个分区都有密码计数器。
5. SLE4432/4442卡SLE4442为加密存储卡，容量为256 byte。
总密码核对正确之后，才可以对卡读、写操作。
该卡前32字节可进行写保护位操作。
总密码错误计数器值为3，核对错误一次，减1操作，若计数值为0，整卡数据锁死。
若3次内有一次核对正确，则计数器恢复初值。
SLE4432特性与4442相似，但无密码操作功能。
6. SLE4418/4428卡SLE4428为加密存储卡,容量为1K byte。
总密码核对正确之后，才可以对卡读、写操作。
该卡所有数据均可以写保护(固化数据)。
总密码错误计数器值为8。
SLE4418特性与4428相似，但无密码操作功能。
7. SLE4404卡SLE 4404是加密存储卡，容量为52 byte。
接触式IC卡读写器使用手册
目录第一章 DP系列接触式IC卡读写器简介 (3)1.1概述 (3)1.2读写器型号 (3)1.3装箱清单 (4)1.4读写器连接方式.... (4)1.5指示灯 (4)1.6程序安装 (4)1.7用户软件 (4)1.8技术指标 (5)第二章演示系统使用说明 (6)第三章 IC卡读写器驱动程序函数说明 (9)3.1 安装程序主要目录和文件 (9)3.2 函数使用规则 (9)3.3 各种库函数说明 (9)3.3.1 C语言接口函数库 (9)●通用函数库 (10)●AT24C01A/24C02/24C04/24C08/24C16/24C64 (13)●AT45D041 (14)●AT88SC102/1604/1604B (15)●AT93C46/93C46A (22)●SLE4404 (23)●SLE4406 (26)●SLE4418/4428 (28)●SLE4432/4442 (30)●CPU卡 (30)3.3.2 FOXPRO FOR DOS函数库 (33)3.3.3 WINDOWS 16位和32位动态库 (34)3.3.4 FOXBASE函数库 (35)3.3.5UNIX函数库 (38)3.3.6LINUX函数库 (38)3.4 VFP、VB、Delphi和PB调用动态库的方法 (38)3.4.1 VFP调用16位动态库的方法 (38)3.4.2 VFP调用32位动态库的方法 (39)3.4.3 VB调用动态库的方法 (40)3.4.4 Delphi调用32位动态库的方法 (41)3.4.5 PB调用32位动态库的方法 (42)3.4.6 VC调用32位动态库的方法 (42)3.5 IC卡类型代码 (43)3.6 函数错误类型代码 (43)3.7自动卡型测试函数原理说明 (44)附录一几种常用IC卡的特性 (45)[2000/05/10]DP-R-XXX第一章DP系列接触式IC卡读写器简介1.1 概述深圳市明华澳汉科技有限公司是以生产IC卡及开发IC卡相关设备为主导产品的高新科技企业。
AT45xxx多路温度测试仪用户手册说明书
AT45xxx多路温度测试仪用户手册2安全须知当你发现有以下不正常情形发生,请立即终止操作并断开电源线。
立刻与安柏科技销售部联系维修。
否则将会引起火灾或对操作者有潜在的触电危险。
l仪器操作异常。
l操作中仪器产生反常噪音、异味、烟或闪光。
l操作过程中，仪器产生高温或电击。
l电源线、电源开关或电源插座损坏。
l杂质或液体流入仪器。
安全信息为避免可能的电击和人身安全，请遵循以下指南进行操作。
免责声明用户在开始使用仪器前请仔细阅读以下安全信息，对于用户由于未遵守下列条款而造成的人身安全和财产损失，安柏科技将不承担任何责任。
仪器接地为防止电击危险，请连接好电源地线。
不可在爆炸性气体环境使用仪器不可在易燃易爆气体、蒸汽或多灰尘的环境下使用仪器。
在此类环境使用任何电子设备，都是对人身安全的冒险。
不可打开仪器外壳非专业维护人员不可打开仪器外壳，以试图维修仪器。
仪器在关机后一段时间内仍存在未释放干净的电荷，这可能对人身造成电击危险。
不要使用已经损坏的仪器如果仪器已经损害，其危险将不可预知。
请断开电源线，不可再使用，也不要试图自行维修。
不要使用工作异常的仪器如果仪器工作不正常，其危险不可预知，请断开电源线，不可再使用，也不要试图自行维修。
不要超出本说明书指定的方式使用仪器超出范围，仪器所提供的保护措施将失效。
声明：!, $, #,安柏标志和文字是常州安柏精密仪器有限公司的商标或注册商标。
QQ：285480356 55178055AT45xxx多路温度测试仪用户手册User’s Manual简体中文Simplified ChineseRev.A2 2009/11 @Instruments 常州安柏精密仪器有限公司©2005-2009 Applent Instruments, Inc.目录 5目录安全须知 (2)安全信息 (2)有限担保和责任范围 (4)1.安装和设置向导 (9)1.1装箱清单 (9)1.2电源要求 (9)1.3操作环境 (9)1.4清洗 (9)1.5仪器手柄 (11)2.概述 (12)2.1引言 (12)2.2测量功能 (12)2.2.1测量参数 (12)2.2.2测试速度 (12)2.2.3基本准确度 (12)2.2.4测量显示范围 (13)2.3主要功能 (13)2.3.1比较器功能 (13)2.3.2用户校正功能 (13)2.3.3文件功能 (13)2.3.4系统设置 (13)2.3.5接口 (13)3.开始 (14)3.1认识前面板 (14)3.1.1前面板描述 (14)3.1.2认识后面板 (15)3.2上电启动 (15)3.2.1开机 (15)3.2.2开机值 (15)4.[Meas] 测量主页面 (16)4.1<测量显示>页 (16)4.1.1【型号】 (16)<测量显示>页的信息栏 (17)4.2<曲线图>页 (17)5.【Setup】设置主页面 (18)5.1功能设置 (18)5.1.1【比较器】 (18)5.1.2【速度】 (19)5.1.3【讯响】 (19)5.1.4【音量】 (19)5.1.5【通讯】 (19)5.1.6【波特率】 (20)5.1.7【字体】 (20)5.1.8【巡检】 (20)5.2分选设置 (21)6AT45xxx系列多路温度测试仪用户手册5.2.1【001】 (21)5.3用户校正 (22)5.3.1【001】 (22)5.4U盘设置 (23)5.4.1【创建文件】 (23)5.4.2【采样时间】 (23)5.4.3【文件操作】 (23)6.系统配置 (24)6.1系统配置页 (24)6.1.1更改系统语言【LANGUAGE】 (24)6.1.2修改日期和时间 (25)6.1.3帐号设置 (25)6.2系统信息页 (26)7.文件操作 (27)7.1文件管理 (27)7.1.1【自动保存】开关 (27)7.1.2文件操作 (28)7.1.3快捷操作文件 (28)8.规格 (29)8.1技术指标 (29)8.2一般规格 (29)8.3外形尺寸 (30)目录7插图目录图1-1仪器手柄(示意图,面板图形与实际不符) (11)图3-1 前面板 (14)图3-2后面板 (15)4-1 <测量显示>页 (16)图5-1<设置>页 (18)图6-1<系统配置>页 (24)图6-2<系统信息>页 (26)图7-1<文件管理>页 (27)8AT45xxx系列多路温度测试仪用户手册表格目录表3-1 前面板功能描述 (14)表4-1参数描述 (16)安装与设置向导91.安装和设置向导感谢您购买我公司的产品！使用前请仔细阅读本章。
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主内存页编程 此操作是缓存写入和带内置擦除的缓存至主内存页编程操作的组合 数据首先由 SI 引脚输入缓存 1
或缓存 2 然后写入主内存指定页 8 bit 操作码 82H 为缓存 1 或 85H 为缓存 2 后跟 4 bit 保留位和 20 bit 地址 最高 11 bit 地址 PA10-PA0 选择主内存中要写入数据的页 后 9 bit 地址 BFA8BFA0 选择缓存中要写的首字节 在所有的地址输入后 器件将从 SI 引脚取数据 存入一个缓存 如 果达到缓存终端 器件将返回缓存始端 当 CS 引脚上发生由低至高的跳变时 器件将首先擦除主内存 中所选的页 使其为全 1 然后将存储在缓存中的数据写入主内存中的指定页 页的擦除和写入均内 部自定时 并发生在最大时间 tEP 之内 在此时间 状态寄存器将指示器件忙
无内置擦除的缓存至主内存页编程 主内存中预先擦除的页可写入缓存 1 或缓存 2 的内容 8 bit 操作码 88H 为缓存 1 或 89H 为缓存
2 后跟 4 bit 保留位 11 bit 地址 PA10-PA0 指定主内存中要写入的页 和 9 bit 任意数据 当 CS 引 脚上发生由低至高的跳变时 器件将把缓存中存储的数据写入主内存中的指定页 必要条件是 主内存 中要写入的页预先已写为全 1 擦除状态 页的写入是内部自定时的 并发生在最大时间 tP 之 内 在此时间 状态寄存器将指示器件忙
以通过一旦输出了 bit 7 就停止 SCK 的方法连续截取状态寄存器的 bit 7 bit 7 的状态将在 SO 引脚上连续输出 一旦器件不再忙 SO 的状态将由 0 变为 1 有 6 种操作能够
使器件处于忙状态 主内存页转存至缓存 主内存页与缓存比较 带内置擦除的缓存至主内存页编程 不带内置擦除的缓存至主内存页编程 主内存页编程和自动页重写
当 CS 引脚出现由低至高的跳变时 器件将首先将数据从主内存页转存到缓存 然后将数据从缓存写 回主内存中原来的页 操作是自定时的 并在最大时间 tEP 内完成 在此时间内 状态寄存器将指示器 件忙
如果主内存是逐页连续编程的 则推荐图 1 所示的编程算法 否则 如果主内存中一页内的多字节 或多页随机编程 推荐图 2 中所示的算法
为 4 bit 保留位 11 bit 地址 PA10-PA0 指定主内存中要转存的页 和 9 bit 任意数据 在向 SCK 引脚输入时钟以通过 SI 引脚载入操作码 地址和无关位的同时 必须保持 CS 引脚为低
电平 当 CS 引脚从低至高跳变时 主内存数据页向缓存的转存将开始 在数据页转存期间 tXFR
自动页重写 此模式仅当以随机方式修改一页内的多个字节或多页数据时才需要 此模式是两种操作的组合 主
内存页至缓存转存和带内置擦除的缓存至主内存页编程 一页数据首先从主内存转存至缓存 1 或缓存 2 然后同样的数据 从缓存 1 或缓存 2 写回主内存中的原始页 8 位操作码 58H 为缓存 1 或 59 为缓存 2 后跟 4 个保留位 指明主内存中所重写页的 11 个地址位 PA10-PA0 9 个附加的无关位
北京卡来通电子技术有限公司
Beijing Card Reader Electronic Technique Co.,
AT45D041
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AT45D041 技术说明
特点
• 单一 4.5V - 5.5V 电源 • 串行接口 • 支持页编程操作
– 单一循环编程 擦除并编程 – 2048 页 264 字节/页 主内存 • 具有两个 264 字节 SRAM 数据缓存 • 具有内部编程和控制定时器 • 快速页编程 典型 7 ms • 页至缓存典型传输时间 80 µs • 低功耗 – 典型工作状态读取电流 15 mA – 典型 CMOS 待命状态电流 20 µA • 最高时钟频率 10 MHz • 具有硬件数据保护功能 • 兼容串行外设接口 Mode 0 和 3 • 兼容 CMOS 和 TTL 输入及输出 • 适应商业和工业温度范围
主内存页与缓存比较的当前结果由状态寄存器的 bit 6 指示 如果 bit 6 为 0 则主内存页中的数据与 缓存中的数据相符 如果 bit 6 为 1 则主内存中的数据至少有 1 位与缓存中的数据不符
器件的集成度由状态寄存器的 bits 5, 4 和 3 指示 对于 AT45D041 此 3 位是 0 1 和 1 这 3 个二 进制位的十进制值并不等于器件的集成度 这 3 位代表了与串行 DataFlash 不同集成度相关的组合码 共有 8 种不同的集成度结构
地址 北京海淀区知春路 108 号豪景大厦 C 座 601 室 100086 电话 010-62104383 010-82104384 传真 010-62104385
北京卡来通电子技术有限公司
Beijing Card Reader Electronic Technique Co.,
AT45D041
带内置擦除的缓存至主内存页编程
写入缓存 1 或缓存 2 的数据可以写至主内存 8 bit 操作码 83H 为缓存 1 或 86H 为缓存 2 后跟 4 bit 保留位 11 bit 地址 PA10-PA0 指定主内存中要写入的页 和 9 bit 任意数据 当 CS 引脚上发生 由低至高的跳变时 器件将首先擦除主内存中所选的页 使其为全 1 然后将存储在缓存中的数据写 入主内存中的指定页 页的擦除和写入均内部自定时 并发生在最大时间 tEP 之内 在此时间 状态寄 存器将指示器件忙
方框图
北京卡来通电子技术有限公司
Beijing Card Reader Electronic Technique Co.,
AT45D041
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页 264 字节
FLASH 存储器矩阵
缓冲器 264 字节
缓冲器 264 字节 I/O 接口
器件操作
器件操作受来自主机处理器的指令控制 指令表及其相关的操作码见表 1 和表 2 有效的指令起始于 CS 的下降沿 含 8 bit 操作码和缓存或主内存地址 当 CS 为低电平时 跳变的 SCK 引脚电平控制操作 码和缓存或主内存地址通过 SI 串行输入 脚输入 所有的指令 地址和数据传送都是最高位在前
允许在对非易失性存储器编程的同时接收数据
说明
AT45D041 是单一 5V 供电串行接口 Flash 存储卡 适用于系统内重复编程 它共有 4,325,376 bits 内存 组织为 2048 页 每页 264 字节 处主内存之外 AT45D041 还有两个 SRAM 数据缓存 每个 264 字节 缓存使得主内存的一页正在编程的同时可以接收数据 与用多条地址线和一个并行接口随机 访问的传统 Flash 存储器不同 其数据闪存 DataFlash 采用串行接口顺序访问数据 这种简单的串行接 口方便了硬件布局 增强了系统灵活性 减小了切换噪声 压缩了封装尺寸和有效引脚数量 此器件是 针对要求大容量 低引脚数 低电压和低功耗的许多工商业应用优化的 DataFlash 的典型应用有数字语 音存储 图像存储和数据存储 器件工作时钟高达 10 MHz 典型工作状态读取电流损耗为 15 mA
引脚定义
引脚名称 CS SCK SI SO WP RESET RDY/BUSY
功能 片选 串行时钟 串行输入 串行输出 硬件页写入保护 片复位 就绪/忙
地址 北京海淀区知春路 108 号豪景大厦 C 座 601 室 100086 电话 010-62104383 010-82104384 传真 010-62104385
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可以读取状态寄存器以确定转存是否完成
主内存与缓存比较
主内存中的数据页可与缓存 1 或缓存 2 中的数据比较 8 bit 操作码 60H 为缓存 1 61H 为缓存 2 其后为 24 bit 地址 由 4 bit 保留位 11 bit 地址 PA10-PA0 指定主内存中要比较的页 和 9 bit 任意 数据组成 操作码和地址位的载入同上 在向 SCK 引脚输入时钟以通过 SI 引脚载入操作码 地址和无 关位的同时 必须保持 CS 引脚为低电平 当 CS 引脚从低至高跳变时 所选主内存页的 264 字节数据 将与缓存 1 或缓存 2 中的 264 字节数据比较 此期间 tXFR 状态寄存器将指示器件是否忙 当比较 操作完成时 状态寄存器的 bit 6 被更新位比较结果
地址 北京海淀区知春路 108 号豪景大厦 C 座 601 室 100086 电话 010-62104383 010-82104384 传真 010-62104385
北京卡来通电子技术有限公司
Beijing Card Reader Electronic Technique Co.,
AT45D041
缓存读取 数据可以通过两个缓存之一来读取 使用不同的操作码可指定使用哪个缓存 操作码 54H 是从缓存
1 读取数据 而操作码 56H 是从缓存 2 读取数据 在缓存读取指令中 8 bit 操作码之后 有 15 bit 任意 数据 9 bit 地址以及 8 bit 任意数据 因为缓存大小是 264 字节 需要 9 bit 地址 BFA8-BFA0 来指定 从缓存读取的首字节
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状态寄存器 状态寄存器可用于确定器件的就绪/忙状态 主内存页与缓存比较运算的结果 器件的集成度 要读
状态寄存器 必须向器件加载操作码 57H 当操作码的最后一位送入后 状态寄存器的 8 位 最高位 bit 7 在前 将在后续的 8 个时钟节拍中在 SO 引脚上送出 状态寄存器的高 5 位包含器件信息 剩余
读取 通过指定相应的操作码 可从主内存读取 也可以通过两个缓存之一读取
主内存页读取 通过主内存读取 可直接读取 2048 页中一页的数据 绕过数据缓存 且保持数据缓存中内容不变
页读取的指令是 8 bit 操作码 52H 后跟 24 bit 地址 以及 32 bit 任意内容 在 AT45D041 中 地址的 首 4 bit 是为更大容量的器件保留的 见第 8 页的注 紧接的 11 bit 地址 PA10-PA0 是页地址 之 后的 9 bit 地址 BA8-BA0 是页内的起始字节地址 24 bit 之后的 32 bit 无关内容用于初始化读取操 作 32 bit 无关字节之后 SCK 上的脉冲将使串行数据输出到 SO 串行输出 引脚上 在载入操作码 地址和读取数据期间 CS 引脚必须保持地点平 当主内存页读取中达到主内存页尾时 期间将继续读取 同一页的起始部分 在 CS 引脚上由低至高的跳变将使读操作终止 并使 SO 引脚处于高阻态