基本数字逻辑单元的设计

WHEN "0010" => q <= "10100100"; WHEN "0011" => q <= "10110000";
WHEN "0100" => q <= "10011001"; WHEN "0101" => q <= "10010010"; WHEN "0110" => q <= "10000010"; WHEN "0111" => q <= "11011000"; WHEN "1000" => q <= "10000000"; WHEN "1001" => q <= "10010000"; WHEN OTHERS => q <="11111111"; END CASE; END PROCESS; END seg-rtl;
DOWN TO 0); END shifter; ARCHITECTURE Alg OF shifter IS BEGIN PROCESS (sr, sl, data_in, ir, il) VARIABLE con：STD_LOGIC_VECTOR (0 TO 1);
BEGIN con: = sr & sl; CASE con IS WHEN "00" => data_out <= data_in; WHEN "01" => data_out <= data_in (6 DOWN TO 0) & il; --左移 WHEN “10” => data_out <= ir & data_in (7 DOWN TO 1); --右移 WHEN "11" => data_out <= data_in; END CASE; END PROCESS;
Gi Pi Gi1Pi Pi1Gi2 Pi Pi1 P1G0Pi Pi1 P0C0I
全加器的各位和为：
S i A iB iC Ii A iB iC Ii A iB iC Ii A iB iC Ii A i B i C Ii
4位超前进位加法器
LIBRARY IEEE; USE IEEE STD_LOGIC_1164.ALL; ENTITY adder4 IS PORT (a, b：IN STD_LOGIC_VECTOR (3DOWN TO 0 )
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shifter IS
PROT (data_in：IN STD_LOGIC_VECTOR (7 DOWN TO 0);
sr, sl, ir, il：IN STD_LOGIC; data_out：OUT STD_LOGIC_VECTOR (7
ci a b sum co
ci a b sum co
N位超 前进位 加法器
S0 S0
SUM CI A B
S1 S1
S2
S3 CO
S3
Sn-1 cout
SUM CI A B
SUM CI A B
SUM CI A B
CI0 A0 B0
CI1 A1 B1
CI2 A2 B2
进位产生逻辑
CIn-1 An-1 Bn-1
dout：OUT STD_LOGIC_VECTOR (7 DOWN TO 0);
en：IN STD_LOGIC); END tri_buf8;
ARCHITECTURE data_flow OF tri_buf8 IS PROCESS (en, din) BEGIN IF (en='1') THEN dout <= din; ELSE dout <= "ZZZZZZZZ"; END IF; END PROCESS;
P2: PROCESS (b, dir, en) BEGIN IF ((en='0') AND (dir='0')) THEN aout <= b; ELSE aout <= "ZZZZZZZZ"; END IF a <= aout; END PROCESS P2;
END rtl;
BCD码—段选码译码器。
4.1.4 运算器的设计
一位全加器的设计. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL； ENTITY full_adder IS PORT (a, b, ci： IN STD_LOGIC;
sum, cout： OUT STD_LOGIC); END full_adder; ARCHITECTURE rtl OF full_adder IS BEGIN
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL； ENTITY seg_del IS PORT (d：IN STD_LOGIC VECTOR (3 DOWN
TO 0 ); q：OUT BIT_VECTOR (7 DOWN TO 0)); END seg_del; ARCHITECTURE seg_rtl OF seg_del IS BEGIN PROCESS(d) BEGIN CASE d IS WHEN "0000" => q <= "11000000"; WHEN "0001" => q <= "11111001";
b a dir en
en dir
功能
1
X 高阻态
0
0 ab<<==ab
0
1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dobl_tri_buf8 IS PORT (a, b：INOUT STD_LOGIC_VECTOR (7 DOWN TO 0); END dobl_tri_buf8；
2.移位器 8bit移位器。
右移
D7 D6 D5 D4 D3 D2 D1 D0 d7 d6 d5 d4 d3 d2 d1 d0 d0
d7 d6 d5 d4 d3 d2 d1 d0 d7 d7 d6 d5 d4 d3 d2 d1 d0
左移
Ir sr sl dataa_out data_in il
8bit移位器的VHDL程序。
ARCHITECTURE rtl OF dobl_ tri_buf8 IS SIGNAL aout, bout：STD_LOGIC_VECTOR (7 DOWN TO 0 ); BEGIN P1: PROCESS (a, dir, en) BEGIN IF ((en='0') AND (dir='1')) THEN bout <= a; ELSE bout <="ZZZZZZZZ"; END IF; b <= bout; END PROCESS P1;
b：UT STD_LOGIC_VECTOR (7 DOWN TO 0)); END complement; ARCHITECTURE rtl OF complement IS BEGIN
b <= NOT a +”00000001”； END rtl;
4. 乘法器。
部分积右移8bit乘法器的设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mult IS
END Alg;
3. 求补器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL； USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY complement IS PORT (a：IN STD_LOGIC_VECTOR (7 DOWN TO 0);
PORT (ai, bi：IN STD_LOGIC_VECTOR (7 DOWN TO 0); Product：OUT STD_LOGIC_VECTOR (15 DOWN TO 0); done：OUT STD_LOGIC);
0101 5 1 0 0 1 0 0 1 0
0110 6 1 0 0 0 0 0 1 0
0111 7 1 0 1 0 0 1 1 1
1000 8 1 0 0 0 0 0 0 0
1001 9 1 0 0 1 0 0 0 0
其它
11111111
Vcc
fa b
e
g d
c
.h
BCD-段选码译码器 d0 d1 d2 d3
基本数字逻辑单元的设计
4.1 组合逻辑设计 4.1.2 三态缓冲器和总线缓冲器
8bit单向总线缓冲器 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_buf8 IS
PORT (din：IN STD_LOGIC_VECTOR (7 DOWN TO 0);
CI
A[0: n-1] B[0: n-1]
超前进位加法器 各位加法器产生进位的逻辑表达式为：
定义
为C 进位i生 O 成函A 数i,定B 义i (A i 为B 进i) 位传C 递函i数I , 则