SN74LS748N中文资料

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74LS48中文资料

74LS48中文资料

74LS48中文资料7段显示译码器74LS48是输出高电平有效的译码器,其真值表如下:灯测试输入端(LT)动态灭零输入端(RBI)74LS48/SN74LS48 引脚功能图工作电压:5V74LS48除了有实现7段显示译码器基本功能的输入(DCBA)和输出(Ya~Yg)端外,7448还引入了灯测试输入端(LT)和动态灭零输入端(RBI),以及既有输入功能又有输出功能的消隐输入/动态灭零输出(BI/RBO)端。

由7448真值表可获知7448所具有的逻辑功能:(1)7段译码功能(LT=1,RBI=1)在灯测试输入端(LT)和动态灭零输入端(RBI)都接无效电平(低电平)时,输入DCBA经74ls48译码,输出高电平有效的7段字符显示器的驱动信号,显示相应字符。

除DCBA = 0000外,RBI也可以接低电平,见表1中1~16行。

(2)消隐功能(BI=0)此时BI/RBO端作为输入端,该端输入低电平信号时,表1倒数第3行,无论LT 和RBI输入什么电平信号,不管输入DCBA为什么状态,输出全为“0”,7段显示器熄灭。

该功能主要用于多显示器的动态显示。

(3)灯测试功能(LT = 0)此时BI/RBO端作为输出端,端输入低电平信号时,表1最后一行,与及DCBA输入无关,输出全为“1”,显示器7个字段都点亮。

该功能用于7段显示器测试,判别是否有损坏的字段。

(4)动态灭零功能(LT=1,RBI=1)此时BI/RBO端也作为输出端,LT 端输入高电平信号,RBI 端输入低电平信号,若此时DCBA = 0000,表1倒数第2行,输出全为“0”,显示器熄灭,不显示这个零。

DCBA≠0,则对显示无影响。

该功能主要用于多个7段显示器同时显示时熄灭高位的零。

表1:(a)逻辑图(b)方框图(c)符号图由符号图可以知道,4号管脚端具有输入和输出双重功能。

作为输入(BI)低电平时,G21为0,所有字段输出置0,即实现消隐功能。

作为输出(RBO),相当于LT,及CT0的与坟系,即LT=1,RBI=0,DCBA=0000时输出低电平,可实现动态灭零功能。

74LS08中文资料_数据手册_参数

74LS08中文资料_数据手册_参数

5
PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION
Orderable Device JM38510/08003BCA
Status Package Type Package Pins Package
(1)
Drawing
Qty
ACTIVE
CDIP
1
TBD
J
14
1
TBD
N
14
TBD
N
14
TBD
N
14
TBD
N
14
TBD
D
14
50 Green (RoHS
& no Sb/Br)
D
14
50 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
POST-PLATE
POST-PLATE
A42
A42
A42
A42
A42
A42
A42
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type
N / A for Pkg Type

74芯片大全

74芯片大全

74芯片大全74芯片是一种常用的集成电路芯片,广泛应用于电子设备中。

本文将介绍一些常见的74芯片及其功能。

1. 74LS00 NAND闸门芯片:具有四个独立的两输入与非门,可用于逻辑门电路的设计与实现。

2. 74LS02 NOR闸门芯片:包含四个独立的两输入或非门,可用于逻辑门电路的搭建。

3. 74LS08 AND闸门芯片:包含四个独立的两输入与门,可用于逻辑门电路的组成。

4. 74LS32 OR闸门芯片:具有四个独立的两输入或门,用于逻辑门电路的设计。

5. 74LS74 双D触发器芯片:有两个D触发器,可用于时序电路的设计,如计数器、寄存器等。

6. 74LS86 XOR闸门芯片:含有四个两输入异或门,用于逻辑电路的设计。

7. 74LS138 3-8译码器芯片:具有三线至八线译码功能,用于地址选择和数据路复用。

8. 74LS151 8-1数据选择器芯片:有8个输入端和一个输出端,用于信号选择和数据传输。

9. 74LS161 4位二进制计数器芯片:可进行4位二进制计数和复位操作,适用于数字计数电路。

10. 74LS245 缓冲转换芯片:用于逻辑电平转换和信号缓冲,能够提供高电平和低电平的接口。

11. 74LS373 透明锁存器芯片:用于数据暂存和传输,可实现数据的存储和保持。

12. 74LS595 移位寄存器芯片:通过串行输入和并行输出,实现数据移位和存储的功能。

13. 74LS688 8位比较器芯片:用于比较两个8位二进制数的大小,并生成相应的输出信号。

14. 74LS139 双3-8译码器芯片:包含双3-8译码器,可实现高级逻辑电路的设计和实现。

15. 74LS240 缓冲器芯片:用于数据传输和信号缓冲,具有高驱动能力和低输出电平。

以上是一些常见的74芯片及其功能介绍。

这些芯片的功能多样,广泛应用于逻辑电路、计算机系统、通信设备、控制系统等领域中。

通过合理使用这些芯片,可以设计出高性能的电子设备和电路。

74l系列型号逻辑功能描述

74l系列型号逻辑功能描述

74l系列型号逻辑功能描述
74L系列是一种高性能低功耗半导体器件,由集成在芯片中的多个晶体管和电子元件
构成。

这种器件具有多种逻辑功能,可用于各种数字电路应用中。

在本篇文章中,我们将
对74L系列的一些常见型号进行逻辑功能描述。

1. 74LS00
74LS00是一种四输入NAND门。

它具有四个输入端口和一个输出端口。

当所有输入端
口电平都为高电平时,输出端口电平为低电平。

当任意一个输入端口电平为低电平时,输
出端口电平为高电平。

74LS74是一种双稳态触发器。

它具有两个输入端口和两个输出端口。

当输入端口电平变化时,输出端口的状态会保持不变,直到另一个输入端口电平变化。

总之,74L系列具有多种逻辑功能,包括AND门、OR门、NAND门、NOR门、XOR门和触发器等。

这些器件广泛应用于各种数字电路、计算机芯片、通讯设备、工业自动化等领域,为现代电子技术的发展做出了重要贡献。

74ls08

74ls08

74LS08介绍74LS08 是一种逻辑门芯片,属于 TTL(Transistor-Transistor Logic)系列。

它由四个 2 输入 AND 门组成,是一种四输入 AND 门。

特点74LS08 具有以下特点:•输入端电压范围:0V 到 5V•输出端电压范围:0V 到 5V•输入端的阻抗为10kΩ•输出能力为 8mA•工作温度范围为 -55°C 到 125°C•供电电压为 5V引脚说明74LS08 具有 14 个引脚,它们的功能如下:•Pin 1: 输入 A1•Pin 2: 输入 B1•Pin 3: 输出 Y1•Pin 4: 输入 A2•Pin 5: 输入 B2•Pin 6: 输出 Y2•Pin 7: GND(地)•Pin 8: 输入 A3•Pin 9: 输入 B3•Pin 10: 输出 Y3•Pin 11: 输入 A4•Pin 12: 输入 B4•Pin 13: 输出 Y4•Pin 14: VCC(电源)使用示例以下是一个使用 74LS08 的简单逻辑电路示例,它通过将两个 AND 门的输出连接到第三个 AND 门的输入上,实现了一个 4 个逻辑输入的 AND 逻辑。

+---|B1| +---|B3|| +---|B2| |+-|-+--+ 74LS08| |+-|-+--+ 74LS08| |+---|A1| +---|A3|| +---|B4| |+-|-+--+ 74LS08| |+-|-+--+| |+---|A4| +---|A2|+-|-+–+ 74LS08 | | +—|Y1 | +—|Y3| +—|Y2```•输入 A1、A2、A3、A4 分别连接到逻辑电路的四个逻辑输入•输入 B1、B2、B3、B4 分别连接到逻辑电路的四个逻辑输入•输出 Y1、Y2、Y3、Y4 分别作为逻辑电路的输出以上逻辑电路即为一个 4 个输入的 AND 逻辑电路,只有当所有输入均为高电平(5V)时,输出才会为高电平(5V),否则输出为低电平(0V)。

74ls74中文资料

74ls74中文资料

74ls74中文资料74ls74中文资料74LS74内含两个独立的D上升沿双d触发器,每个触发器有数据输入(D)、置位输入()复位输入()、时钟输入(CP)和数据输出(Q、)。

、的低电平使输出预置或清除,而与其它输入端的电平无关。

当、均无效(高电平式)时,符合建立时间要求的D数据在CP上升沿作用下传送到输出端。

74ls74功能表:输入输出S D R D CP D Qn+1 Qn+10 1 ×× 1 01 0 ××0 10 0 ××φ φ1 1 ↑ 1 1 01 1 ↑0 0 11 1 ↓×Qn Qn图1 74ls74引脚图实验:用74LS74构成4位寄存器一个D触发器可实现一位二进数的存储,因此应采用4个D触发器实现4位寄存器。

由于要实现移位寄存,4个D触发器之间应相互联接。

(1)首先在图2中完成相应的联线,构成可实现并入并出、串入串出、并入串出、串入并出的多功能移位寄存。

按图接好电路。

(2) D3 D2 D1 D0分别接逻辑开关,Q3 Q2 Q1 Q0接发光二极管;(3) 先清零;(4) 按下列要求,实现相应功能,观察结果,并描述工作过程。

并入并出:使数据输入端D3D2D1D0=1011,给CP端输入一个正单脉冲,观察Q3Q2Q1Q0发光二极管的状态,、将结果填入表中。

并入串出:使数据输入端D3D2D1D0=1011,给CP端输入4个正单脉冲,观察Q3端发光二极管的状态,将结果填入表6中。

串入并出:使数据输入端D0分别为1011,同时通过给CP端输入正单脉冲将D0端的4 个数据送入寄存器。

观察Q3Q2Q1Q0端发光二极管的状态,将结果填入表中。

串入串出:使数据输入端D0分别为1011,同时通过给CP端输入正单脉冲,将D0端的4 个数据送入寄存器。

在CP端输完8个脉冲后,观察Q3端发光二极管的状态,将结果填入表2中。

并入并出:D3D2D1D0=10111个CP脉冲Q3Q2Q1Q0=结论:并入串出D3D2D1D0=10114个CP脉冲Q3=结论串入并出D3=10114个CP脉冲Q3Q2Q1Q0=结论串入串出D3=10118个CP脉冲Q3=结论图274ls153芯片管脚图引脚逻辑功能以及封装2007年12月17日 23:53 本站原创作者:本站用户评论()关键字:74ls153管脚图逻辑功能图封装:74LS163引脚功能表及管脚定义图(带时序波形图)发布:2011-08-30 | 作者: | 来源: huangjiapeng| 查看:2620次 | 用户关注:定时器由与系统秒脉冲(由时钟脉冲产生器提供)同步的计数器构成,要求计数器在状态信号ST作用下,首先清零,然后在时钟脉冲上升沿作用下,计数器从零开始进行增1计数,向控制器提供模5的定时信号TY和模25的定时信号TL。

74系列中文资料(超级全)

74系列中文资料(超级全)

┌┴─┴─┴─┴─┴─┴─┴┐ 双 D 触发器 74LS74
│14 13 12 11 10 9 8 │


│ 1 2 3 4 5 6 7│
└┬─┬─┬─┬─┬─┬─┬┘
1Cr 1D 1Ck 1St 1Q -1Q GND
Vcc 8Q 8D 7D 7Q 6Q 6D 5D 5Q ALE
┌┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┐ 8 位锁存器 74LS373
Vcc -G B1 B2 B3 B4 B8 B6 B7 B8
┌┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┐ 8 位总线驱动器 74LS245
│20 19 18 17 16 15 14 13 12 11│

│ DIR=1 A=>B
│ 1 2 3 4 5 6 7 8 9 10│ DIR=0 B=>A
└┬─┬─┬─┬─┬─┬─┬─┬─┬─┬┘
___

│ Y = A+B
│ 1 2 3 4 5 6 7│
└┬─┬─┬─┬─┬─┬─┬┘
1Y 1A 1B 2Y 2A 2B GND
Vcc 2Y 2B 2A 2D 2E 1F
┌┴─┴─┴─┴─┴─┴─┴┐ 双与或非门 74S51
│14 13 12 11 10 9 8│
_____

│ 2Y = AB+DE
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
正逻辑与门,与非门:
Vcc 4B 4A 4Y 3B 3A 3Y
┌┴─┴─┴─┴─┴─┴─┴┐
│14 13 12 11 10 9 8│
Y = AB )
│ 2 输入四正与门 74LS08
│ 1 2 3 4 5 6 7│

SN74LS74AD中文资料

SN74LS74AD中文资料

Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)JM38510/00205BCA OBSOLETE CDIP J14TBD Call TI Call TIJM38510/00205BDA OBSOLETE CFP W14TBD Call TI Call TIJM38510/00205BDA OBSOLETE CFP W14TBD Call TI Call TIJM38510/07101BCA ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCJM38510/07101BCA ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCJM38510/07101BDA ACTIVE CFP W141TBD Call TI Level-NC-NC-NCJM38510/07101BDA ACTIVE CFP W141TBD Call TI Level-NC-NC-NCJM38510/30102B2A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCJM38510/30102B2A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCJM38510/30102BCA ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCJM38510/30102BCA ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCJM38510/30102BDA ACTIVE CFP W141TBD Call TI Level-NC-NC-NCJM38510/30102BDA ACTIVE CFP W141TBD Call TI Level-NC-NC-NCJM38510/30102SCA ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCJM38510/30102SCA ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCJM38510/30102SDA ACTIVE CFP W141TBD Call TI Level-NC-NC-NCJM38510/30102SDA ACTIVE CFP W141TBD Call TI Level-NC-NC-NC SN5474J OBSOLETE CDIP J14TBD Call TI Call TISN5474J OBSOLETE CDIP J14TBD Call TI Call TISN54LS74AJ ACTIVE CDIP J141TBD Call TI Level-NC-NC-NC SN54LS74AJ ACTIVE CDIP J141TBD Call TI Level-NC-NC-NC SN54S74J ACTIVE CDIP J141TBD Call TI Level-NC-NC-NC SN54S74J ACTIVE CDIP J141TBD Call TI Level-NC-NC-NC SN7474DR OBSOLETE SOIC D14TBD Call TI Call TISN7474DR OBSOLETE SOIC D14TBD Call TI Call TISN7474N OBSOLETE PDIP N14TBD Call TI Call TISN7474N OBSOLETE PDIP N14TBD Call TI Call TISN7474N3OBSOLETE PDIP N14TBD Call TI Call TISN7474N3OBSOLETE PDIP N14TBD Call TI Call TISN74LS74AD ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74AD ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADBR ACTIVE SSOP DB142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADBR ACTIVE SSOP DB142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADBRE4ACTIVE SSOP DB142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADBRE4ACTIVE SSOP DB142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADE4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LS74ADE4ACTIVE SOIC D1450Green(RoHS&CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)no Sb/Br)SN74LS74ADR ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADR ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADRE4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ADRE4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LS74AJ OBSOLETE CDIP J14TBD Call TI Call TISN74LS74AJ OBSOLETE CDIP J14TBD Call TI Call TISN74LS74AN ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS74AN ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74LS74AN3OBSOLETE PDIP N14TBD Call TI Call TISN74LS74AN3OBSOLETE PDIP N14TBD Call TI Call TISN74LS74ANE4ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS74ANE4ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS74ANSR ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ANSR ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ANSRG4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS74ANSRG4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74D ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74D ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74DE4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74DE4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74DR ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74DR ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74DRE4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74DRE4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74N ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S74N ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S74N3OBSOLETE PDIP N14TBD Call TI Call TIOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)SN74S74N3OBSOLETE PDIP N14TBD Call TI Call TISN74S74NE4ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S74NE4ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S74NSR ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74NSR ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74NSRE4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S74NSRE4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SNJ5474J OBSOLETE CDIP J14TBD Call TI Call TISNJ5474J OBSOLETE CDIP J14TBD Call TI Call TISNJ5474W OBSOLETE CFP W14TBD Call TI Call TISNJ5474W OBSOLETE CFP W14TBD Call TI Call TI SNJ54LS74AFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS74AFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS74AJ ACTIVE CDIP J141TBD Call TI Level-NC-NC-NC SNJ54LS74AJ ACTIVE CDIP J141TBD Call TI Level-NC-NC-NC SNJ54LS74AW ACTIVE CFP W141TBD Call TI Level-NC-NC-NC SNJ54LS74AW ACTIVE CFP W141TBD Call TI Level-NC-NC-NC SNJ54S74FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S74FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCSNJ54S74J ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCSNJ54S74J ACTIVE CDIP J141TBD Call TI Level-NC-NC-NCSNJ54S74W ACTIVE CFP W141TBD Call TI Level-NC-NC-NCSNJ54S74W ACTIVE CFP W141TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other 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10-LINE-TO-4-LINE
AND 8-LINE-TO-3-LINE
PRIORITY ENCODERS
The SN54/74LS147 and the SN54/74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level.
The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level.
The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry.
The SN54/74LS748 is a proprietary Motorola part incorporating a built-in deglitcher network which minimizes glitches on the GS output. The glitch occurs on the negative going transition of the EI input when data inputs 0–7 are at logical ones.
The only dc parameter differences between the LS148 and the LS748 are that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.
The only ac difference is that t PHL from EI to EO is changed from 40 to 45ns.
SN54/74LS147
(TOP VIEW)
OUTPUT INPUTS OUTPUT
45678C B
INPUTS OUTPUTS
SN54/74LS148
SN54/74LS748
(TOP VIEW)
OUTPUTS INPUTS OUTPUT
3210
4567E1A2A1
INPUTS OUTPUTS。

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