西南交大 实验8 指令存储器与取指令部件的设计

实验8 指令存储器与取指令部件的设计
西南交大计算机组成原理实验（代码）
实验要求:建立256*16的指令存储器ROM,将它关联到元件IPM-Rom，有PC 值决定存储器地址，PC有清零，置数，自动加一，自动减一功能，并将指令输出到数码管显示。

实验原理：建立内存文件，256代表内存地址是8位，16代表内存数据是16位实验代码：
PC：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is
port(clk,reset,load,add:in std_logic;
inn:in std_logic_vector(7 downto 0);
output:buffer std_logic_vector(7 downto 0));
end;
architecture one of PC is
begin
process(clk)
begin
--wt<=load&add;
if clk'event and clk='1' then
if reset='1' then output<="00000000";
else if load='1' then output<=inn;
else if add='1' then output<=output+1;
else output<=output-1;
end if;
end if;
end if;
end if;
end process;
end;
FRQ：用于分频
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FRQ is
port(clk_in:in std_logic;
clk_out:out std_logic);
end;
architecture one of FRQ is
signal temp:std_logic_vector(2 downto 0);
begin
process(clk_in)
begin
if clk_in'event and clk_in='1' then
temp<=temp+1;
clk_out<=temp(2);
end if;
end process;
end;
IR：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IR is
port(clk1,clk2,aadd:in std_logic;
input:in std_logic_vector(15 downto 0);
sel:buffer std_logic_vector(2 downto 0);
outadd:out std_logic;
led7:out std_logic_vector(7 downto 0));
end;
architecture one of IR is
signal sel_temp:std_logic_vector(2 downto 0);
signal data:std_logic_vector(3 downto 0);
begin
process(clk1,clk2)
begin
if clk1'event and clk1='1' then
if aadd='1' then outadd<='1';
else outadd<='0'; end if;
end if;
if clk2'event and clk2='1' then
sel_temp<=sel_temp+1;
if sel_temp>="011" then sel_temp<="000"; end if;
sel<=sel_temp;
case sel_temp is
when"000"=>data<=input(15 downto 12);
when"001"=>data<=input(11 downto 8);
when"010"=>data<=input(7 downto 4);
when"011"=>data<=input(3 downto 0);
when others=>null;
end case;
end if;
case data is
WHEN "0000"=> led7<="00111111";--0
WHEN "0001"=> led7<="00000110";--1
WHEN "0010"=> led7<="01011011";--2
WHEN "0011"=> led7<="01001111";--3
WHEN "0100"=> led7<="01100110";--4
WHEN "0101"=> led7<="01101101";--5
WHEN "0110"=> led7<="01111101";--6
WHEN "0111"=> led7<="00000111";--7
WHEN "1000"=> led7<="01111111";--8
WHEN "1001"=> led7<="01101111";--9
WHEN "1010"=> led7<="01110111";--10
WHEN "1011"=> led7<="01111100";--11
WHEN "1100"=> led7<="00111001";--12
WHEN "1101"=> led7<="01011110";--13
WHEN "1110"=> led7<="01111001";--14
WHEN "1111"=> led7<="01110001";--15
WHEN OTHERS =>NULL;
end case;
end process;
end;
原理图：
内存文件：
引脚锁定：。