AnalogIC_Lecture07_Bandgap
bandgap设计教程
1 : 1V REF∂V 考虑版图，N可取8R3=R0, R4=R2, M3=M2,R3R0R4R2M3M2运放的失调必须控制好具体设计请参考基准电压与电流201R R V V V BEBE REF ⋅Δ+=Ref:sansen 0ln 21R R N q kT V V BE REF ⋅⋅+=−~m1156mVchapter 16()T C T V V g BE +=λ00For I DS T ln qR N kT I BG⋅=Is PTAT0qVBG 通常在1.2左右结合电阻的温度系数，IBG 在高温与低温下其值变化可能较大，若用它直接去偏置其他电路，这一点须特别注意IBG~T 注意到：IBG T 时，gm constant二次补偿：VBG 的温度特性包含抛物线型非线性项，设计中令顶点位于常温附近，更高精度要求可采用二次补偿电路（例sansen ppt 1626）简单的电阻补偿：ln NkT I BG ⋅=若采用负温度系数的电阻，有可能降低非线性，实现更小的温度系数qR 例：设置不同的电阻温度系数，并在每个系数下调整电阻比例至最佳输出状态Tr1 = 1m Tr1 = ‐2m Tr1 = ‐3m温度系数——不同的Corner下，会有不同的温度系数，希望通过调整电阻比例，将温度系数调整至最佳状态调整至最佳状态；输出电压值：由于失配，或工艺起伏，输出电压会在一个范围内变化，系统通过调整电阻比例，将变化的范围控制得小一些。
电路设计：将电阻分段，并加开关控制；校准策略：批校准；每个校准校准策略批校准每个校准启动与稳定性启动：这个电路有两个稳定工作点，其中一个是两个支正反馈负反馈启动电路回路回路静态损耗:VDD/RESOpa RC VBG MOSCAPVREF ‐Vos +抑制/噪声采1/f噪声还可采用chopping技术V/I转换V/V转换R1=R2VBG的大小可通过整, 不影响温度系数IBG=VBG/R3,由IBG温漂较小，主要取决于电阻温度系数最低电源电压可正反馈环负反馈环MOSResistor正常输出下VBG>VTn, 否则应采用其他形式的启动电路MOSCAPPMOS采用folded结构采用PMOS输入差分对, 减少1/f噪声, 并适合于低输入共模的情况VGS‐VT小, 其他电流镜VGS‐VT大, 晶体管的L要大一些, 减输入差分对GS GS要大些少失调, 1/f噪声, 以及沟道调制效应自便置设计启动时，vb1若为高，则无法启动，故需增加拉低vb1低压设计将R1, R2由两个电阻串联，取中间点接运放输入，可降低输共模步降低压压入共模，进一步降低电压电压要求运放采用PMOS输入的folded‐cascode结构或symmetrical结构可进一步采用电路设计技术来降低运放对电源电压的要求‐BandgapSub1V ExampleRef: Ka Nang Leung, JSSC2002采用symmetrical结构和电平移位(level shifting)来降低输入共模要求ip inPhase 1in ipPhase 2。
商务英语写作-电子电器英语：单词大解码
商务英语写作电子电器英语：单词大解码1 backplane 背板2 band gap voltage reference 带隙电压参考3 benchtop supply 工作台电源4 block diagram 方块图5 bode plot 波特图6 bootstrap 自举7 bottom fet bottom fet8 bucket capcitor 桶形电容9 chassis 机架10 combi-sense combi-sense11 constant current source 恒流源12 core sataration 铁芯饱和13 crossover frequency 交叉频率14 current ripple 纹波电流15 cycle by cycle 逐周期16 cycle skipping 周期跳步17 dead time 死区时间18 die temperature 核心温度19 disable 非使能，无效，禁用，关断20 dominant pole 主极点21 enable 使能，有效，启用22 esd rating esd额定值23 evaluation board 评估板24 exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specified in the electrical characteristics section is not implied. 超过下面的规格使用可能引起永久的设备损害或设备故障。
建议不要工作在电特性表规定的参数范围以外。
25 failling edge 下降沿26 figure of merit 品质因数27 float charge voltage 浮充电压28 flyback power stage 反驰式功率级29 forward voltage drop 前向压降30 free-running 自由运行31 freewheel diode 续流二极管32 full load 满负载33 gate drive 栅极驱动34 gate drive stage 栅极驱动级35 gerber plot gerber 图36 ground plane 接地层37 henry 电感单位：亨利38 human body model 人体模式39 hysteresis 滞回40 inrush current 涌入电流41 inverting 反相42 jittery 抖动43 junction 结点44 kelvin connection 开尔文连接45 lead frame 引脚框架46 lead free 无铅47 level-shift 电平移动48 line regulation 电源调整率49 load regulation 负载调整率50 lot number 批号51 low dropout 低压差52 miller 密勒53 node 节点54 non-inverting 非反相55 novel 新颖的56 off state 关断状态57 operating supply voltage 电源工作电压58 out drive stage 输出驱动级59 out of phase 异相60 part number 产品型号61 pass transistor pass transistor62 p-channel mosfet p沟道mosfet63 phase margin 相位裕度64 phase node 开关节点65 portable electronics 便携式电子设备66 power down 掉电67 power good 电源正常68 power groud 功率地69 power save mode 节电模式70 power up 上电71 pull down 下拉72 pull up 上拉73 pulse by pulse 逐脉冲(pulse by pulse)74 push pull converter 推挽转换器75 ramp down 斜降76 ramp up 斜升77 redundant diode 冗余二极管78 resistive divider 电阻分压器79 ringing 振铃80 ripple current 纹波电流81 rising edge 上升沿82 sense resistor 检测电阻83 sequenced power supplys 序列电源84 shoot-through 直通，同时导通85 stray inductances. 杂散电感86 sub-circuit 子电路87 substrate 基板88 telecom 电信89 thermal information 热性能信息90 thermal slug 散热片91 threshold 阈值92 timing resistor 振荡电阻93 top fet top fet94 trace 线路，走线，引线95 transfer function 传递函数96 trip point 跳变点97 turns ratio 匝数比，=np / ns。
04-18种BACnet对象说明
BACNET对象说明目录1 Analog Input---模拟输入对象 (2)2AnalogOutput--模拟输出对象 (6)3 AnalogValue--模拟值对象 (9)4 Binary Input--二进制输入对象 (11)5 Binary Output 二进制输出对象 (14)6 Binary Value--二进制值对象 (17)7. Calendar（日期表）对象 (21)8. Command（命令）对象 (23)9.Device（设备）对象 (25)10. Event Enrollment（事件登录）对象 (29)11 File(文件)对象 (32)12 Group（组）对象 (34)13 Loop(控制环)对象 (36)14 Multi-State Input(多态输入)对象 (39)15 Multi-State Output(多态输出)对象 (41)16 Notification Class(通告类)对象 (44)17 Program(程序)对象 (46)18 Schedule(时间安排)对象 (48)1 Analog Input---模拟输入对象例子：读取AI对象的Present_Value属性。
----------------------------------MSTP---LPDU---------------------------------------55 FF --前导码02 --帧类型64 --目标地址EE --源地址00 16 --帧数据部分长度(22个byte)2E --帧头CRC校验高位在先--------------------------------------NPDU------------------------------------------------------PCI01---BACnet协议版本号04 ---00000100 bit7:表示传输的是APDU报文Bit5:0 和Bit3:0 表示DNET,DLEN,HopCount,SNET,SLEN,SARD都不存在。
bandgap
M2
VDD
M3
M2
VDD M3
M2
VDD M3
N Q4
R1
1 Q5 VO
N Q4
R1
Q6
1
Q5
VO
N Q4
R1
1 Q5 VO
R2 a)
GND
R2
R4
GND b)
R2 c)
GND
Fig. 1: Basic BiCMOS bandgap circuit with a) no beta-booster,b) emitter-follower beta-booster, and c) op-amp beta-booster.
Optimal Noise and Mismatch Budgeting
Bandgap Notes from Paul Gray
Basic Bandgap Topology
Bandgap Design Equations
Bandgap Headroom Constraints
BiCMOS Bandgap Noise Analysis
σIon :=
Inputs
4⋅4⋅k⋅Temp ⋅ 2 ⋅ 2⋅Io 3 VDSsato
Output Current Noise Specification
Model File
optimal current derivation
General Bandgap Notes
_______________________________________
Almost all reference circuits have multiple stable operating points and require additional start-up circuitry to insure the main circuit is the correct region of operation. The design and sizing of the start-up circuitry is described in a later section. Short channel effects are not added, because the lengths are usually made long for bandgap circuits to improve matching and reduce 1/f noise. The extra length hurts bandwidth, but bandgaps are primarily DC bias circuits, so BW doesn't matter as much.
Bandgap Reference Voltage
Bandgap Reference VoltageChun-Ping Huang, Ying-Shun Chuang, Tzu-Hen Hsucphuang@Abstract-A bandgap reference voltage is an essential component of an analog-to-digital converter. It is often used to supply a reference voltage which is compared with other voltages. There are some problems arising from temperature-dependent to power supply rejection ratio when implementing a bandgap reference circuit. The main design criteria for this project is toachieve PSRR above 60dB and a variation less than 3% resulting from temperature changes between 27℃ and 85℃. The wholearchitecture is shown in Fig. 1Figure 1 Circuit of BGR1. IntroductionThe bandgap reference used in diverse applications is based on the idea of Hilbiler in 1964[1]. A bandgap reference voltage with low sensitivity to temperature and supply voltage is commonly required in analog or digital circuits. There are several methods to realize a temperature independent voltage. The base emitter junction used as a core component of the bandgap reference is the most popular approach. The general bandgap reference voltage is described by a linear combination of base-emitter voltage. We can compensate temperature dependent voltage by adding a positive-TC voltage to a negative-TC voltage. The temperature behavior of a pn junction voltage is described by2ln g c BE T TT s s E I V V V V T T I I KT ∂∂=−−∂∂ where is the thermal voltage. With T at room temperature and =750mv,T V BE V 1.5/o BEV mv K T∂≈−∂. The positive-TC voltage comes from the voltage difference between two pn junctions. The Fig. 2 shows the reason behind positive-TC voltage.12ln ln ln c c BE BE BE T T T S SI IV V V V V V I nI −=∆=−=nwhere n equals to the current density ratio ofto .2Q 1QFigure 2 Generation of temperature independent voltage Ideally, adding a positive-TC voltage to anegative-TC voltage can realize a zero temperature coefficient 1.26V at the room temperature. Additionally, the reference voltage is required to be robust to the power supply voltage. An easy way to improve power supply rejection ratio (PSRR) is to increase the open loop gain.2. Circuit of the BGRA. Start Up CircuitThe transistors have two states, on and off,when power is provided. In order to make sure the circuit works properly, we need a mechanism which can provide a small current to flow through Op Amp and enableit. This mechanism is also required to beturned off when Op Amp works properly. The start up circuit [2] is presented in Fig. 3. The start-up circuit consists of transistors, M13-M15. The mechanism works as the following. Since M13 is also in saturation, it provides a sufficient gate voltage for M15 to turn on. When M15 is on, a small current will flow through Op Amp and enable the entire circuit. Furthermore, M14 will turn on and sink all the current from M13 and disable M15. Then the start-up circuit isdisabled.Figure 3 Start up circuitB. Differential AmplifierIn the circuit depicted in Fig 4., we need to force node X and Y to have the same voltage. We use an operational amplifier for this purpose. It is composed by thecommon-source stages with diode-connected loads. In order to increase the gain, we stack two pmos transistors into it and its gain can be expressed as()108860810//v m m mb o o A g g g r r r ≈+⎡⎤⎣⎦Its output provides a bias for the entire circuits, and a feedback loop is formed. Therefore, this bias voltage ideally provides a constant gs V for the pmos transistors anda constant current can be obtained.Figure 4 Differential gain stageC. BandgapFig. 5 [3] [5] shows the basic bandgap circuit. Because of high gain of Op Amp, the voltage at node X and Y is forced to be equal.Figure 5 Bandgap circuitX V ===+Y V 1BE V 2BE V 11I R × whereln(cBE T sI V V I =. Therefore,121ln BE BE T V V V n I R −==×1The voltage difference between the two pn junctions is the positive-TC voltage. Thecurrent across 1R equals to 1ln()TV n R which is called the proportional to absolute temperature (PTAT) current. A PTAT current can be copied from the current mirror and can be adjusted by changing the width of M12 or the resistance of 1R . Adding a positive-TC voltage 22I R to a base-emittervoltage, the negative-TC voltage, canachieve a temperature independent voltage.The ideally reference voltage equals 321ln() 1.26T ref BE V n V V R V R =+=The n is usually chosen to be eight for the layout purpose. 3. SimulationThe reference voltage is required to be 1.26V at the room temperature. The relationship between reference voltage and base-emitter voltage is given by32ref BE V V I R 2=+ (1)The base-emitter voltage is 0.75V at 25℃. We can set the PTAT current going through 2R to be 54µA. Therefore, from the equation (1), the resistance of 2R can bedetermined by 1.260.759.454V VK µ−≈For Cadence simulation, the appropriate 2R is 9.37K. Fig. 6 shows the reference voltage changes with temperature ranging from 27℃ to 85℃ and 10 % supply voltage variation. The reference voltage changes around 7.24mV . The is very low sensitive to the changes of the temperature.refV Figure 6 Temperature dependence ofbandgap output voltageThe power supply rejection ratio is shown in Fig. 6. From Fig. 6, the circuit of the BGR is robust to the power supply when thetemperature changes from 27℃ to 56℃. The exact PSRR and reference voltages for certain values are depicted in the Table 1.Temperature (℃) V oltage Variation 27℃ 376.707µV 55.6℃ 499.067µV 85℃1.25189mVTable 1 Outcomes of PSRR and reference voltage at certain temperature.4. ConclusionA design using bandgap core circuit with Op amp and start-up circuit is presented and simulated. The overall performance of the BGR circuit is summarized in the Table 2. The schematic layout is shown in Figure 7.Parameter Measured Supply voltagerange2.5V±10%Temperaturerange27℃ to 85℃.V REF 1.26079V~1.25365VPSRR >52dB Powerconsumption 0.5W Layout dimension68.06µ×84.62µTable 2 Summary of performanceFigure 7 Layout of BGRComparisons with other design are shown in table 3.Design 1 [3]Our DesignSupply V oltage1V 2.5VPSRR >40dB>60dBTemp. Variation 1.2mV~5.4mV (-20℃~50℃) 7mv 0.58%≅(27℃ to85℃) Table 3(a) Comparison between differentdesigns Design 1 [4] Our Design Supply V oltage 2V 2.5VTemp. Variation <0.1% (-30℃~125℃)7mv ≅0.58%(27℃ to 85℃)Power Consumption2.2mW 0.5mWTable 3(b) Comparison between different designs5. References[1] D. F. Hilbiber, “A new semiconductor voltage standard”, ISSCC Digest Technical Papers, vol. 7, pp. 32-33, 1964[2] David Jones, “Analog Integrated CircuitDesign”[3] K. Lasanen, V. Korkala, “Design of a 1-V low power CMOS bandgap reference based on resistive subdivision”, IEEE[4] T. L. Brooks and A. L. Westwick, “A low-power differential CMOS bandgap reference,” in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 248–249.[5] Behzad Razavi, “ Design of Analog CMOS Integrated Circuits”, McGRAW-Hill, 2000。
Teaching Materials of Analog Circuits - chp (7)
resistor biasing uses coupling and bypass capacitors
§6.1 Current Sources Circuits and its Application
on-chip applications. In general, these op-amps are
designed to drive other CMOS circuits, which form high capacitive loads.
§6.0 Preview
一、Characteristics Of Analog IC
used for discrete circuits,it is not suitable for integrated
circuits. Resistors require relatively large areas on an
IC compared to transistors; therefore, a resistor-intensive
§6.0 Preview
The 741 is an example of an all-bipolar general-
purpose op-amp.Even though this op-amp is considered
classic, it still provides a good case study in which we perform a detailed analysis to dertimine both the dc and the small signal characteristics of the circuit. All-CMOS Op-amps can be designed for special
bandgap
BandgapBandgap电路原理如下：V BE1=V T ln(I/(n*Is))V BE2=V T ln(I/Is)V R1=V BE1-V BE2=V T ln(n)I=V R1/R1=V T ln(n)/R1Vref=(R2/R1)V T ln(n)+V BE3选用一个一级运放，运放测试电路图如图所示。
bias电流设置为227nA，输入端输入电压分别为700mV、699mV，即V in=1mV。
仿真波形见下图。
V out=4.08V，即该运放的开环增益为4080倍。
？Bandgap电路原理图如下图所示对r2设置不同值仿真，当r2为460k时vref最稳定。
1、电容在图示位置放置一个100p的电容。
当电容断路时，当电源接通，电路即刻开始工作。
当电容接入时，电路在70s后开始正常工作。
为消除电容影响，设计了如图所示的启动电路，启动电路的构成为一个反相器接一个N管。
当电路未开始正常工作，Vref电压低，N管导通拉低D点电压，各管导通电路可以开始正常工作。
Vref电压升高，启动电路关断。
下图中图一是未加启动电路时的仿真波形，图二是加启动电路后的仿真波形，图三是未接电容时的仿真波形。
可见电容影响基本被消除。
2.电路功率测如图六处电流P=IU=(0.134+0.134+1.85+1.85+1.6+1.8)uA*5V=36.84uW4.管子宽长设置如图，下方蓝色曲线是宽1.1um、长550nm的管子，当电源从4变化到6时的电流曲线。
上方曲线是当宽分别取值2、3、4、11um时的电流曲线。
综合管子大小和电流平稳程度考虑，选择3/1.5um。
(电压值需提升到12V？疑问，暂未使用)。
bandgap仿真
Vout VS Vdd
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目前性能较好的几种电路
2007-4-27
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高阶温度补偿的带隙基准电路1
I NL
VBE1 VBE2 R3
VT R3
ln
IC1 A2 A1I C 2
VT R3
ln
NI PTAT I NL ICons tant
工艺：Bipolar
Reference: G.M.Meijer et. Al., “A New CurvatureCorrected Bandgap Reference,” IEEE Journal of Solid-State Circuits, vol.17, NO.6, PP. 1139-1143, DEC,1982.
VX VY
VY VX
VX VY
VY VZ
VZ VX
dVZ
M2
M3
VX
gM4,5,6
VY
Vout=VZ
AV
VZ Vdd
VZ VX
VX Vdd
1
VX VY
VY VX
VX VY
VY VZ
VZ VX
CC
Rs
gM1
rX
rY
Bias
三支路bias电路： 存在VX－VZ－VY－VX负反馈支路
gM4,5,6
dVZ
VZ Vdd
dVdd
VZ VX
dVX
VZ Vdd
VZ VX VX Vdd
VZ VX VY VX VY Vdd
VX VY VZ VY VX Vdd
dVdd
VX VY
VY VX
VY VZ
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VREF 1VBE 2 VBE
VREF VBE MVT
VDD
VBE
-1.5mV/oK
≈ 17.2
Vref V V BE M × T T T T
VBE
T
VREF VBE VT ln n
+
VT Generator
VT
+0.087mV/oK
Vref=VBE+MVT
Vref
VREF VBE VT ln 0 T T T
VBE VBE 4 m VT Eg q T T
M
T
T
VREF
VBE 负温度系数，近似线性 4 m VT VT 正温度系数，线性 q VBE 和 VT 的加权求和可获得低温 VG 0 (Si Bandgap) V (T ) 度系数的基准电压
CEST, SHENZHEN UNIVERSITY
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多路输出的基准电压电路
VDD
1 M1 : K M2 resistor ratio
VREF
KVREF / R1
M0 VGS0
VREF / R1 R5 R4 R3 R2
R2 R3 R4 R5 VO 4 K VREF R 1 R2 R3 R4 VO 3 K VREF R 1 R2 R3 VO 2 K R VREF 1 R2 VO1 K R VREF 1
I2
R2 N
I1 R1
负温度系数电压
负温度系数电压：
PN结二极管的正向电压，具有 负温度系数
VBE I VT ln C IS
I
VBE Q1 VDD
I S bT
4 m
Eg exp kT
Eg ≈ 1.12eV, Si的带隙能量
VBE VT I C VT I S ln T T I S I S T E I V V T ln C 4 m T g2 VT T IS T kT VBE 4 m VT Eg q T
Interface
系统中有多个基准（电压或电流）电路 每个基准电路的指标要求不同 （如精度、线性调整率、温度系数等） 不同模块采用不同的基准电路可有效避免干扰
CEST, SHENZHEN UNIVERSITY 3
基准电路的应用 （二）
Reference is everywhere
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Chapter 7 Bandgap Voltage Reference
基准电路的应用 带隙基准的概念与原理
带隙基准的电路实现
温度系数和线性调整率 带输出缓冲的基准电压电路 多路输出的基准电压电路 由基准电压构成的电流源 低于1-V电源电压的CMOS带隙基准电路 一个实际芯片中的带隙基准电路
2 4 I D 2
1
IREF
ISS
2 4 f I SS
M1
M2
CEST, SHENZHEN UNIVERSITY
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基准电路的应用 （一）
REF Power Management
Amp
ADC
DSP or Microsystem
DAC
Amp
REF
REF
Clocks & Timers
需满足开启条件： VTH 1 VTH 5 VTH 3 VDD 需满足关断条件：VDD VGS 3 VGS1 VTH 5
M5
I OUT
2 1 1 1 2 nCOX W L N RS K
2
IOUT：insensitive to VDD
CEST, SHENZHEN UNIVERSITY 6
M3
M4
VEB 2 VBE1 IR1
I C1 IC 2 IR1 VT ln V ln I T I S1 S2 I C 2 I S1 V I T ln R1 I C1 I S 2 =n
Eg
CEST, SHENZHEN UNIVERSITY
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与温度无关的基准 —— 带隙电压基准
VDD I VO1 VO2 R I R1 X R3 R2 Y _
+
A1
+ Vout _
A Q1 Q2
nA
Q1
A Q2
nA
VO1 VO 2 VBE1 VBE 2 RI
RI VBE1 VBE 2 VT ln n VO1 VO 2 VBE 2 VT ln n
关于电压基准电路的参考文献
CEST, SHENZHEN UNIVERSITY 1
基准电路: Why？
VDD M3 M4 Vout CL
Voltage reference
VBattery VREF
A
VDD
M1 Vin
M2
VDD ISS
Current reference
A0 Gm Rout g m1 rds 2 || rds 4 g m1 2 nCOX W L 1 1 I SS
与电源无关的偏置
VDD IREF R1 IOUT 1 : 1 VDD
M3 IOUT
M4
IREF K:1 M1
M1
M2
M2 RS
iREF
W L 2 vDD i i R1 1 g m1 OUT REF W L 1
VDD W L 2 R1 1 g m1 W L 1
VGS1 VGS 2 I D 2 RS
106 Tmax Tmin
ppm C
Bandgap TC 典型值: 25 – 100ppm/oC
CEST, SHENZHEN UNIVERSITY 12
温度系数（TC ）的仿真与计算
TC at VDD = 3.3V
TC
Vref (max) Vref (min) Vref
106 1.1761 1.1731 10 6 25.5ppm/ oC 1.1761 Tmax Tmin 100 0
CEST, SHENZHEN UNIVERSITY
13
线性调整率（Line Regulation ）的仿真与计算
Supply-voltage dependence at T = 27oC
VDD = 5 V VDD = 4 V VDD = 3.3 V
Tr = 27 OC
Line Regulation
VBE 750mV, T 300 o K时, VBE T 1.5mV o K
7
CEST, SHENZHEN UNIVERSITY
正温度系数电压
正温度系数电压：
不等电流密度下的双极晶体管，
I0 + VDD
I0
_
△VBE
VBE T
VBE VBE1 VBE 2 VT ln I0 I VT ln 0 I S1 IS 2
A
VO A VIN 1 A
RO
Ropen 1 g m Ropen
1 gm
Voltage-series feedback High output current to drive resistive load Low output resistance Isolation to reduce cross-talk through reference circuit
CEST, SHENZHEN UNIVERSITY
Vout VBE 2
lnn ≈ 17.2 n≈ e17.2 ≈ 29502926 !!!
VBE1 VBE 2 R2 R3 R3 VT ln n R2 R3 R3
VBE 2
R VBE 2 VT ln n 1 2 R3
CEST, SHENZHEN UNIVERSITY
IOUT：insensitive to VDD
5
启动问题
电路中存在两个工作点，其中一个 是IOUT=0 需增加启动电路保证电路正常工作
IOUT
K:1 M1 M2 RS 1 : 1 VDD
M3
M4
IREF
M5提供了从VDD经M3、M1到地的 电流通路
11
CEST, SHENZHEN UNIVERSITY
温度系数 —— 定义
VREF
Vref 0 T
Fairly a constant
Tmin
0o C
Tr =
27oC
Tmax T
温度系数（Temperature Coefficient）: TC
TC
Vref (max) Vref (min) Vref (max)
低于1-V 电源电压的 CMOS 带隙基准电路
VDD
M2
M1 M3 VREF I1 + I 2 I1 + I 2
R3 R2 VREF V ln N V T R EB 2 R 2 1
R1, R2 & R3 made of same material Good matching R1 and R2 for optimizing tempco
IS
Q1
Q2 nIS
I0 I0 VT ln VT ln IS nI S VT ln n kT ln n q
CEST, SHENZHEN UNIVERSITY
VT k 0.087 mV o K 0 T q