蓝牙射频前端跳频频综的几项关键技术英文

division ratio is AV +B. The FC block is used for com2 paring the reference frequency and the frequency of the VCO feedback signal to indicate PLL locked tim e. A pulse w ill appear when the PLL is locked.
F ig. 1 System block of the FH synthesizer
2 VCO D esign
It is a cross2coup led differential VCO w ith both PMOS and NMOS cross2coup led amp lifying units, which generate a negative resistance to compensate the loss of the LC tank[3, 4 ]. The LC tank consists of two rectangular sp iral inductors made of thick A lCu metal, two M IM capacitors, and two MOS varactors made of thin oxide MOS structure w ith a three group gate. The VCO buffer is also an important circuit in the design of the VCO and it is used for imp roving driving capacity and isolation between the LC tank and the load. In this design, a symmetrical PMOS and NMOS buffer is used, different from conventional architecture. The main ad2 vantage of this VCO architecture is that symm etrical waveform s and lower distortion can be obtained[5, 6 ].
Xu Yong1, 2 W ang Zhigong1 L i Zhiqun1 Zhang L i1 M in Rui2 Xu Guanghui1, 3
(1 Institute of RF2 & OE2ICs, Southeast University, Nanjing 210096, China) (2 Institute of Sciences, PLA University of Science and Technology, Nanjing 211101, China) (3 Institute of Communication Engineering, PLA University of Science and Technology, Nanjing 210007, China)
The D 2latch is made up of imp roved m aster/ slave FSCL D 2flip 2flop. D1 and D2 form the input port of the integrated “OR ”logic and VB is a bandgap reference 1 V voltage. The advantage of using comp lem entary cross2 coup le pairs M6 ,M7 and M8 , M9 , instead of one NMOS cross2coup le pair M6 , M7 , is to increase the sw ing of output signals (QP, QN ) under the condition that the
Key technologies of frequency2hopp ing frequency synthesizer for B luetooth RF front2end
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A schem atic of the VCO circuit is given in Fig. 2 and when operational frequency is 21453 GHz, a transi2 ent wave of the VCO is shown in Fig. 3 (a). The meas2 ured phase noise is - 114132 dBc /Hz at a frequency offset of 214 MHz as shown in Fig. 3 (b).
Abstract:A scheme of a frequency2hopp ing frequency2synthesizer app lied to a B luetooth ratio frequency (RF) front2end is p resented, and design of a voltage controlled oscillator (VCO) and dual2modulus p rescaler are focused on. It is fabricated in a 0118 μm m ixed2signal CMOS ( comp lementary metal2oxide2sem iconductor transistor)
F ig. 2 Schematic of the VCO circuit
F ig. 3 Tested s of VCO. (a) Transient waves; (b) Phase noise
3 DM P D esign
Another block operating on the high frequency band is the DMP in the total synthesizer. In this paper, a novel D2latch architecture integrated with “OR ”logic gate is p resented. The imp lemented circuit of the DM P is shown in Fig. 4 (a). Fig. 4 (b) shows the D2latch circuit schematic integrated with “OR”logic gate. It is verified that the D2latch can work 20% faster than a normal D 2 latch w ithout integrated logic gate[6 - 8 ].
p rocess. The power dissipation of VCO is low and a stable performance is gained. The measured phase noise of VCO at 214 GHz is less than - 114132 dBc /Hz. The structure of the DMP is op tim ized and a novel D2latch integrated with “OR”logic gate is used. The measured results show that the chip can work well under a 118 V power supp ly. The power dissipation of the core part in a dual modulus p rescaler is only 5176 mW. An RMS jitter of 2 p s is measured on the output signal at 11813 MHz. It is less than 0102% of the clock period. Key words: B luetooth; frequency hopp ing; frequency synthesizer; voltage controlled oscillator (VCO ) ; dual2
modulus p rescaler; p rogrammable divider
Generally, it contains a phase locked loop (PLL ) synthesizer, transm itting and receiving functions in a monolithic, integrated B luetooth ratio frequency (RF ) transceiver. The PLL is shared between the transm itter and the receiver, so it is a key section. Furthermore, the research and design of the PLL frequency synthesizer in the B luetooth system are relatively difficult for frequen2 cy hopp ing (FH ) one. The FH synthesizer is built w ith components such as a voltage controlled oscillator (VCO ) , dual2modulus p rescaler (DM P) , p rogrammable divider, phase2frequency detector (PFD ) , charge pump (CP) and frequency comparator (FC) , etc. This paper focuses on some vital blocks in the RF transceiver.