液晶驱动芯片BU9793
单相计量多功能芯片 ATT7053BU用户手册
4. 通信接口 ........................................................................................................................................................... 8 4.1. SPI接口 ............................................................................................................................................. 8
奇美2730寸液晶背光灯驱动及保护电路原理分析2
OZ960方框图
驱动板 处理器 存储器 投影镜头
光学
色轮 冷镜 光源
屏幕
OZ960关键脚位描述
2脚OVP（Over Voltage Protection）过压保护 该脚的取样信号是从变压器的输出送来的电压信 号，IC内部设置的极限电平是2V，当取样电压达到这 个极限电平时，IC内部OVP运放输出翻转，保护电路 起动，4个输出激励端停止输出激励脉冲，灯管熄灭， 同时，7脚也没有2.5V的基准电压输出，整个IC不工 作。
U11双电压比较器是用来对输出变压器 T1-T4电流取样信号的电压比较，⑴⑺脚两 个运放输出电平均连接到OZ960的9脚FB输 入，作为对输出变压器T1-T4电流的监测和 保护。
4、LM324（U15）四运算放大器
该IC主要用来对背光控制信号和亮度调 节PWM信号进行电平转换。
5、FDS8958A（U2-U9）双MOSFET
OZ960
输出插座
输出变压器
பைடு நூலகம்
双MOSFET
LM393
LM393
LM324
LM339
一、背光板IC介绍
1、OZ960（U15）背光控制
OZ960是O2Micro公司的一片专用于背 光控制的高效率DC-AC转换IC，具有很宽 的输入电压范围，其亮度控制可用一个模 拟的电压或低频的脉冲宽度调制（PWM） 信号控制。 OZ960采用20脚SSOP封装。
3脚ENA（Enable）点灯使能端 该脚是IC运行与否的使能端，或者说是 灯管点亮的控制端。临界电平设置于1.5V， 当该脚输入电平高于1.5V时，IC开始运行， 灯管点亮，当该脚输入电平低于1.5V时，IC 停止工作，灯管熄灭。 7脚REF（Reference）基准电压 该脚是由5脚电源端经内部稳压后输出的 一个2.5V基准电压，供IC内部和外部电路 工作，IC保护时该脚没有输出。
8COM液晶驱动bu97950fuv
LCD Segment DriversStandardSegment DriverBU97950FUV 280Segment(35SEG×8COM)●Features1) LCD driving port : 8 Common output, 35 Segment output2) Integrated RAM for display data (DDRAM) : 35 × 8bit (Max 280 Segment) 3) 2wire serial interface (SCL, SDA) 4) Integrated Oscillation circuit5) Integrated Power supply circuit for LCD driving 1/4 Bias 1/8 Duty Integrated Buffer AMP 6) No external components7) Low power consumption design8) Integrated Electrical volume register (EVR) function 9) Operation power supply: 2.5～5.5V10) Power supply for LCD driving: 2.5～5.5V●ApplicationsTelephone, FAX, Portable equipments (POS, ECR, PDA etc.),DSC, DVC, Car audio, Home electrical appliance, Meter equipment etc.●Absolute Maximum Ratings (VSS=0V)ParameterSymbol Ratings Unit RemarksPower Supply Voltage1 VDD -0.5 ~ +7.0 V Power supply Power Supply Voltage2 VLCD -0.5 ~ +7.0 V LCD drive voltageAllowable loss Pd 0.75 W When use more than Ta=25 ºC, subtract 7.5mW per degree. (Package only) Input voltage range VIN -0.5 ~ VDD+0.5 V Operational temperature rangeTopr -40 ~ +85 ºC Storage temperature rangeTstg-55 ~ +125ºC*1 This product is not designed against radioactive ray.●Recommend operating conditions (Ta=-40~85ºC, VSS=0V)LimitsParameter SymbolMIN TYPMAX Unit RemarksPower Supply Voltage1 VDD 2.5 - 5.5 V Power supplyPower Supply Voltage2 VLCD2.5-5.5VLCD drive voltageNo.10044EAY08●Electrical characteristicsDC Characteristics (VDD=2.5~5.5V, VLCD=2.5~5.5V, VSS=0V, Ta=-40~85 ºC, unless otherwise specified)LimitsParameter SymbolMIN TYP MAXUnit Conditions “H” level input voltage VIH 0.7VDD - VDD V SDA,SCL“L” level input voltage VIL VSS - 0.3VDD V SDA,SCL“H” level input current IIH - - 1 µA SDA,SCL“L” level input current IIL -1 - - µA SDA,SCLSEG RON - 3.5 - kΩLCD Driver onresistance COM RON - 3.5 - kΩIload=±10µA Standby current Ist - - 5 µA Display off, Oscillation offPower consumption 1 IDD - 2.5 15 µA VDD=3.3V, VLCD=5V, Ta=25 ºC Power save mode1, FR=80Hz 1/4 bias, Frame inversePower consumption 2 ILCD - 10 20 µA VDD=3.3V, VLCD=5V, Ta=25 ºC Power save mode1, FR=80Hz 1/4 bias, Frame inverseOscillation Characteristics (VDD=2.5~5.5V, VLCD=2.5~5.5V, VSS=0V, Ta=-40~85 ºC, unless otherwise specified)LimitsParameter SymbolMIN TYP MAXUnit ConditionsFrame frequency fCLK 56 80 104 Hz FR = 80Hz setting, VDD=3.3VMPU interface Characteristics (VDD=2.5~5.5V, VLCD=2.5~5.5V, VSS=0V, Ta=-40~85 ºC, unless otherwise specified)LimitsParameter SymbolMIN TYP MAXUnit ConditionsInput rise time tr - - 0.3 µsInput fall time tf - - 0.3 µsSCL cycle time tSCYC 2.5 - - µs“H” SCL pulse width tSHW 0.6 - - µs“L” SCL pulse width tSLW 1.3 - - µsSDA setup time tSDS 200 - - nsSDA hold time tSDH 0 - - nsBuss free time tBUF 1.3 - - µsSTART condition hold time tHD;STA 0.6 - - µsSTART condition setup time tSU;STA 0.6 - - µsSTOP condition setup time tSU;STO 0.6 - - µsFig.12-wire interface timing●Block Diagram ●Pin ArrangementFig.2 block diagram Fig.3 Pin arrangement●Terminal descriptionTerminal Terminal No.I/O FunctionSDA 48 I/O serial data input SCL 47 I serial data transfer clock VSS 3 I GND VDD 1 I Power supplyVLCD 2 I Power supply for LCD drivingSEG0-35 4-24 33-46 O SEGMENT output for LCD driving COM0-725-32OCOMMON output for LCD drivingSDA SCL S D AS C LS E G 21S E G 22S E G 23S E G 24S E G 25S E G 26S E G 27S E G 28S E G 29S E G 30S E G 31S E G 32S E G 33S E G 34C O M 0C O M 1C O M 2C O M 3C O M 4C O M 5C O M 6C O M 7V D DV L C DV S SS E G 20S E G 19S E G 18S E G 17S E G 16S E G 15S E G 14S E G 13S E G 12S E G 11S E G 10S E G 9S E G 8S E G 7S E G 6S E G 5S E G 4S E G 3S E G 2S E G 1S E G●Functional descriptions○Command /Data transfer methodThis device is controlled by 2wire serial signal (SDA, SCL).Fig.4 2wire serial Command/Data transfer FormatIt has to generate the condition such as START condition and STOP condition in 2wire serial interface transfer method.Fig.5 Interface protcolMethod of how to transfer command and data is shown as follows.1) Generate “START condition”. 2) Issue Slave address.3) Transfer command and display data.○AcknowledgeData format is 8bits and return Acknowledge after transfer 8bits data.When SCL 8th=’L’ after transfer 8bit data (Slave Address, Command, Display Data), output ’L’ and open SDA line. When SCL 9th=’L’, stop output function.(As Output format is NMOS-Open-Drain, can’t output ‘H’ level.)If no need Acknowledge function, please input ‘L’ level from SCL 8th=’L’ to SCL 9th=’L’.Fig.6 Acknowledge timingSTART condition STOP conditionSDA SCL Slave addressSTART condition STOPcondition○Command transfer methodIssue the Slave Address (“01111100” for Write Mode or “01111101” for Read Mode) after the “START condition” is generated. Command input follows after the Slave Address. The least significant bit (LSB) of the Slave Address determines if the operation to be done is Write or Read operation.The MSB (command or data judgment bit) defines if the succeeding byte is a command or data.When “command or data judgment bit”=‘1’, the next byte is a command.When “command or data judgment bit”=‘0’, the next byte is display data.Once it enters display data transfer condition, it cannot input any command.To input command again, please generate the “START condition” again.If “START condition” or “STOP condition” is inputted in the middle of command transmission, the command will be cancelled. If the Slave address is continuously inputted following “START condition”, it will be in command input condition. Please input “Slave Address” in the first data transmission after “START condition”.When Slave Address cannot be recognized in the first data transmission, Acknowledge does not return and the next transmission will be invalid. When data transmission is in invalid status and the “START condition” is transmitted again, it will return to valid status.＊Please observe MPU Interface characteristic that Input rise time and Setup, Hold time when transfer command and data（Refer to MPU Interface）.○Write display and transfer methodWrite mode happens when R/W bit = ‘0’This device has Display Data RAM (DDRAM) of 35×8=280bits.The relationship between data input and display data, DDRAM data and address are as follows.The 8-bit display data will be stored in the DDRAM. The address to be written is the address specified by Address Set command, and the address is automatically incremented after every 8-bits of data.Data can be continuously written in the DDRAM by transmitting Data continuously.0 1 2 3 4 5 6 7 ・・・・・・・・21h 22h0 a i COM01 b j COM12 c k COM23 d l COM3BIT4 e m COM45 f n COM56 g o COM67 h p COM7SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG33 SEG34DDRAM address○Read Command Register and Transfer MethodThe command registers can be read during read mode. The sequence for the command register read is shown below.The command register addresses are described in 6. Command Description (ADSET command). The following register settings can be read in this mode.Register D7 D6 D5 D4 D3 D2 D1 D0 AddressREG1 0P5 P4 P3 P2 P1 P023h REG2P7 P6 P5 P4 P3 P2 P1 P024hREG1: P5 = Software reset conditionP4 to P0 = EVR settingREG2: P7 to P6 = Frame Frequency (FR) setting P5 to P4 = Power Save Mode (SR) setting P3 = LCD drive waveform setting P2 = Display ON/OFF setting P1 =APON setting P0 = APOFF setting○ LCD Driver Bias CircuitThis device generates LCD driving voltage with on-chip Buffer AMP.And it can drive LCD at low power consumption.*Line and frame inversion can set in DISCTL command.Refer to the “LCD driving waveform” about each LCD driving waveform.○ Reset initialize conditionInitial condition after execute Software Reset is as follows.・Display is OFF.・DDRAM address is initialized (DDRAM Data is not initialized).Refer to Command Description about initialize value of register.●Command / Function ListDescription List of Command / FunctionCommand Function1 Address set (ADSET) DDRAM address setting (00h~22h)2 EVR set (EVRSET) EVR setting (0~31)3 Display Control (DISCTL) Frame Frequency, Power save mode setting4 IC operation set (ICSET) LCD drive mode, software reset, display on/off5 All pixel Control (APCTL) All pixel control during display ON●Detailed command descriptionD7 (MSB) is bit for command or data judgment.Refer to Command and data transfer method.C: 0: Next byte is RAM write data.1: Next byte is command.○Address set (ADSET)MSBD7 D6 D5 D4 D3 D2 D1 LSB D0C 0 P5 P4 P3 P2 P1 P0Address data is specified in P[5:0].The address range can be set as 000000～100010(bin).When the specified address is out of range, the address will be set to “000000”.The Reset initialize condition of the DDRAM address is “000000”Command Register Addresses (read mode):P[5:0] = 23h （100011b）- REG1Register address for Software reset condition and EVR setting P[5:0] = 24h （100100b）- REG2Register address for the other settings(Please refer to 1.5 Read Command Register and Transfer Method)○EVR Set (EVRSET)MSBD7 D6 D5 D4 D3 D2 D1 LSB D0C 1 0 P4 P3 P2 P1 P0It is able to control 32-step electrical volume register (EVR).It is able to set V0 voltage level (the max level voltage of LCD driving voltage). Electrical volume register (EVR) is set “00000” in reset initialize conditionIn “00000” condition, V0 voltage output VLCD voltage.It is prohibited to set EVR V0 voltage under 2.5V.○The relationship of electrical volume register (EVR) setting and V0 voltageEVR CalculationformulaVLCD= 5.500 VLCD= 5.000 VLCD= 4.000 VLCD= 3.500 VLCD= 3.000 VLCD= 2.500 [V]0 VLCD V0= 5.500 V0= 5.000 V0= 4.000 V0= 3.500 V0= 3.000 V0= 2.500 [V]1 0.967*VLCD V0= 5.323 V0= 4.839 V0= 3.871 V0= 3.387 V0= 2.903 V0= 2.419 [V]2 0.937*VLCD V0= 5.156 V0= 4.688 V0= 3.750 V0= 3.281 V0= 2.813 V0= 2.344 [V]3 0.909*VLCD V0= 5.000 V0= 4.545 V0= 3.636 V0= 3.182 V0= 2.727 V0= 2.273 [V]4 0.882*VLCD V0= 4.853 V0= 4.412 V0= 3.529 V0= 3.088 V0= 2.647 V0= 2.206 [V]5 0.857*VLCD V0= 4.714 V0= 4.286 V0= 3.429 V0= 3.000 V0= 2.571 V0= 2.143 [V]6 0.833*VLCD V0= 4.583 V0= 4.167 V0= 3.333 V0= 2.917 V0= 2.500 V0= 2.083 [V]7 0.810*VLCD V0= 4.459 V0= 4.054 V0= 3.243 V0= 2.838 V0= 2.432 V0= 2.027 [V]8 0.789*VLCD V0= 4.342 V0= 3.947 V0= 3.158 V0= 2.763 V0= 2.368 V0= 1.974 [V]9 0.769*VLCD V0= 4.231 V0= 3.846 V0= 3.077 V0= 2.692 V0= 2.308 V0= 1.923 [V]10 0.750*VLCD V0= 4.125 V0= 3.750 V0= 3.000 V0= 2.625 V0= 2.250 V0= 1.875 [V]11 0.731*VLCD V0= 4.024 V0= 3.659 V0= 2.927 V0= 2.561 V0= 2.195 V0= 1.829 [V]12 0.714*VLCD V0= 3.929 V0= 3.571 V0= 2.857 V0= 2.500 V0= 2.143 V0= 1.786 [V]13 0.697*VLCD V0= 3.837 V0= 3.488 V0= 2.791 V0= 2.442 V0= 2.093 V0= 1.744 [V]14 0.681*VLCD V0= 3.750 V0= 3.409 V0= 2.727 V0= 2.386 V0= 2.045 V0= 1.705 [V]15 0.666*VLCD V0= 3.667 V0= 3.333 V0= 2.667 V0= 2.333 V0= 2.000 V0= 1.667 [V]16 0.652*VLCD V0= 3.587 V0= 3.261 V0= 2.609 V0= 2.283 V0= 1.957 V0= 1.630 [V]17 0.638*VLCD V0= 3.511 V0= 3.191 V0= 2.553 V0= 2.234 V0= 1.915 V0= 1.596 [V]18 0.625*VLCD V0= 3.438 V0= 3.125 V0= 2.500 V0= 2.188 V0= 1.875 V0= 1.563 [V]19 0.612*VLCD V0= 3.367 V0= 3.061 V0= 2.449 V0= 2.143 V0= 1.837 V0= 1.531 [V]20 0.600*VLCD V0= 3.300 V0= 3.000 V0= 2.400 V0= 2.100 V0= 1.800 V0= 1.500 [V]21 0.588*VLCD V0= 3.235 V0= 2.941 V0= 2.353 V0= 2.059 V0= 1.765 V0= 1.471 [V]22 0.576*VLCD V0= 3.173 V0= 2.885 V0= 2.308 V0= 2.019 V0= 1.731 V0= 1.442 [V]23 0.566*VLCD V0= 3.113 V0= 2.830 V0= 2.264 V0= 1.981 V0= 1.698 V0= 1.415 [V]24 0.555*VLCD V0= 3.056 V0= 2.778 V0= 2.222 V0= 1.944 V0= 1.667 V0= 1.389 [V]25 0.545*VLCD V0= 3.000 V0= 2.727 V0= 2.182 V0= 1.909 V0= 1.636 V0= 1.364 [V]26 0.535*VLCD V0= 2.946 V0= 2.679 V0= 2.143 V0= 1.875 V0= 1.607 V0= 1.339 [V]27 0.526*VLCD V0= 2.895 V0= 2.632 V0= 2.105 V0= 1.842 V0= 1.579 V0= 1.316 [V]28 0.517*VLCD V0= 2.845 V0= 2.586 V0= 2.069 V0= 1.810 V0= 1.552 V0= 1.293 [V]29 0.508*VLCD V0= 2.797 V0= 2.542 V0= 2.034 V0= 1.780 V0= 1.525 V0= 1.271 [V]30 0.500*VLCD V0= 2.750 V0= 2.500 V0= 2.000 V0= 1.750 V0= 1.500 V0= 1.250 [V]31 0.491*VLCD V0= 2.705 V0= 2.459 V0= 1.967 V0= 1.721 V0= 1.475 V0= 1.230 [V]Prohibit setting*In case EVR using, please satisfy VLCD-V0 >0.6 V condition.If do not satisfy this condition, IC output will be unstable.*Do not use V0 < 2.5V area. If EVR set this area, IC operating will be unstable.○Display control (DISCTL)MSBD7 D6 D5 D4 D3 D2 D1 LSB D0C １１０P3 P2 P1 P0Set Power save mode FR.Power save mode FR P３P２Reset initialize conditionNormal mode (80Hz) 0 0 ○Power save mode1 (71Hz) 0 1Power save mode2 (64Hz) 1 0Power save mode3 (50Hz) 1 1＊Operation current decrease inNormal mode > Power save mode1 > Power save mode2 > Power save mode 3 order.Set Power save mode SR.Setup P1 P0 Reset initialize conditionPower save mode 1 0 0Power save mode 2 0 1Normal mode 1 0 ○High power mode 1 1＊Operation current increase in order ofPower save mode 1 < Power save mode 2 < Normal mode < High power mode order.Note:Power save mode FR / LCD drive waveform / Power save mode SR will affect the display image.Select the best value depending on the current consumption and display image using LCD panel (under real application).Mode Flicker Display grade/ContrastPower save mode FR ○ -LCD drive waveform (ICSET) ○ ○Power save mode SR - ○○Set IC Operation (ICSET)MSBD7 D6 D5 D4 D3 D2 D1 LSB D0C 1 1 1 0 P2 P1 P0Set LCD drive waveform.Setup P2 Reset initialize conditionLine inversion mode 0Frame inversion mode 1 ○Operation current: Line inversion > Frame inversionFor drive mode of Line inversion and Frame inversion, refer to LCD waveform..Set Software Reset condition.Setup P1 Reset initialize conditionNo operation 0 ○Software reset 1When “Software Reset” is executed, this device is reset to initial condition.(Refer to Reset initialize condition)Software reset is asserted only once when P1 is set.Other settings can be set after this.Set Display ON and OFFSetup P0 Reset initialize conditionDisplay OFF(DISPOFF) 0 ○Display ON(DISPON) 1Display OFF : The DDRAM content is not affected. All SEGMENT and COMMON output stop after a frame.Display OFF mode ends when Display ON is set.Display ON : SEGMENT and COMMON outputs are active.Start read operation to display data from the DDRAM.○All Pixel control (APCTL)MSBD7 D6 D5 D4 D3 D2 D1 LSB D0C 1 1 1 1 0 P1 P0All display set ONAPON P1 Reset initialize conditionNormal 0 ○All pixel ON 1All display set OFFAPOFF P0 Reset initialize conditionNormal 0 ○All pixel OFF 1All pixels ON : All pixels are ON regardless of DDRAM data.All pixels OFF : All pixels are OFF regardless of DDRAM data.Note:All pixels ON/OFF is effective only at the time of “Display ON” status.The contents of DDRAM do not change at this time.When P1 and P0=’1’, APOFF is selected. APOFF has higher priority than APON.●LCD driving waveform(1/4bias, 1/8duty)Line inversion modeFrame inversion mode●Initialize sequencePlease follow the sequence below after Power-On to set this device to initial condition. Power on↓STOP condition↓START condition↓Issue Slave address↓Execute Software Reset by ICSET commandEach register value and DDRAM address is initialized to their default values. DDRAM data is random after power on.●Start sequence○Start sequence example No. Input D7 D6 D5 D4 D3 D2 D1 D0 Descriptions1 Power onVDD=0→5[V] (Tr=0.1[ms])↓2 wait 100usInitialize IC↓3 Stop Stop condition↓4 StartStart condition 5 Slave address0 1 1 1 1 1 0 0 Issue slave address↓6 ICSET 1 1 1 1 0 * 1 * Software Reset↓7 DISCTL1 1 1 0 0 0 1 0 Unnecessary when initial value setup ↓ (If you need to change the condition) 8 EVRSET1 1 0 0 0 0 0 0 Unnecessary when initial value setup ↓ (If you need to change the condition)9 ADSET 0 0 0 0 0 0 0 0 RAM address set↓10 Display Data* * * * * * * * Address 00h………………Display Data* * * * * * * * Address 22h↓11 Stop Stop condition↓12 StartStart condition 13 Slave address0 1 1 1 1 1 0 0 Issue slave address↓14ICSET1111*1Display ON●Caution in P .O.R circuit useThis device has “P .O.R” (Power-On Reset) circuit and Software Reset function.Please keep the following recommended Power-On conditions in order to power up properly.Please set power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec below in order to ensure P .O.R operationRecommended condition of tR, tF, tOFF, Vbot (Ta=25 ºC)tR tF tOFF Vbot Less than 5ms Less than 5ms More than 20ms Less than 0.3VIf it is difficult to meet above conditions, execute the following sequence after Power-On.(1) STOP conditionSTOP conditionVDDSDASCLSTOP condition(2) After send STOP condition, execute Software Reset (ICSET) command.●I/O Equivalent CircuitFig.20 I/O Equivalent CircuitSDAVSSSCLVSSVLCDVSSVLCDSEG/COMVSSVDDVSS●Example of recommended circuitFig.21example of recommended circuit●Notes for use(1) Absolute Maximum RatingsAn excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.(2) Operating conditionsThese conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter.(3) Reverse connection of power supply connectorThe reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal.(4) Power supply lineDesign PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns.For the GND line, give consideration to design the patterns in a similar manner.Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal.At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant.(5) GND voltageMake setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.(6) Short circuit between terminals and erroneous mountingIn order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down.(7) Operation in strong electromagnetic fieldBe noted that using ICs in the strong electromagnetic field can malfunction them.(8) Inspection with set PCBOn the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB.(9) Input terminalsIn terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminalsa voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply avoltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics.(10) Ground wiring patternIf small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.(11) External capacitorIn order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.(12) No Connecting input terminalsIn terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.(13) Rush currentWhen power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.●Ordering part numberB U 9 7 9 5 0 FU V - E 2Part No.Part No.PackageFUV: TSSOP-C48VPackaging and formingE2: Embossed tape and reel (TSSOP-C48V)TSSOP-C48V。
长虹CH-16机芯(TDA9370、TDA9383、TDA9.
长虹CH-16机芯（TDA9370、TDA9383、TDA9373和OM8370、OM8373掩膜）彩电电路类型来源：本站整理作者：佚名2010-07-08 15:46:44一、控制功能部分控制系统相关电路由超级芯片UOC相关脚和内部相关电路组成，对外部电路的控制由相关脚输出，不过同芯片引脚功能会因软件及硬件电路的需要而改变，表1～表5汇总了长虹CH-16机芯采用TDA9370、TDA9383、TDA9373和OM8370、OM8373 OTP片重新掩膜后形成的多个不同型号的芯片在不同产品上应用时各脚功能及工作电压。
由表1～表5中统计的内容可知：表1 21英寸彩电应用OTP片IM8370PS/N3/A掩膜的CH05T1626新片特点[代表产品有PF2195(F23、SF2158(F23、PF2156(F23、PF2163(F23、PF2165(F23等]引脚符号引脚功能及维修提示电路特点1DEGAUSS开机输出消磁控制信号,二次开机便输出高电平去消磁控制电路接R202(4.7KΩ于5V上2SCL总线控制,控制存储器接R204(4.7KΩ于5V上AT24C16和调谐器TAF5-3SDACI41接R203(4.7KΩ于5V上5KEY1按键控制电路.外接防干扰二极VD221,VD220上接电阻R205(4.7KΩ于5V上6KEY2上接电阻R207(4.7KΩ于5V上7LED指示灯控制输出,通过VK01实现指示灯显示上接电阻R409(4.7KΩ于5V上54、55、61控制系统三路3.3V供电58、5912 MHz晶体62MUTE静音输出，控制V601伴音功放TDA517P⑧脚。
接上电阻R145B于⑧脚为低电平时处于静止状态。
⑧脚还受5V 上，R606接V601基极V402控制行推动管V401工作或停止63STANDBY开机待机控制，控制电源V803实现电源待或接R218A(4.7KΩ接在5V上开机；控制V402控制行推动管V401工作或停止64PEM遥控入38SANPLL/R171(3.9KΩ、C171(3900pF、C171A(330pFSIFAGC表5 TDA9373掩膜的芯片CH05T1611、1621与OM8373掩膜的芯片CH05T1611、CHT05T1621、CH05T1630、CH05T1636的引脚功能电压及维修提示引脚符号引脚功能及维修提示电路特点SF2511(F06(CH05T1621待机电压(V工作电压(V1 BAND1波段切换电平输出，控制接R139A(4.7KΩ于5V上4.964.97V(L段6 BAND2TDA-5B6-M，实现L/H/U波段切换接R143A(2.2KΩ于5V上0.094.322 SCL总线输出控制存储器和TDA9859音效处理接R132A(3.3KΩ于5V上4.962.923 SDA接R133A(3.3KΩ于5V上4.96 2.674 VT调谐输出1.92~2.44变2.15变5KEY/LE指示灯出及键控信0.030.D 号入31变7VOL2(ON/OFF重低音静音控制,经V605、V606功放TDA8943SF⑦脚.高电平时,静音.低电平时0.091.89送入功放⑦脚功放工作.⑦脚还受关机静音控制电路V890控制8VOL1(MUTE主伴音静音控制输出,经V608/主伴音功放TDA8944J⑩脚为高电平时静音、静2.470.06(无信号时2.45VV607送入TDA8944J⑩脚音信号来自关机静音电路V890和CPU9 地010 STB开机/待机控制接R141A于3.3V上,控制待机管V830.V830基极有0.6V电压时整机处于待机状态0.02(待11 DK/M伴音多制式控制输出控制声表面滤波器和38脚外接3.21V246/V24754、56、613.3V控制系统供电3.35812MHz晶体1.5759 1.6562 KAV1AV1/AV2视频信号切换控制电平控制HEF4053，实现AV1/AV2切换0.0163 KAV2 0.0164 遥控入 4.96（1）控制系统供电脚为54、56、61脚54脚：给图文解调控制单元及TV数字处理单元供电端；56脚：芯片数字电路供电端；61脚：控制系统数字电路供电端，在长虹彩电中，该脚上都接有抗干扰的LC滤波元件。
LED显示驱动芯片BN5279(A)及其串行接口应用
LED显示驱动芯片BN5279(A)及其串行接口应用
高美珍;洪家平
【期刊名称】《国外电子元器件》
【年(卷),期】2005(000)006
【摘要】BN5279(A)是贝能科技有限公司生产的集成LED显示驱动器,具有工作电压低、串行接口、带有64键的键盘矩阵控制等特点.文中介绍了该电路的主要特性及工作原理,给出了BN5279(A)与AT89C2052微处理器的连接电路及程序代码.【总页数】4页(P69-72)
【作者】高美珍;洪家平
【作者单位】湖北师范学院,计算机科学系,湖北,黄石,435002;湖北师范学院,计算机科学系,湖北,黄石,435002
【正文语种】中文
【中图分类】TP335
【相关文献】
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2.串行接口LED显示驱动器MC14489及其应用 [J], 王子梁;王维原
3.多种串行接口技术在LED大屏幕显示系统中的应用 [J], 任志斌;朱俊林
4.一种应用于AMOLED显示驱动芯片的伽马校正电路 [J], 宇跃峰;尹勇生;谢熙明;权磊;贾晨
5.聚积推出智能型省电模式的LED驱动芯片MBI5037为LED交通显示屏应用创造节能新境界 [J], 本刊编辑部
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LED显示屏单元板常用芯片参数说明方便客户维修维护【LED显示屏维修资料】
上海元国光电科技常用器件的介绍随着LED显示屏工程商越来越多，生意越做越火爆，显示屏的问题也水涨船高，通常最头疼的问题就是显示屏的主要组成部分：单元板，新手一般不知道LED单元板维修时从哪里下手，围绕这个问题，我们总结了一下常见的问题及排除，提起74HC595，我想大家都不陌生，595也就是单元板的模块或者灯珠的垂直驱动芯片，一般单元板出现垂直一组灯不亮或者常亮，基本上都是这个芯片出现了问题或者虚焊，我们再来介绍下4953，它的作用是模块或者灯珠的行驱动，当LED单元板出现水平一条或者两条灯不亮的现象，也就是4953这个芯片的问题，至于其它芯片的作用及介绍，如下所述：1．ＩＣ的管脚功能IC芯片分别：74HC245、74HC595、74HC138、74HC04、4953。
各IC管脚功能如下：A: 74HC245功能是放大及缓冲。
各引脚如图120 和1接电源(+5V)19脚和10脚接电源地(GND)当电源是以上接时：输入脚分别为2、3、4、5、6、7、8、9。
输出脚分别为11、12、13、14、15、16、17、18注：2脚输入时，18脚输出。
其它脚以此类推。
B：74HC138功能是8选1译码器，输出为8行。
控制行数据。
各引脚如图2第8脚GND，电源地。
第16脚VCC，电源正极第1-3脚A、B、C输入脚。
第4-6脚选通输入端，（一般第5脚为EN ）9-15脚和第7脚输出端。
C：74HC595功能是8位串入、并出移位寄存器。
控制列数据。
各引脚如图316脚和10脚接电源（+5V），13脚和8脚接电源地（GND）。
列信号输出脚：1、2、3、4、5、6、7、15。
第一列输出脚为7脚，以此类推。
另第八列输出脚为15脚。
数据信号输入脚（Din）为14，数据信号输出脚（Din）为9。
锁存信号脚（L）为12脚，移位信号脚为11脚。
D：74HC04功能是六带缓冲反相器，控制使零信号（EN）。
各引脚如下图15脚接电源（+5V），7脚电源地（GND）。
BA9741F笔记本电脑液晶显示器高压驱动芯片
引脚号引脚名称
引脚功能
1CT
外接振荡电容2RT
外接振荡电阻3NON1放大器正相输入端4INV1放大器反相输入端5FB1内部误差放大器输出端6
DT1死区（过压）保护端7
OUT1脉冲电压输出端8
GND 接地端9
VCC 电源供电端10
OUT2脉冲电压输出端11DT2死区（过压）保护端12
FB2内部误差放大器输出端13
INV2放大器反相输入14
NON2放大器正相输入15SCP
过流（短路）保护端16VREF 基准电压（2.5V）SSOP-A16
SOP16 ＢＡ９７４１Ｆ的内部电路框图
ＢＡ９７４１Ｆ的针脚封装图
ＢＡ９７４１Ｆ的各引脚功能
ＢＡ９７４１Ｆ是双通道输出的ＰＷＭ驱动调整芯片，其工作电压范围为３．６Ｖ－３５Ｖ。
三角振荡器
计时器锁存
误差放大器１误差放大器２比较器
比较器１
比较器２。
单相多功能电能计量芯片FAQ-ATT7053
修改内容 初始版本 正式版本 增加提高 Poffset 校准速率方法 增加如何通过 0.5mT 潜动验证 增加有效值寄存器更新迟滞说明 1,SPI 通讯强调了 CS 拉低时务必 保证 CLK 为低电平，应用在新版 5000：1 动态范围的 7053 上，设 计修改可保证更强的 EMC 特性。 2, 文 件 名 增 加 同 类 产 品 7059B,7059S。
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版权归钜泉光电科技（上海）有限公司所有
Rev1.2
单相多功能电能计量芯片 FAQ——ATT7053BU(370-CS-002)
目录
1. 外部晶振不需要增加 10Mohm 偏置电阻...............................................................................................3 2. 推荐的电压输入信号。（电流信号幅度根据实际情况而定）..............................................................3 3. ADC 通道采样的推荐..............................................................................................................................3 4. ATT7053BU 和 MCU 的 IO 口线连接 ....................................................................................................3 5. ATT7053BU 工作晶振的选择与应用以及晶振布线原则......................................................................4 6. ATT7053BU 在各种情况下的复位时间？..............................................................................................4 7. ATT7053BU 上电后多久会出脉冲？......................................................................................................4 8. 如果只使用 2 路 ADC，第二路电流通道怎样处理最好？ ..................................................................5 9. P-offset 和 RMS-offset 应用以及对视在功率的影响 .............................................................................5 10. 如何使用第二路电流通道设计防窃电功能 ........................................................................................... 5 11. ATT7053BU 适用的计量交流电频率范围是多少..................................................................................6 12. SPI 通讯设计 ............................................................................................................................................6 13. 能否选用第二路电流通道作为首选计量通道........................................................................................ 8 14. 功率及有效值(RMS) 折计算公式 .......................................................................................................... 8 15. 考虑到 P-offset 和使用第二路电流通道的校表流程 .............................................................................9 16. 精度重复校验公式 ................................................................................................................................... 9 17. P_offset 采用功率法校验的换算公式 .................................................................................................. 11 18. AUTODC 可以长期打开吗？................................................................................................................ 11 19. 7053BU 无功相位补偿校正...................................................................................................................12 20. 如何通过射频辐射抗扰度试验？ ......................................................................................................... 12 21. 如何解决脉冲群试验中 IRMS 不为零的现象？..................................................................................12 22. ATT7053BU 怎样做直流表 ...................................................................................................................13 23. ATT7053BU 的电源电压抑制比特性....................................................................................................13 24. ATT7053BU 如何提高校准 Poffset 的速率 ..........................................................................................13 25. 如何通过 0.5mT 潜动验证.....................................................................................................................13 26. 有效值寄存器更新迟滞 ......................................................................................................................... 14