VHDL实例(latest)
3 微分电路
提取脉冲前沿
Q1
Q2
仿真结果
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY weifen2 IS PORT( A,clk:IN STD_LOGIC; Qout:OUT STD_LOGIC ); END weifen2;
练习
设计一个可逆BCD码计数器BICOUNTER， 输入为CLK，BIR，输出为Q[3..0]。当BIR=‘1’时， 计数器进行加计数；当BIR=‘0’时，计数器进行减 计数。
VHDL程序如下：
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BICOUNTER IS PORT( clk,BIR:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END BICOUNTER;
ARCHITECTURE a OF weifen2 IS SIGNAL Q1,Q2:STD_LOGIC; BEGIN PROCESS(clk) BEGIN IF clk'event AND clk='1' THEN Q1<=A; Q2<=Q1; END IF; END PROCESS; Qout<=Q1 and NOT Q2; END a;
VHDL应用实例
1. 序列信号发生器
在数字信号的传输和数字系统的测试中，有时需要用到一组特定的串 行数字信号，产生序列信号的电路称为序列信号发生器。 “01111110”序列发生器 该电路可由计数器与数据选择器构成，其VHDL描述如下： LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； USE IEEE.STD_LOGIC_ARITH.ALL； USE IEEE.STD_LOGIC_UNSIGNED.ALL；
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY debounce IS PORT( D_IN,clk:IN STD_LOGIC; D_OUT:OUT STD_LOGIC ); END debounce; ARCHITECTURE behave OF debounce IS COMPONENT RSCFQ PORT(R,S,CLK:IN STD_LOGIC; Q,QB:BUFFER STD_LOGIC); END COMPONENT RSCFQ; SIGNAL D0,D1,S,R:STD_LOGIC; BEGIN
PROCESS(COUNT) BEGIN CASE COUNT IS WHEN "000"=>Z<=‘0’； WHEN "001"=>Z<=‘1’； WHEN "010"=>Z<=‘1’； WHEN "011"=>Z<=‘1’； WHEN "100"=>Z<=‘1’； WHEN "101"=>Z<=‘1’； WHEN "110"=>Z<=‘1’； WHEN OTHERS=>Z<=‘0’； END CASE； END PROCESS；
WHEN S5=> IF DATAIN=‘1’THEN PRESENT_STATE：=S6； ELSE PRESENT_STATE：=S1； END IF； WHEN S6=> IF DATAIN=‘1’THEN PRESENT_STATE：=S7； ELSE PRESENT_STATE：=S1； END IF； WHEN S7=> IF DATAIN=‘0’THEN PRESENT_STATE：=S8；Q<=‘1’； ELSE PRESENT_STATE：=S0；END IF； WHEN S8=> IF DATAIN=‘0’THEN PRESENT_STATE：=S1； ELSE PRESENT_STATE：=S2； END IF； END CASE； WAIT UNTIL CLK’EVENT AND CLK=‘1’； END PROCESS； END ART；
DFF D_ IN D PRN D0 Q
D
PRN D1 Q
S
S
Q
D_ OUT
CLRN 11 CLK 10
CLRN 8
R
弹跳消除电路的内部实现原理图
此处RS触发器的前端连接与门和非门的处理原则是： (1) 因为一般人的按键速度至多是10次/秒，亦即一次按键时间是100 ms ， 所 以 按 下 的 时 间 可 估 算 为 50ms 。 以 取 样 信 号 CLK 的 周 期 为 8ms(125Hz)计，则可以取样到6次。 (2) 对于不稳定的噪声，在4ms以下则至多抽样一次。 (3) 在触发器之前，接上AND-NOT之后，SR的组态如表所示。
ARCHITECTURE a OF BICOUNTER IS SIGNAL Q_B:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk) BEGIN IF clk'event AND clk='1' THEN IF BIR='1' THEN IF Q_B="1001" THEN Q_B<="0000"; ELSE Q_B<=Q_B+1; END IF; ELSE IF Q_B="0000" THEN Q_B<="1001"; ELSE Q_B<=Q_B-1; END IF; END IF; END IF; END PROCESS; Q<=Q_B; END a;
PROCESS(CLOCK，Z) BEGIN --消除毛刺的锁存器 IF(CLOCK'EVENT AND CLOCK=‘1’)THEN ZO<=Z； END IF； END PROCESS； END ART；
2. 序列信号检测器
一个“01111110”序列信号检测器的VHDL描述 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； ENTITY DETECT IS PORT( DATAIN：IN STD_LOGIC； CLK：IN STD_LOGIC； Q：OUT STD_LOGIC)； END DETECT； ARCHITECTURE ART OF DETECT IS TYPE STATETYPE IS(S0，S1，S2，S3，S4，S5，S6，S7，S8)； BEGIN PROCESS(CLK) VARIABLE PRESENT_STATE：STATETYPE； BEGIN Q<=‘0’；
按键信号
抽样信号
抽样结果
弹跳现象产生错误的抽样结果
弹跳消除电路的实现原理如图所示，先将键盘的输入信号D_IN做为电路的 输入信号，CLK是电路的时钟脉冲信号，也就是取样信号，D_IN经过两级D触发 器延时后再使用RS触发器处理。
VCC 13
AND2 DFF 6 NOT AND2 9 NOT R 7 Q
ENTITY SENQGEN IS PORT(CLK，CLR，CLOCK：IN STD_LOGIC； ZO：OUT STD_LOGIC)； END SENQGEN；
ARCHITECTURE ART OF SENQGEN IS SIGNAL COUNT：STD_LOGIC_VECTOR(2 DOWNTO 0)； SIGNAL Z：STD_LOGIC :=‘0’； BEGIN PROCESS(CLK,CLR) BEGIN IF(CLR=‘1’)THEN COUNT<="000"； ELSE IF(CLK=‘1’AND CLK'EVENT)THEN IF(COUNT="111")THEN COUNT<="000"； ELSE COUNT<=COUNT +‘1’； END IF； END IF； END IF； END PROCESS；
PROCESS(CLK,R,S,Q_S,QB_S) BEGIN LIBRARY IEEE; IF (CLK'EVENT AND CLK='1')THEN USE IEEE.STD_LOGIC_1164.ALL; IF(S='1' AND R='0') THEN Q_S<='0'; ENTITY RSCFQ IS QB_S<='1'; PORT(R,S,CLK:IN STD_LOGIC; ELSIF (S='0'AND R='1') THEN Q,QB:BUFFER STD_LOGIC); Q_S<='1'; END RSCFQ; QB_S<='0'; ELSIF (S='0'AND R='0') THEN Q_S<=Q_S; ARCHITECTURE ART OF RSCFQ IS QB_S<=QB_S; SIGNAL Q_S,QB_S:STD_LOGIC; ELSE BEGIN NULL; END IF; END IF ; Q<=Q_S; QB<=QB_S; END PROCESS; END ART;
PROCESS(clk) BEGIN IF clk'event AND clk='1' THEN D0<=D_IN; D1<=D0; END IF; END PROCESS; S<=D0 AND D1; R<=(NOT D0) AND (NOT D1); u1:RSCFQ PORT MAP (R,S,CLK,QB=>D_OUT); END behave;
一个老外写的DDS(VHDL)的例子,很经典。
典。
-- DDFS.vhd--------------------------------------- Direct Digital Freq. Synthesis ----------------------------------------- (c) Bert Cuzeau, ALSE - info@-- May be reproduced provided that copyright above remains.-- We use one of the symetries in the sine function,-- so the lookup table is re-used twice (128 entries table)-- The Sine Table is built by a C program...--------------------------------------- Design IOs :-- Clk : Global Clock input-- Rst : Global Reset input-- Freq_data : 8-bit frequency control vector-- from DIP switches on the board.-- Dout : is signed 8-bit output to the DAC.-- -----------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;-- -----------------------------------------------Entity DDFS is-- -----------------------------------------------Port ( CLK : in std_logic;RST : in std_logic;Freq_Data : in std_logic_vector (7 downto 0);Dout : out std_logic_vector (7 downto 0));end DDFS;-- -----------------------------------------------Architecture RTL of DDFS is-- -----------------------------------------------signal Address : unsigned (6 downto 0);signal Result : std_logic_vector (7 downto 0);signal Accum : unsigned (28 downto 0); -- we want very low Frequencies ! signal Sign : std_logic;begin-- Signed Accumulator-- ------------------Acc: process (CLK,RST)beginif RST='1' thenAccum '0');elsif rising_edge(CLK) thenAccum <= Accum + unsigned(Freq_Data);end if;END process acc;Sign <= Accum(Accum'high); -- MSB-- Lookup Table Index calculation-- ------------------------------Address <= unsigned(Accum(Accum'high-1 downto Accum'high-Address'length)); -- SINE Look-Up TABLE-- --------------------- Inference of an Asynchronous Rom.-- A synchronous one would be better, but we register the output.-- This table has been built by GENVEC.exe (C program)-- We use only positive values ! (sign comes from quadrant info)-- This could be further optimized by coding only one quadrant...lookup: process (Address)subtype SLV8 is std_logic_vector (7 downto 0);type Rom128x8 is array (0 to 127) of SLV8; -- 0 to 2**Address'length - 1 constant Sinus_Rom : Rom128x8 := (x"00", x"03", x"06", x"09", x"0c", x"0f", x"12", x"15",x"18", x"1b", x"1e", x"21", x"24", x"27", x"2a", x"2d",x"30", x"33", x"36", x"39", x"3b", x"3e", x"41", x"43",x"46", x"49", x"4b", x"4e", x"50", x"52", x"55", x"57",x"59", x"5b", x"5e", x"60", x"62", x"64", x"66", x"67",x"69", x"6b", x"6c", x"6e", x"70", x"71", x"72", x"74",x"75", x"76", x"77", x"78", x"79", x"7a", x"7b", x"7b",x"7c", x"7d", x"7d", x"7e", x"7e", x"7e", x"7e", x"7e",x"7f", x"7e", x"7e", x"7e", x"7e", x"7e", x"7d", x"7d",x"7c", x"7b", x"7b", x"7a", x"79", x"78", x"77", x"76",x"75", x"74", x"72", x"71", x"70", x"6e", x"6c", x"6b",x"69", x"67", x"66", x"64", x"62", x"60", x"5e", x"5b",x"59", x"57", x"55", x"52", x"50", x"4e", x"4b", x"49",x"46", x"43", x"41", x"3e", x"3b", x"39", x"36", x"33",x"30", x"2d", x"2a", x"27", x"24", x"21", x"1e", x"1b",x"18", x"15", x"12", x"0f", x"0c", x"09", x"06", x"03" );beginResult '0');elsif rising_edge(CLK) thenif Sign='1' thenDout <= Result;elseDout <= std_logic_vector (- signed(Result));end if;end if;。
VHDL语言实例
VHDL语言实例例1：设计一七段显示译码器，用它来驱动七段发光管LED显示十六进制数字0到9和字母A到F。
LED显示数码管为共阳极。
LIBRARYieee;USE ieee.std_logic_1164.all;ENTITY HEX2LEDISPORT(HEX :IN std_logic_vector(3 DOWNTO0);LED : OUT std_logic_vector(6 TO0));ENDHEX2LED; 图例1 七段显示译码器实体ARCHITECTURE HEX2LED_arc OF HEX2LED IS BEGIN-- HEX-TO-SEVEN-SEGMENT DECODER-- SEGMENT ENCODING---------- 5 ||1-- ---- <--6-- 4 ||2--------3WITH HEX SELECTLED<= "1111001" when "0001","0100100" when "0010","0110000" when "0011","0011001" when "0100","0010010" when "0101","0000010" when "0110","1111000" when "0111","0000000" when "1000","0010000" when "1001","0001000" when "1010","0000011" when "1011","1000110" when "1100","0100001" when "1101","0000110" when "1110","0001110" when "1111","1000000" when others;END HEX2LED_arc;例2：设计一个八选一数据选择器1）s是通道选择信号, d0,d1,d2,d3,d4,d5,d6,d7数据输入 out1是数据输出ENTITY sels ISPORT(d0,d1,d2,d3,d4,d5,d6,d7:INBIT;s :INTEGER RANGE0 TO 7;out1 :OUT BIT);END sels;图例2（a) 八选一数据选择器实体ARCHITECTURE sels_arc OF sels ISBEGINWITH s SELECTout1 <= d0 WHEN 0,d1 WHEN 1,d2 WHEN 2,d3 WHEN 3,d4 WHEN 4,d5 WHEN 5,d6 WHEN 6,d7 WHEN 7;END sels_arc;2)A,B,C是通道选择信号, I0,I1,I2,I3,I4,I5,I6,I7数据输入 Q是数据输出LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(I0,I1,I2,I3,I4,I5,I6,I7,A,B,C:INstd_logic;Q :OUT std_logic);END mux8;图例2（b) 八选一数据选择器实体SIGNAL sel :INTEGER ；BEGINQ <= I0 AFTER 10 ns WHEN sel= 0 ELSEI1 AFTER 10 ns WHEN sel= 1 ELSEI2 AFTER 10 ns WHEN sel= 2 ELSEI3 AFTER 10 ns WHEN sel= 3 ELSEI4 AFTER 10 ns WHEN sel= 4 ELSEI5 AFTER 10 ns WHEN sel= 5 ELSEI6 AFTER 10 ns WHEN sel= 6 ELSEI7 AFTER 10 ns ;sel <= 0 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘0’ ELSE1 WHEN A= ‘1’ AND B= ‘0’ AND C= ‘0’ ELSE2 WHEN A= ‘0’ AND B= ‘1’ AND C= ‘0’ ELSE3 WHEN A= ‘1’ AND B= ‘1’ AND C= ‘0’ ELSE4 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘1’ EL SE5 WHEN A= ‘1’ AND B= ‘0’ AND C= ‘1’ ELSE6 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘1’ ELSE7;END mux8_arc;例3：设计一D触发器d是输入端，clk是时钟信号控制端，q是触发器的输出端。
VHDL Examples VHDL语言编程相关案例
ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ; STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;
VHDL code for a 16-bit adder
VHDL code for a full-adder
LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( X, Y S END adder16 ;
: IN : OUT
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;
VHDL数字逻辑电路设计19例
VHDL 数字逻辑电路设计19例第1章组合逻辑电路8例1. 2-4译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq24 ISPORT (EN,A,B:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(3 downto 0 ));END ENTITY ymq24 ;ARCHITECTURE rt1 OF ymq24 ISSIGNAL T:STD_LOGIC_vector(1 downto 0 );BEGINT<=A & B;process(EN,T)beginIF EN='1' THEN YN<="1111";ELSIF T="00" THEN YN<="1110";ELSIF T="01" THEN YN<="1101";ELSIF T="10" THEN YN<="1011";ELSE YN<="0111";END IF;End process;END ARCHITECTURE rt1;2. 3-8译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq38 ISPORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END ENTITY ymq38 ;ARCHITECTURE rt1 OF ymq38 ISSIGNAL T1,T2:STD_LOGIC_vector(2 downto 0 );BEGINT1<=A & B & C;T2<=G1 & G2N & G3N;process(G1,G2N,G3N,T1,T2)beginIF T2/="100" THEN YN<="11111111";ELSIF T1="000" THEN YN<="11111110";ELSIF T1="001" THEN YN<="11111101";ELSIF T1="010" THEN YN<="11111011";ELSIF T1="011" THEN YN<="11110111";ELSIF T1="100" THEN YN<="11101111";ELSIF T1="101" THEN YN<="11011111";ELSIF T1="110" THEN YN<="10111111";ELSE YN<="01111111";END IF;End process;END ARCHITECTURE rt1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq41 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq41;ARCHITECTURE rt1 OF xzq41 ISsignal s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS<= a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "00"=> Y<=d(0);WHEN "01"=> Y<=d(1);WHEN "10"=> Y<=d(2);WHEN "11"=> Y<=d(3);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq81 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq81;ARCHITECTURE rt1 OF xzq81 ISsignal s: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINS<= a2 & a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "000"=> Y<=d(0);WHEN "001"=> Y<=d(1);WHEN "010"=> Y<=d(2);WHEN "011"=> Y<=d(3);WHEN "100"=> Y<=d(4);WHEN "101"=> Y<=d(5);WHEN "110"=> Y<=d(6);WHEN "111"=> Y<=d(7);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l75 ISPORT (A,B,C:IN STD_LOGIC;d,g : OUT STD_LOGIC);END ENTITY l75 ;ARCHITECTURE rt1 OF l75 ISCOMPONENT ymq38PORT (G1, G2N, G3N, A, B, C: IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END COMPONENT ;signal ynt : STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1','0','0',a,b,c,YNt(7 DOWNTO 0));d<=not(ynt(1) and ynt(2) and ynt(4) and ynt(7));g<=not(ynt(1) and ynt(2) and ynt(3) and ynt(7));END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l76 ISPORT (A,B,C,D:IN STD_LOGIC;F : OUT STD_LOGIC);END ENTITY l76 ;ARCHITECTURE rt1 OF l76 ISCOMPONENT ymq38PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 ));END COMPONENT ;signal yn1t:STD_LOGIC_vector(7 downto 0 );signal yn2t:STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1',A,'0',B,C,D,YN1t(7 DOWNTO 0));U2 :ymq38 PORT MAP (A,'0','0',B,C,D,YN2t(7 DOWNTO 0));F<=not( yn1t(2) and yn1t(4) and yn1t(6) and yn2t(0) and yn2t(2) and yn2t(4) and yn2t(6)); END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq81PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;BEGINU1 :xzq81 PORT MAP ('0',"01101100",c,b,a,f);END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq41PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;signal t:STD_LOGIC;signal dt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINt<= not c;dt<=t & c & '1' & '0';U1 :xzq41 PORT MAP ('0',dt,b,a,f);【作业】以下所有题目必须用VHDL代码实现。
vhdl语言编程实例
实现各种逻辑功能：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY louji1a ISPORT(S: IN STD_LOGIC_VECTOR(2 DOWNTO 0);C: IN STD_LOGIC;A: IN STD_LOGIC_VECTOR(4 DOWNTO 0);B: IN STD_LOGIC_VECTOR(4 DOWNTO 0);F: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );END ENTITY louji1a;ARCHITECTURE ONE OF louji1a ISBEGINF<=A WHEN S="000" ELSEA-B WHEN S="001" ELSEA-1 WHEN (S="010" AND C='0') ELSEA+1 WHEN (S="011" AND C='0') ELSEA ANDB WHEN S="100" ELSEA ORB WHEN S="101" ELSEA XORB WHEN S="110" ELSENOT A WHEN S="111" ELSENULL;END ARCHITECTURE ONE;38译码器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY yimaqi1a ISPORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);B: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );END ENTITY yimaqi1a;ARCHITECTURE one OF yimaqi1a IS--SIGNAL abc:STD_LOGIC_VECTOR(3 DOWNTO 0); --SIGNAL def:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN--abc<=A3&A2&A1&A0;--def<=g&f&e&d&c&b&a;PROCESS (A)case A ISWHEN"0000"=>B<="0111111";WHEN"0001"=>B<="0000110";WHEN"0010"=>B<="1011011";WHEN"0011"=>B<="1001111";WHEN"0100"=>B<="1100110";WHEN"0101"=>B<="1101101";WHEN"0110"=>B<="1111101";WHEN"0111"=>B<="0000111";WHEN"1000"=>B<="1111111";WHEN"1001"=>B<="1101111";WHEN"1010"=>B<="1110111";WHEN"1011"=>B<="1111100";WHEN"1100"=>B<="0111001";WHEN"1101"=>B<="1011110";WHEN"1110"=>B<="1111001";WHEN"1111"=>B<="1110001";WHEN OTHERS =>NULL;END CASE ;END PROCESS;END ARCHITECTURE ONE;十进制计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY jishuqi1a ISPORT(CLK,EN,CTRL,CLR:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CO:OUT STD_LOGIC);END ENTITY jishuqi1a;ARCHITECTURE BHV OF jishuqi1a ISSIGNAL QQ :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,EN,CTRL,CLR)--V ARIABLE QQ :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLR='0' THEN QQ<="0000";ELSIF CTRL='0' THEN QQ<="0000";ELSIF CLK'EVENT AND CLK='1'THEN IF EN='1' THEN IF QQ<9 THEN QQ<=QQ+1;ELSE QQ<="0000";END IF;END IF;IF QQ="0000" THEN CO<='1';ELSE CO<='0';END IF;END PROCESS ;Q<=QQ;END ARCHITECTURE BHV;实现六十进制计数器：1.实现任何计数器:2.library ieee;use ieee.std_logic_1164.all;--use ieee.std_logic_unsigned.all;entity ncount isgeneric(n: integer :=6);port(clk : in std_logic;clr : in std_logic;--updown : in std_logic;en : in std_logic;ctrl : in std_logic;d : in INTEGER range n-1 downto 0;q : out INTEGER RANGE n-1 DOWNTO 0;C : OUT STD_LOGIC);end entity;architecture rtl of ncount is-- Declare the shift register signalsignal qq : INTEGER RANGE n-1 DOWNTO 0;beginprocess (clk,en,ctrl,clr,qq)beginif (clr = '0') then qq <= 0;elsif (rising_edge(clk)) thenif (en = '1') thenif (ctrl = '1') then qq <= d;--elsif (updown = '1') thenelse if ( qq < n-1 ) thenqq <= qq+1;elseqq <= 0;end if;--elsif ( qq > 0 ) then-- qq <= qq-1;-- else-- qq <= n-1;end if;end if;end if;if ( qq = 0 ) thenc<='1';elsec<='0';end if;q<=qq;end process;end rtl;六进制：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity sixcount is(n: integer :=3);port(clk : in std_logic;clr : in std_logic;en : in std_logic;ctrl : in std_logic;d : in std_logic_vector (n-1 downto 0);q : out std_logic_vector (n-1 downto 0);C : OUT STD_LOGIC);end entity;architecture rtl of sixcount is-- Declare the shift register signalsignal qq : std_logic_vector (n-1 downto 0);beginprocess (clk,en,ctrl,clr,qq)beginif (clr = '0') then qq <= "000";elsif (rising_edge(clk)) thenif (en = '1') thenif (ctrl = '1') then qq <= d;--elsif (updown = '1') thenelse if ( qq < "101" ) thenqq <= qq+1;elseqq <= "000";end if;--elsif ( qq > 0 ) then-- qq <= qq-1;-- else-- qq <= n-1;end if;end if;if ( qq = "000" ) thenc<='1';elsec<='0';end if;q<=qq;end process;end rtl;十进制：generic(n: integer :=4);port(clk : in std_logic;clr : in std_logic;--updown : in std_logic;en : in std_logic;ctrl : in std_logic;d : in std_logic_vector (n-1 downto 0);q : out std_logic_vector (n-1 downto 0);C : OUT STD_LOGIC);end entity;architecture rtl of tencount is-- Declare the shift register signalsignal qq : std_logic_vector (n-1 downto 0);beginprocess (clk,en,ctrl,clr,qq)beginif (clr = '0') then qq <="0000";elsif (rising_edge(clk)) thenif (en = '1') thenif (ctrl = '1') then qq <= d;--elsif (updown = '1') thenelse if ( qq < "1001" ) thenqq <= qq+1;elseqq <= "0000";end if;--elsif ( qq > 0 ) then-- qq <= qq-1;-- else-- qq <= n-1;end if;end if;end if;if ( qq = "0000" ) thenc<='1';elsec<='0';end if;q<=qq;end process;end rtl;还需用译码器：library ieee ;use IEEE.STD_LOGIC_1164.ALL;ENTITY TRANS ISPORT(A3,A2,A1,A0 :IN STD_LOGIC;--A,B,C,D,E,F,G:OUT STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );END ENTITY TRANS ;ARCHITECTURE A OF TRANS ISSIGNAL AA:STD_LOGIC_VECTOR(3 DOWNTO 0); --SIGNAL Q:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGINAA <= A3&A2&A1&A0;--Q <= G&F&E&D&C&B&A;PROCESS(AA)BEGINCASE AA ISWHEN "0000" => Q<="0111111";WHEN "0001" => Q<="0000110";WHEN "0010" => Q<="1011011";WHEN "0011" => Q<="1001111";WHEN "0100" => Q<="1100110";WHEN "0101" => Q<="1101101";WHEN "0110" => Q<="1111101";WHEN "0111" => Q<="0000111";WHEN "1000" => Q<="1111111";WHEN "1001" => Q<="1101111";WHEN "1010" => Q<="1110111";WHEN "1011" => Q<="1111100";WHEN "1100" => Q<="0111001";WHEN "1101" => Q<="1011110";WHEN "1110" => Q<="1111001";WHEN "1111" => Q<="1110001";WHEN OTHERS => NULL;END CASE;END PROCESS;END ARCHITECTURE A ;将十进制，六进制组成六十进制：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity stencount is(clk1 : in std_logic;clr1 : in std_logic;--updown1 : in std_logic;en1 : in std_logic;ctrl1 : in std_logic;--ctrl2 : in std_logic;dd1 : in INTEGER RANGE 9 DOWNTO 0;dd2 : in INTEGER RANGE 5 DOWNTO 0;q1 : out INTEGER RANGE 59 DOWNTO 0;C1 : OUT STD_LOGIC);end entity;architecture rtl of stencount iscomponent ncountgeneric(n: integer);port(clk : in std_logic;clr : in std_logic;-- updown : in std_logic;en : in std_logic;ctrl : in std_logic;d : in INTEGER range n-1 downto 0;q : out INTEGER RANGE n-1 DOWNTO 0;c : OUT STD_LOGIC);end component;-- Declare the shift register signalsignal aa : std_logic;signal qq1 : INTEGER RANGE 9 DOWNTO 0;signal qq2 : INTEGER RANGE 5 DOWNTO 0;signal cctrl1,cctrl2 : std_logic;begincctrl2<=ctrl1;--qq1<=q1(3)&q1(2)&q1(1)&q1(0);--qq2<=q1(6)&q1(5)&q1(4);U1 :ncount GENERIC MAP(n=>10)PORT MAP( clk=>clk1,en=>en1 ,c=>aa,ctrl =>cctrl1,clr=>clr1,q=>qq1,d=>dd1);U2 :ncount GENERIC MAP(n=>6)PORT MAP( clk=>aa ,en=>en1 ,ctrl =>cctrl2,clr=>clr1,q=>qq2,d=>dd2);q1<=qq2*10+qq1;process (qq1,qq2)beginif ( qq2*10+qq1 = 0 ) thenc1<='1';elsec1<='0';end if;end process;end rtl;锁存器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY keep ISPORT (CTRL:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);DOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END keep;ARCHITECTURE one OF keep ISBEGINPROCESS(CTRL,DIN)beginDOUT<=DIN;END IF;END PROCESS;END one;分频器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY pinlvji ISPORT(CLK:IN STD_LOGIC;RST_CNT:OUT STD_LOGIC;CNT_EN:OUT STD_LOGIC;LOAD:OUT STD_LOGIC);END ENTITY pinlvji;ARCHITECTURE beh1 OF pinlvji ISSIGNAL AA:STD_LOGIC ;BEGINPROCESS(CLK)BEGINIF CLK'EVENT AND CLK='1' THEN AA<=NOT AA; END IF;END PROCESS;PROCESS (CLK,AA)BEGINIF CLK='0' AND AA='0' THEN CNT_EN<='1'; ELSE CNT_EN<='0';END IF;END PROCESS;LOAD<=NOT AA;RST_CNT<=AA;END BEH1;。
vhdl语言100例程序
vhdl语言100例程序以下是100个关于VHDL语言的程序示例：1. 用VHDL编写一个计数器模块2. 用VHDL编写一个SR-Latch模块3. 用VHDL编写一个JK-Flip Flop模块4. 用VHDL编写一个D-Flip Flop模块5. 用VHDL编写一个T-Flip Flop模块6. 用VHDL编写一个复位计数器模块7. 用VHDL编写一个移位寄存器模块8. 用VHDL编写一个状态机模块9. 用VHDL编写一个MUX模块10. 用VHDL编写一个DeMUX模块11. 用VHDL编写一个加法器模块12. 用VHDL编写一个减法器模块13. 用VHDL编写一个乘法器模块14. 用VHDL编写一个除法器模块15. 用VHDL编写一个比较器模块16. 用VHDL编写一个位逻辑模块17. 用VHDL编写一个字逻辑模块18. 用VHDL编写一个数据选择器模块19. 用VHDL编写一个FIFO队列模块20. 用VHDL编写一个LIFO栈模块21. 用VHDL编写一个流水线模块22. 用VHDL编写一个中断控制器模块23. 用VHDL编写一个时钟分频器模块24. 用VHDL编写一个IO控制器模块25. 用VHDL编写一个SPI通信控制器模块26. 用VHDL编写一个I2C通信控制器模块27. 用VHDL编写一个UART通信控制器模块28. 用VHDL编写一个哈希函数模块29. 用VHDL编写一个随机数产生器模块30. 用VHDL编写一个CRC校验器模块31. 用VHDL编写一个AES加密算法模块32. 用VHDL编写一个DES加密算法模块33. 用VHDL编写一个SHA加密算法模块34. 用VHDL编写一个MD5加密算法模块35. 用VHDL编写一个RSA加密算法模块36. 用VHDL编写一个卷积滤波器模块37. 用VHDL编写一个峰值检测器模块38. 用VHDL编写一个平滑滤波器模块39. 用VHDL编写一个中值滤波器模块40. 用VHDL编写一个微处理器模块41. 用VHDL编写一个信号发生器模块42. 用VHDL编写一个信号采集器模块43. 用VHDL编写一个频率计算器模块44. 用VHDL编写一个相位计算器模块45. 用VHDL编写一个时序分析器模块46. 用VHDL编写一个正弦波产生器模块47. 用VHDL编写一个余弦波产生器模块48. 用VHDL编写一个数字滤波器模块49. 用VHDL编写一个数字信号处理器模块50. 用VHDL编写一个数字识别模块51. 用VHDL编写一个自动售货机模块52. 用VHDL编写一个二进制加法器模块53. 用VHDL编写一个二进制减法器模块54. 用VHDL编写一个二进制乘法器模块55. 用VHDL编写一个二进制除法器模块56. 用VHDL编写一个自然对数模块57. 用VHDL编写一个指数函数模块58. 用VHDL编写一个三角函数模块59. 用VHDL编写一个高斯滤波器模块60. 用VHDL编写一个激光传感器模块61. 用VHDL编写一个超声波传感器模块62. 用VHDL编写一个光电传感器模块63. 用VHDL编写一个温度传感器模块64. 用VHDL编写一个气压传感器模块65. 用VHDL编写一个陀螺仪模块67. 用VHDL编写一个电流传感器模块68. 用VHDL编写一个电容传感器模块69. 用VHDL编写一个磁场传感器模块70. 用VHDL编写一个通信电缆模块71. 用VHDL编写一个电源控制器模块72. 用VHDL编写一个电机控制器模块73. 用VHDL编写一个汽车控制器模块74. 用VHDL编写一个飞机控制器模块75. 用VHDL编写一个摄像头模块76. 用VHDL编写一个音频控制器模块77. 用VHDL编写一个扬声器控制器模块78. 用VHDL编写一个拨号器模块79. 用VHDL编写一个振动控制器模块80. 用VHDL编写一个压力控制器模块81. 用VHDL编写一个过滤器模块82. 用VHDL编写一个微波发射模块84. 用VHDL编写一个智能电表模块85. 用VHDL编写一个闹钟模块86. 用VHDL编写一个计时器模块87. 用VHDL编写一个时间戳模块88. 用VHDL编写一个脉冲宽度模块89. 用VHDL编写一个电路仿真模块90. 用VHDL编写一个电路控制模块91. 用VHDL编写一个电路测试模块92. 用VHDL编写一个电路优化模块93. 用VHDL编写一个电路布局模块94. 用VHDL编写一个电路验证模块95. 用VHDL编写一个数字信号发生器模块96. 用VHDL编写一个数字信号反演器模块97. 用VHDL编写一个数字信号滤波器模块98. 用VHDL编写一个数字信号加速器模块99. 用VHDL编写一个数字信号降噪器模块100. 用VHDL编写一个数字信号解调器模块VHDL语言是一种硬件描述语言，它用于描述数字电路和系统。
vhdl编程实例
vhdl编程实例VHDL编程实例- 设计与实现一个4位的全加器在本篇文章中，我们将一步一步地回答如何设计和实现一个4位的全加器。
VHDL编程语言将是我们用于描述和模拟这个电路的工具。
第一步：理解全加器的原理在编写代码之前，我们首先需要理解全加器的原理。
全加器是一种用于对两个二进制数字进行相加的电路。
它接收三个输入信号：两个位的输入（A 和B）以及一个进位输入（C_in）。
全加器的输出结果为一个位的和（S）和一个进位输出（C_out）。
我们可以使用如下的真值表来描述全加器的输出结果：输入信号输出结果A B C_in S C_out0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1了解了全加器的工作原理后，我们可以开始编写代码了。
第二步：编写全加器的VHDL代码我们将使用VHDL语言来描述和模拟全加器。
下面是一个简单的4位全加器的VHDL代码实现：vhdlEntity声明entity full_adder isport (A, B : in std_logic_vector(3 downto 0);C_in : in std_logic;S : out std_logic_vector(3 downto 0);C_out : out std_logic);end full_adder;Architecture声明architecture Behavioral of full_adder isbeginprocess(A, B, C_in)variable carry : std_logic;begincarry := C_in;for i in 0 to 3 loopS(i) <= A(i) xor B(i) xor carry;carry := (A(i) and B(i)) or (carry and (A(i) xor B(i)));end loop;C_out <= carry;end process;end Behavioral;在此代码中，我们首先声明了一个实体（entity）和一个架构（architecture）。
VHDL语言实例
VHDL 语言实例例1:设计一七段显示译码器，用它来驱动七段发光管 到9和字母A 到F 。
LED 显示数码管为共阳极。
LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY HEX2LED ISP ORT(LED : OUT std_logic_vector(6 TO图例1七段显示译码器实体ARCHITECTURE HEX2LED_arc OF HEX2LED IS BEGIN--HEX-TO-SEVEN-SEGMENT DECODER --SEGMENT ENCODING--5 | |1-- — — — — --4 | |20);HEX2LEDHEX :IN std_logic_vector(3 DOWNTO HEXES. . 0]"0) );LED 显示十六进制数字0ENDHEX2LED;WITH HEX SELECTLED<= "1111001" when "0001","0100100" when "0010","0110000" when "0011","0011001" when "0100","0010010" when "0101","0000010" when "0110","1111000" when "0111","0000000" when "1000","0010000" when "1001","0001000" when "1010","0000011" when "1011","1000110" when "1100","0100001" when "1101","0000110" when "1110","0001110" when "1111","1000000" when others;END HEX2LED_arc;例 2 ：设计一个八选一数据选择器1)s 是通道选择信号,d0,d1,d2,d3,d4,d5,d6,d7 数据输入out1 是数据输出ENTITY sels ISP ORT(d0,d1,d2,d3,d4,d5,d6,d7:IN BIT;s :INTEGERRANGE0 TO 7;END sels;ARCHITECTURE sels_arc OF sels IS BEGINWITH s SELECTout1 <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3,d4 WHEN 4,d5 WHEN 5, d6 WHEN 6, d7 WHEN 7;END sels_arc;LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(IO,I1,I2,I3,I4,I5,I6,I7,A,B,C:IN std_logic; END mux8;sels图例2 (a)八选一数据选择器实体图例2 (b)八选一数据选择器实体out1 :OUT BIT);2)A,B,C 是通道选择信号,据输出10,11,12,13,14,15,16,17数据输入 Q 是数Q :OUT std_logic);ARCHITECTURE mux8_arc OF mux8 ISSIGNAL sel :INTEGER ；BEGINQ <= 10 AFTER 10 ns WHEN sel= 0 ELSE11 AFTER 10 ns WHEN sel= 1 ELSE 12 AFTER 10 ns WHEN sel= 2 ELSE 13 AFTER 10 ns WHEN sel= 3 ELSE 14 AFTER 10 ns WHEN sel= 4 ELSE 15 AFTER 10 ns WHEN sel= 5 ELSE 16 AFTER 10 ns WHEN sel= 6 ELSE 17 AFTER 10 ns ;sel <= 0 WHEN A=‘ 0' AND B= ‘ 0' AND C= ‘ 0' ELSE1 WHEN A= '1' AND B= ‘ 0'AND C='0' ELSE2 WHEN A='0' AND B=‘1' AND C= '0' ELSE3 WHEN A='1' AND B=‘1' AND C='0' ELSE4 WHEN A='0' AND B=‘ 0'AND C= '1' ELSE5 WHEN A='1' AND B=‘ 0'AND C= '1' ELSE6 WHEN A='0' AND B=‘ 0'AND C= '1' ELSE7；END mux8_arc;例3:设计一 D 触发器 d 是输入端，clk 是时钟信号控制端，q 是触发器的输出端。
VHDL设计实例
A4：IN STD_LOGIC_VECTOR(3 DOWNTO 0)；
第6章
VHDL设计应用实例
B4：IN STD_LOGIC_VECTOR(3 DOWNTO 0)； S4：OUT STD_LOGIC_VECTOR(3 DOWNTO 0)； CO4：OUT STD_LOGIC)； END COMPONENT ADDER4B； SIGNAL SC：STD_LOGIC； BEGIN U1：ADDER4B --例化(安装)一个4位二进制加法器U1 --4位加法器的进位标志
ENTITY CHK IS
PORT(DIN：IN STD_LOGIC； --串行输入数据位 CLK，CLR：IN STD_LOGIC； --工作时钟/复位信号 D：IN STD_LOGIC_VECTOR(7 DOWNTO 0)； --8位待检测预置数 AB：OUT STD_LOGIC_VECTOR(3 DOWNTO 0))；
PORT MAP(C4=>C8 ， A4=>A8(3 DOWNTO 0) ，
B4=>B8(3 DOWNTO0)， S4=>S8(3 DOWNTO 0)， CO4=>SC)；
第6章
VHDL设计应用实例
U2：ADDER4B
--例化(安装)一个4位二进制加法器U2
PORT MAP(C4=>SC ， A4=>A8(7 DOWNTO 4) ，
WHEN 5 => IF DIN =D(2) THEN Q<= 6 ；ELSE Q<=0；END IF；
WHEN 6 => IF DIN =D(1) THEN Q<= 7 ；ELSE Q<=0；END IF； WHEN 7 => IF DIN =D(0) THEN Q<= 8 ；ELSE Q<=0；END IF；
vhdl语言例程集锦
v h d l语言例程集锦 The document was prepared on January 2, 2021vhdl语言例程集锦Examples of VHDL DescriptionsAdvanced Electronic Design AutomationExamples of VHDL DescriptionsAuthor: Ian Elliott of Northumbria UniversityThis file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described interms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can besynthesised using current synthesis tools.Use the hierarchical links below to navigate your way through the examples:l Combinational Logicl Countersl Shift Registersl Memoryl State Machinesl Registersl Systemsl ADC and DACl ArithmeticCombinational Logicl Exclusive-OR Gate (Dataflow style)l Exclusive-OR Gate (Behavioural style)l Exclusive-OR Gate (Structural style)l Miscell aneous Logic Gatesl Three-input Majority Voterl Magnitude Comparatorl Quad 2-input Nand (74x00)l BCD to Seven Segment Decoderl Dual 2-to-4 Decoderl Octal Bus Transceiverl Quad 2-input ORl 8-bit Identity Comparatorl Hamming Encoderl Hamming Decoderl 2-to-4 Decoder with Testbench and Configurationl Multiplexer 16-to-4 using Selected Signal Assignment Statementl Multiplexer 16-to-4 using Conditional Signal Assignment Statementl Multiplexer 16-to-4 using if-then-elsif-else Statementl M68008 Address Decoderl Highest Priority Encoderl N-input AND GateCountersh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 1 ]Examples of VHDL Descriptionsl Counter using a Conversion Functionl Generated Binary Up Counterl Counter using Multiple Wait Statementsl Synchronous Down Counter with Parallel Loadl Mod-16 Counter using JK Flip-flopsl Pseudo Random Bit Sequence Generatorl Universal Counter/Registerl n-Bit Synchronous CounterShift Registersl Universal Shift Register/Counterl TTL164 Shift Registerl Behavioural description of an 8-bit Shift Registerl Structural Description of an 8-bit Shift RegisterMemoryl ROM-based Waveform Generatorl A First-in First-out Memoryl Behavioural model of a 16-word, 8-bit Random Access Memoryl Behavioural model of a 256-word, 8-bit Read Only MemoryState Machinesl Classic 2-Process State Machine and Test Benchl State Machine using Variablel State Machine with Asynchronous Resetl Pattern Detector FSM with Test Benchl State Machine with Moore and Mealy outputsl Moore State Machine with Explicit State encodingl Mealy State Machine with Registered Outputsl Moore State Machine with Concurrent Output LogicSystemsl Pelican Crossing Controllerl Simple Microprocessor Systeml Booth Multiplierl Lottery Number Generatorl Digital Delay Unitl Chess ClockADC and DACl Package defining a Basic Analogue typel 16-bit Analogue to Digital Converterl 16-bit Digital to Analogue Converterl 8-bit Analogue to Digital Converterl 8-bit Unipolar Successive Approximation ADCh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 2 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 7 ]Examples of VHDL DescriptionsArithmeticl 8-bit Unsigned Multiplierl n-bit Adder using the Generate Statementl A Variety of Adder Stylesl Booth MultiplierRegistersl Universal Registerl Octal D-Type Register with 3-State Outputsl Quad D-Type Flip-flopl 8-bit Register with Synchronous Load and ClearUniversal RegisterDescription - This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. The register can be loaded from a set of parallel data inputsand the mode is controlled by a 3-bit input. The 'termcnt' (terminal count) output goes high when the register contains zero.LIBRARY ieee;USEUSEENTITY unicntr ISGENERIC(n : Positive := 8); --size of counter/shifterPORT(clock, serinl, serinr : IN Std_logic; --serial inputsmode : IN Std_logic_vector(2 DOWNTO 0); --mode controldatain : IN Std_logic_vector((n-1) DOWNTO 0); --parallel inputs dataout : OUT Std_logic_vector((n-1) DOWNTO 0); --parallel outputstermcnt : OUT Std_logic); --terminal count outputEND unicntr;ARCHITECTURE v1 OF unicntr ISSIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0);BEGINmain_proc : PROCESSBEGINWAIT UNTIL rising_edge(clock);CASE mode IS--resetWHEN "000" => int_reg <= (OTHERS => '0');--parallel loadWHEN "001" => int_reg <= datain;--count upWHEN "010" => int_reg <= int_reg + 1;--count downWHEN "011" => int_reg <= int_reg - 1;--shift leftWHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl;--shift rightWHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);--do nothingWHEN OTHERS => NULL;END CASE;END PROCESS;det_zero : PROCESS(int_reg) --detects when count is 0BEGINtermcnt <= '1';FOR i IN int_reg'Range LOOPh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 3 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL DescriptionsIF int_reg(i) = '1' THENtermcnt <= '0';EXIT;END IF;END LOOP;END PROCESS;--connect internal register to dataout portdataout <= int_reg;END v1;Octal D-Type Register with 3-State OutputsSimple model of an Octal D-type register with three-state outputs using two concurrent statements.LIBRARY ieee;USEENTITY ttl374 ISPORT(clock, oebar : IN std_logic;data : IN std_logic_vector(7 DOWNTO 0);qout : OUT std_logic_vector(7 DOWNTO 0));END ENTITY ttl374;ARCHITECTURE using_1164 OF ttl374 IS--internal flip-flop outputsSIGNAL qint : std_logic_vector(7 DOWNTO 0);BEGINqint <= data WHEN rising_edge(clock); --d-type flip flopsqout <= qint WHEN oebar = '0' ELSE "ZZZZZZZZ"; --three-state buffersEND ARCHITECTURE using_1164;Exclusive-OR Gate (Dataflow style)-- 2 input exclusive or-- Modeled at the RTL level.entity x_or isport (in1 : in bit ;in2 : in bit ;out1 : out bit);end x_or;architecture rtl of x_or isbeginout1 <= in1 xor in2 after 10 ns;end rtl;Exclusive-OR Gate (Behavioural style)-- Exclusive or gate-- modeled at the behavioral level.entity x_or isport (in1 : in bit ;in2 : in bit ;out1 : out bit) ;end x_or;architecture behavior of x_or ish t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 4 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptionsbeginprocess(in1, in2)beginif in1 = in2 thenout1 <= '0' after 10 ns;else out1 <= '1' after 10 ns;end if;end behavior;Exclusive-OR Gate (Structural style) -- 2 input exclusive-or gate.-- Modeled at the structural level. entity x_or isport (in1 : in bit ;in2 : in bit ;out1 : out bit) ;end x_or;entity and_gate isport (a : in bit ;b : in bit ;c : out bit) ;end and_gate;architecture behavior of and_gate is beginprocess(a,b)beginc <= a and b after 5 ns;end process;end behavior;entity or_gate isport (d : in bit ;e : in bit ;f : out bit) ;end or_gate;architecture behavior of or_gate is beginprocess(d,e)beginf <= d or e after 4 ns;end process;end behavior;entity inverter isport (g : in bit ;h : out bit) ;end inverter;architecture behavior of inverter is beginbeginh <= not g after 3 ns;end process;end behavior;h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 5 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptionsarchitecture structural of x_or is-- signal declarationssignal t1, t2, t3, t4 : bit;-- local component declarationscomponent and_gateport (a, b : in bit; c : out bit) ;end component;component or_gateport (d, e : in bit; f : out bit) ;end component;component inverterport (g : in bit; h : out bit) ;end component;begin-- component instantiation statementsu0: and_gate port map ( a => t1, b => in2, c => t3);u1: and_gate port map ( a => in1, b => t2, c => t4);u2: inverter port map ( g => in1, h => t1);u3: inverter port map ( g => in2, h => t2);u4: or_gate port map ( d => t3, e => t4, f => out1);end structural;Three-input Majority VoterThe entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.ENTITY maj ISPORT(a,b,c : IN BIT; m : OUT BIT);END maj;--Dataflow style architectureARCHITECTURE concurrent OF maj ISBEGIN--selected signal assignment statement (concurrent)WITH a&b&c SELECTm <= '1' WHEN "110"|"101"|"011"|"111",'0' WHEN OTHERS;END concurrent;--Structural style architectureARCHITECTURE structure OF maj IS--declare components used in architectureCOMPONENT and2 PORT(in1, in2 : IN BIT; out1 : OUT BIT);END COMPONENT;COMPONENT or3 PORT(in1, in2, in3 : IN BIT; out1 : OUT BIT);END COMPONENT;--declare local signalsSIGNAL w1, w2, w3 : BIT;BEGIN--component instantiation statements.--ports of component are mapped to signals--within architecture by position.gate1 : and2 PORT MAP (a, b, w1);gate2 : and2 PORT MAP (b, c, w2);gate3 : and2 PORT MAP (a, c, w3);gate4 : or3 PORT MAP (w1, w2, w3, m);h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 6 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL DescriptionsEND structure;--Behavioural style architecture using a look-up tableARCHITECTURE using_table OF maj ISBEGINPROCESS(a,b,c)CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111";VARIABLE index : NATURAL;BEGINindex := 0; --index must be cleared each time process executes IF a = '1' THEN index := index + 1; END IF;IF b = '1' THEN index := index + 2; END IF;IF c = '1' THEN index := index + 4; END IF;m <= lookuptable(index);END PROCESS;END using_table;Magnitude Comparator--VHDL description of a 4-bit magnitude comparator with expansion inputs--first architecture demonstrates use of relational operators on --bit vectors (=,>,<).Second architecture shows sequential behaviourdescriptions do not fully model behaviour of real--device for all possible combinations of inputs.ENTITY mag4comp ISGENERIC(eqdel,gtdel,ltdel : TIME := 10 ns); --output delay parametersPORT(a,b : IN BIT_VECTOR(3 DOWNTO 0); --input words, DOWNTO orderingneeded for comparison operatorsaeqbin,agtbin,altbin : IN BIT; --expansion inputsaeqbout,agtbout,altbout : OUT BIT); --outputsEND mag4comp;ARCHITECTURE dataflow OF mag4comp IS--this architecture assumes that only one of the expansion inputs --is active at any time,if more than one expansion input is active,--more than one output may be active.BEGINaeqbout <= '1' AFTER eqdel WHEN ((a = b) AND (aeqbin = '1'))ELSE '0' AFTER eqdel;agtbout <= '1' AFTER gtdel WHEN ((a > b) OR ((a = b) AND (agtbin = '1')))ELSE '0' AFTER gtdel;altbout <= '1' AFTER ltdel WHEN ((a < b) OR ((a = b) AND (altbin = '1')))ELSE '0' AFTER ltdel;END dataflow;ARCHITECTURE behaviour OF mag4comp ISBEGINPROCESS(a,b,aeqbin,agtbin,altbin)BEGINIF (a > b) THENagtbout <= '1' AFTER gtdel;aeqbout <= '0' AFTER eqdel;altbout <= '0' AFTER ltdel;ELSIF (a < b) THENaltbout <= '1' AFTER ltdel;aeqbout <= '0' AFTER eqdel;agtbout <= '0' AFTER gtdel;ELSE --a=b,expansion inputs have priority orderingIF (aeqbin = '1') THENaeqbout <= '1' AFTER eqdel;agtbout <= '0' AFTER gtdel;altbout <= '0' AFTER ltdel;ELSIF (agtbin = '1') THENagtbout <= '1' AFTER gtdel;altbout <= '0' AFTER ltdel;h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 7 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptionsaeqbout <= '0' AFTER eqdel;ELSIF (altbin = '1') THENagtbout <= '0' AFTER gtdel;altbout <= '1' AFTER ltdel;aeqbout <= '0' AFTER eqdel;ELSEagtbout <= '0' AFTER gtdel;altbout <= '0' AFTER ltdel;aeqbout <= '0' AFTER eqdel;END IF;END IF;END PROCESS;END behaviour;8-bit Register with Synchronous Load and ClearThe design entity shows the standard way of describing a register using a synchronous process, ie. a process containing a single wait statement which is triggered by a rising edge on the clock input.library ieee;useentity reg8 isport(clock, clear, load : in std_logic;d : in std_logic_vector(7 downto 0);q : out std_logic_vector(7 downto 0));end entity reg8;architecture v1 of reg8 isbeginreg_proc : processbeginwait until rising_edge(clock);if clear = '1' thenq <= (others => '0');elsif load = '1' thenq <= d;end if;end process;end architecture v1;BCD to Seven Segment DecoderThe use of the std_logic literal '-' (don't care) is primarilyfor the synthesis tool. This example illustrates the use of the selected signal assignment.LIBRARY ieee;USEENTITY seg7dec ISPORT(bcdin : IN std_logic_vector(3 DOWNTO 0);segout : OUT std_logic_vector(6 DOWNTO 0));END seg7dec;ARCHITECTURE ver3 OF seg7dec ISBEGINWITH bcdin SELECTsegout <= "1000000" WHEN X"0","1100111" WHEN X"1","1101101" WHEN X"2","0000011" WHEN X"3","0100101" WHEN X"4","0001001" WHEN X"5","0001000" WHEN X"6","1100011" WHEN X"7","0000000" WHEN X"8",h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 8 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptions"0000001" WHEN X"9","-------" WHEN OTHERS;END ver3;2-to-4 Decoder with Testbench and ConfigurationThis set of design units illustrates several features of the VHDL language including:l Using generics to pass time delay v alues to design entities.l Design hierarchy using instantiated components.l Test benches for design verification.l Configuration declaration for binding components to design entities and setting delay v alues.--ANATOMY OF A VHDL MODEL--This VHDL source description illustrates the use--of the basic constructs of VHDL.--The model describes a 2-input/4-output decoder--comprising two behavioural primitives 'inv' and 'and3'--instanced in a structure.-------------------------------------------------------------- ENTITY inv ISGENERIC(tplh,tphl,tplhe,tphle : TIME := 1 ns);PORT(a : IN BIT; b : OUT BIT);END inv;ARCHITECTURE behaviour OF inv ISBEGINPROCESS(a)VARIABLE state : BIT;BEGINstate := NOT(a);IF state = '1' THENb <= state AFTER (tplh + tplhe);ELSEb <= state AFTER (tphl + tphle);END IF;END PROCESS;END behaviour;--------------------------------------------------------------- ENTITY and3 ISGENERIC(tplh,tphl,tplhe,tphle : TIME := 1 ns);PORT(a1,a2,a3 : IN BIT; o1 : OUT BIT);END and3;ARCHITECTURE behaviour OF and3 ISBEGINPROCESS(a1,a2,a3)VARIABLE state : BIT;BEGINstate := a1 AND a2 AND a3;IF state = '1' THENo1 <= state AFTER (tplh + tplhe);ELSEo1 <= state AFTER (tphl + tphle);END IF;END PROCESS;END behaviour;--------------------------------------------------------------- ENTITY dec2to4 ISPORT(s0,s1,en : IN BIT; y0,y1,y2,y3 : OUT BIT);END dec2to4;ARCHITECTURE structural OF dec2to4 ISCOMPONENT invh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 9 o f6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL DescriptionsPORT(a : IN BIT; b : OUT BIT); END COMPONENT;COMPONENT and3PORT(a1,a2,a3 : IN BIT; o1 : OUT BIT); END COMPONENT;SIGNAL ns0,ns1 : BIT;BEGINi1 : inv PORT MAP(s0,ns0);i2 : inv PORT MAP(s1,ns1);a1 : and3 PORT MAP(en,ns0,ns1,y0);a2 : and3 PORT MAP(en,s0,ns1,y1);a3 : and3 PORT MAP(en,ns0,s1,y2);a4 : and3 PORT MAP(en,s0,s1,y3);END structural;-------------------------------------------------------------------ENTITY dec2to4_stim ISPORT(stimulus : OUT BIT_VECTOR(0 TO 2); response : INBIT_VECTOR(0 TO 3));END dec2to4_stim;ARCHITECTURE behavioural OF dec2to4_stim ISBEGINstimulus <= TRANSPORT "000" AFTER 0 ns,"100" AFTER 100 ns,"010" AFTER 200 ns,"110" AFTER 300 ns,"001" AFTER 400 ns,"101" AFTER 500 ns,"011" AFTER 600 ns,"111" AFTER 700 ns;END behavioural;--------------------------------------------------------------------ENTITY dec2to4_bench ISEND dec2to4_bench;ARCHITECTURE structural OF dec2to4_bench ISCOMPONENT dec2to4PORT(s0,s1,en : IN BIT; y0,y1,y2,y3 : OUT BIT);END COMPONENT;COMPONENT dec2to4_stimPORT(stimulus : OUT BIT_VECTOR(0 TO 2); response : INBIT_VECTOR(0 TO 3));END COMPONENT;SIGNAL stimulus : BIT_VECTOR(0 TO 2);SIGNAL response : BIT_VECTOR(0 TO 3);BEGINgenerator : dec2to4_stim PORT MAP(stimulus,response);circuit : dec2to4 PORT MAP(stimulus(1),stimulus(2),stimulus(0), response(0),response(1),response(2),response(3));END structural;--------------------------------------------------------------- CONFIGURATION parts OF dec2to4_bench ISFOR structuralFOR generator : dec2to4_stimUSE ENTITY (behavioural);END FOR;FOR circuit : dec2to4USE ENTITY (structural);FOR structuralFOR ALL : invUSE ENTITY (behaviour)GENERIC MAP(tplh => 10 ns,h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 0 of 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptionstphl => 7 ns,tplhe => 15 ns,tphle => 12 ns);END FOR;FOR ALL : and3USE ENTITY (behaviour)GENERIC MAP(tplh => 8 ns,tphl => 5 ns,tplhe => 20 ns,tphle => 15 ns);END FOR;END FOR;END FOR;END FOR;END parts;Generated Binary Up CounterThe first design entity is a T-type flip-flop. The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce regular structures of components.library ieee;useentity tff isport(clk, t, clear : in std_logic; q : buffer std_logic);end tff;architecture v1 of tff isbeginprocess(clear, clk)beginif clear = '1' thenq <= '0';elsif rising_edge(clk) thenif t = '1' thenq <= not q;elsenull;end if;end if;end process;end v1;library ieee;useentity bigcntr isgeneric(size : positive := 32);port(clk, clear : in std_logic;q : buffer std_logic_vector((size-1) downto 0));end bigcntr;architecture v1 of bigcntr iscomponent tff isport(clk, t, clear : in std_logic; q : buffer std_logic);end component;signal tin : std_logic_vector((size-1) downto 0);begingenttf : for i in (size-1) downto 0 generatettype : tff port map (clk, tin(i), clear, q(i));end generate;genand : for i in 0 to (size-1) generatet0 : if i = 0 generateh t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 1 of 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptionstin(i) <= '1';end generate;t1_size : if i > 0 generatetin(i) <= q(i-1) and tin(i-1);end generate;end generate;end v1;Counter using Multiple Wait StatementsThis example shows an inefficient way of describing a counter.--vhdl model of a 3-state counter illustrating the use--of the WAIT statement to suspend a each wait--statement the simulation time is updated one cycle,transferring --the driver v alue to the output count.--This architecture shows that there is no difference between--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'ENTITY cntr3 ISPORT(clock : IN BIT; count : OUT NATURAL);END cntr3;ARCHITECTURE using_wait OF cntr3 ISBEGINPROCESSBEGIN--WAIT UNTIL (clock'EVENT AND clock = '1');WAIT UNTIL clock = '1';count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1');WAIT UNTIL clock = '1';count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1');WAIT UNTIL clock = '1';count <= 2;END PROCESS;END using_wait;Counter using a Conversion FunctionThis counter uses a natural number to hold the count v alue and converts it into a bit_vector for output. Illustrates the use of a function.--4-bit binary up counter with asynchronous reset 2/2/93ENTITY cntr4bit ISPORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));END cntr4bit;ARCHITECTURE dataflow OF cntr4bit IS--interface function to generate output bit_vector from--internal count v alue.FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)RETURN BIT_VECTOR ISVARIABLE temp : NATURAL := 0;VARIABLE output : BIT_VECTOR(0 TO highbit);BEGINtemp := input;--check that input fits into (highbit+1) bitsASSERT (temp <= (2**(highbit + 1) - 1))REPORT "input no. is out of range" SEVERITY ERROR;h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 2 of 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptions--generate bit v aluesFOR i IN highbit DOWNTO 0 LOOPIF temp >= (2**i)THEN output(i) := '1';temp := temp - (2**i);ELSE output(i) := '0';END IF;END LOOP;RETURN output;END nat_to_bv;--signal to hold current count v alueSIGNAL intcount : NATURAL := 0;BEGIN--conditional natural signal assignment models counterintcount <= 0 WHEN (reset = '1') ELSE((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')ELSE intcount;--interface function converts natural count to bit_vector count count <= nat_to_bv(intcount,3);END;Quad 2-input NandSimple concurrent model of a TTL quad nand gate.--uses 1993 std VHDLlibrary IEEE;useentity HCT00 isport(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;Y1, Y2, Y3, Y4 : out std_logic);end HCT00;architecture VER1 of HCT00 isbeginY1 <= A1 nand B1 after 10 ns;Y2 <= A2 nand B2 after 10 ns;Y3 <= A3 nand B3 after 10 ns;Y4 <= A4 nand B4 after 10 ns;end VER1;Dual 2-to-4 DecoderA set of conditional signal assignments model a dual 2-to-4 decoder--uses 1993 std VHDLlibrary IEEE;useentity HCT139 isport(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);end HCT139;architecture VER1 of HCT139 isbeginY10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 3 of 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL DescriptionsY21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';end VER1;Quad D-Type Flip-flopThis example shows how a conditional signal assignment statement could be used to describe sequential logic (it is more common to use a process). The keyword 'unaffected' is equivalent to the 'null' statement in the sequential partof the language. The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.--uses 1993 std VHDLlibrary IEEE;useentity HCT175 isport(D : in std_logic_vector(3 downto 0);Q : out std_logic_vector(3 downto 0);CLRBAR, CLK : in std_logic);end HCT175;architecture VER1 of HCT175 isbeginQ <= (others => '0') when (CLRBAR = '0')else D when rising_edge(CLK)else unaffected;end VER1;Octal Bus TransceiverThis example shows the use of the high impedance literal 'Z' provided by std_logic. The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. Ports A and B must be resolved for this model to work correctly (hence std_logic rather than std_ulogic).library IEEE;useentity HCT245 isport(A, B : inout std_logic_vector(7 downto 0);DIR, GBAR : in std_logic);end HCT245;architecture VER1 of HCT245 isbeginA <=B when (GBAR = '0') and (DIR = '0') else (others => 'Z');B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');end VER1;Quad 2-input OR--uses 1993 std VHDLlibrary IEEE;useentity HCT32 isport(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;Y1, Y2, Y3, Y4 : out std_logic);end HCT32;architecture VER1 of HCT32 isbeginY1 <= A1 or B1 after 10 ns;Y2 <= A2 or B2 after 10 ns;Y3 <= A3 or B3 after 10 ns;Y4 <= A4 or B4 after 10 ns;h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r se w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 4 of 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ]Examples of VHDL Descriptionsend VER1;8-bit Identity Comparator--uses 1993 std VHDL。