交通灯信号控制器的设计实验报告

交通灯信号控制器的设计1、实验目的（1）学习QuartusII软件的基本使用方法。

（2）学习VHDL程序的基本结构和基本语句。

2、实验内容欲设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器，具体要求如下：（1）主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。

（2）主干道处于常允许通行状态，支干道有车来时才允许通行；当主干道允许通行亮绿灯时，支干道亮红灯；支干道允许通行亮绿灯时，主干道亮红灯。

（3）当主、支道均有车时，两者交替允许通行，主干道每次放行45s，支干道每次放行25s，在每次由亮绿灯变成亮红灯的转换过程中，要亮5s的黄灯作为过渡，并进行减计时显示。

3、设计思路交通控制器拟由单片的CPLD/FPGA来实现，经分析设计要求，整个系统由8个单元电路组成，包括：JTDKZ：交通灯状态控制CNT45S：45秒计时CNT05S：5秒计时CNT25S：25秒计时XSKZ：产生数码管段码数据，数据为BCD码YMQ：译码器，将BCD码转为段码CTRLS：产生数码管动态扫描信号MUXB41：4选1数据选择器，并产生位选信号整个控制系统中，U1为交通灯控制模块JTDKZ，此模块根据主、支道传感器信号SM、SB以及来自时基发生电路的时钟信号CLK，发出主、支道指示灯的控制信号，同时向各定时单元、显示控制单元发出使能控制信号EN45、EN25、EN05M、EN05B;U2、U3、U4为45s、5s、25s定时单元CNT45S、CNT05S、CNT25S，这些单元根据SM、SB、CLK及JTDKZ发出的有关使能控制信号EN45、EN25、EN05M、EN05B，按要求进行定时，并将其输出传送至显示控制单元；U5为显示控制单元XSKZ，此单元根据JTDKZ发出的有关使能控制信号EN1、EN2、EN3、EN4选择定时单元CNT45S、CNT05S、CNT25S的输出，并将之传送至各显示译码器：U6、U7、U8、U9为译码器YMQ，它将显示控制单元XSKZ的输出作为输入进行译码，将XSKZ的时间BCD码译码为数码管的8位段码，并将产生的段码经MUXB41送给数码管进行动态扫描显示的过程，动态扫描的选测信号由CTRLS产生。

在定时单元CNT45S和CNT25S的设计中，根据设计要求需要进行减计数，但本设计中仍使用的是加法计数，只是在将计数结果转换成两位BCD码时，将计数的最小值对应转换成显示定时的最大值，计数值加1时，转换的显示值减1，以此类推。

同时，由于主、支道从亮绿灯转到亮红灯中间有5s亮黄灯的时间过渡，因此对应的支、主道亮红灯的时间比对应的主、支道亮绿灯的时间要多5s，考虑到此原因，CNT45S和CNT25S计数器在把计数结果转换成显示的BCD码值时，将用于驱动绿灯的BCD码按实际定时要求转换，而将对应的用于驱动红灯的BCD码在实际定时要求的基础上加5进行转换。

4、实验设计1)系统原理框图本系统总体可分为两个两个层次，即LED显示和数码管显示，核心模块为JTDKZ产生系统的所有信号2)VHDL程序JTDKZ的VHDL程序--Jtdkz.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JTDKZ ISPORT(CLK,SM,SB:IN STD_LOGIC;MR,MY,MG,BR,BY,BG:OUT STD_LOGIC);END ENTITY JTDKZ;ARCHITECTURE ART OF JTDKZ ISTYPE STATE_TYPE IS(A,B,C,D);SIGNAL STATE:STATE_TYPE:=A;BEGINCNT:PROCESS(CLK) ISVARIABLE S:INTEGER RANGE 0 TO 45:=0;VARIABLE CLR:BIT:='0';VARIABLE EN:BIT:='0';BEGINIF(CLK'EVENT AND CLK='1') THENIF CLR='0' THEN S:=0;ELSIF EN='0' THEN S:=S;ELSE S:=S+1;END IF;CASE STATE ISWHEN A=>MR<='0';MY<='0';MG<='1';BR<='1';BY<='0';BG<='0';IF(SB AND SM)='1' THENIF S=45 THEN STATE<=B;CLR:='0';EN:='0';ELSE STATE<=A;CLR:='1';EN:='1';END IF;ELSIF(SB AND (NOT SM))='1' THENSTATE<=C;CLR:='0';EN:='0'; --STATE<=BELSE STATE<=A;CLR:='1';EN:='0'; --END IF;WHEN B=>MR<='0';MY<='1';MG<='0';BR<='1';BY<='0';BG<='0';IF S=5 THEN STATE<=C;CLR:='0';EN:='0';ELSE STATE<=B;CLR:='1';EN:='1';END IF;WHEN C=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='0';BG<='1';IF(SB AND SM)='1' THENIF S=25 THEN STATE<=D;CLR:='0';EN:='0';ELSE STATE<=C;CLR:='1';EN:='1';END IF;ELSIF SB='0' THEN STATE<=A;CLR:='0';EN:='0';ELSIF S=25 THEN STATE<=D;CLR:='0';EN:='0';ELSE STATE<=C;CLR:='1';EN:='1';END IF;WHEN D=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='1';BG<='0';IF S=5 THEN STATE<=A;CLR:='0';EN:='0';ELSE STATE<=D;CLR:='1';EN:='1';END IF;WHEN OTHERS =>STATE<=A;END CASE;END IF;END PROCESS CNT;END ARCHITECTURE ART;XSKZ的VHDL程序--Xskz.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XSKZ ISPORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC;AIN45M,AIN45B,AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ENTITY XSKZ;ARCHITECTURE ART OF XSKZ ISBEGINPROCESS(EN45,EN25,EN05M,EN05B,AIN45M,AIN45B,AIN25M,AIN25B,AIN05) IS BEGINIF EN45='1' THEN DOUTM<=AIN45M(7 DOWNTO 0);DOUTB<=AIN45B(7DOWNTO 0);ELSIF EN05M='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7DOWNTO 0);ELSIF EN25='1' THEN DOUTM<=AIN25M(7 DOWNTO 0);DOUTB<=AIN25B(7 DOWNTO 0);ELSIF EN05B='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7DOWNTO 0);END IF;END PROCESS;END ARCHITECTURE ART;CNT05S的VHDL程序--Cnt05s.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT05S ISPORT(CLK,EN05M,EN05B:IN STD_LOGIC;DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ENTITY CNT05S;ARCHITECTURE ART OF CNT05S ISSIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINPROCESS(CLK,EN05M,EN05B) ISBEGINIF(CLK'EVENT AND CLK='1') THENIF EN05M='1' THEN CNT3B<=CNT3B+1;ELSIF EN05B='1' THEN CNT3B<=CNT3B+1;ELSIF EN05B='0' THEN CNT3B<=CNT3B-CNT3B-1;END IF;END IF;END PROCESS;PROCESS(CNT3B) ISBEGINCASE CNT3B ISWHEN"000"=>DOUT5<="00000101";WHEN"001"=>DOUT5<="00000100";WHEN"010"=>DOUT5<="00000011";WHEN"011"=>DOUT5<="00000010";WHEN"100"=>DOUT5<="00000001";WHEN OTHERS=>DOUT5<="00000000";END CASE;END PROCESS;END ARCHITECTURE ART;CNT25S的VHDL程序--Cnt25s.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT25S ISPORT(SB,SM,CLK,EN25:IN STD_LOGIC;DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY CNT25S;ARCHITECTURE ART OF CNT25S ISSIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINPROCESS(SB,SM,CLK,EN25) ISBEGINIF (SB='0'OR SM='0')THEN CNT5B<=CNT5B-CNT5B-1;ELSIF(CLK'EVENT AND CLK='1') THENIF EN25='1' THEN CNT5B<=CNT5B+1;ELSIF EN25='0' THEN CNT5B<=CNT5B-CNT5B-1;END IF;END IF;END PROCESS;PROCESS(CNT5B) ISBEGINCASE CNT5B ISWHEN"00000"=>DOUT25M<="00100101";DOUT25B<="00110000";WHEN"00001"=>DOUT25M<="00100100";DOUT25B<="00101001";WHEN"00010"=>DOUT25M<="00100011";DOUT25B<="00101000";WHEN"00011"=>DOUT25M<="00100010";DOUT25B<="00100111";WHEN"00100"=>DOUT25M<="00100001";DOUT25B<="00100110";WHEN"00101"=>DOUT25M<="00100000";DOUT25B<="00100101";WHEN"00110"=>DOUT25M<="00011001";DOUT25B<="00100100";WHEN"00111"=>DOUT25M<="00011000";DOUT25B<="00100011";WHEN"01000"=>DOUT25M<="00010111";DOUT25B<="00100010";WHEN"01001"=>DOUT25M<="00010110";DOUT25B<="00100001";WHEN"01010"=>DOUT25M<="00010101";DOUT25B<="00100000";WHEN"01011"=>DOUT25M<="00010100";DOUT25B<="00011001";WHEN"01100"=>DOUT25M<="00010011";DOUT25B<="00011000";WHEN"01101"=>DOUT25M<="00010010";DOUT25B<="00010111";WHEN"01110"=>DOUT25M<="00010001";DOUT25B<="00010110";WHEN"01111"=>DOUT25M<="00010000";DOUT25B<="00010101";WHEN"10000"=>DOUT25M<="00001001";DOUT25B<="00010100";WHEN"10001"=>DOUT25M<="00001000";DOUT25B<="00010011";WHEN"10010"=>DOUT25M<="00000111";DOUT25B<="00010010";WHEN"10011"=>DOUT25M<="00000110";DOUT25B<="00010001";WHEN"10100"=>DOUT25M<="00000101";DOUT25B<="00010000";WHEN"10101"=>DOUT25M<="00000100";DOUT25B<="00001001";WHEN"10110"=>DOUT25M<="00000011";DOUT25B<="00001000";WHEN"10111"=>DOUT25M<="00000010";DOUT25B<="00000111";WHEN"11000"=>DOUT25M<="00000001";DOUT25B<="00000110";WHEN OTHERS=>DOUT25M<="00000000";DOUT25B<="00000000";END CASE;END PROCESS;END ARCHITECTURE ART;CNT45S的VHDL程序--Cnt45s.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT45S ISPORT(SB,SM,CLK,EN45:IN STD_LOGIC;DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY CNT45S;ARCHITECTURE ART OF CNT45S ISSIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0);BEGINPROCESS(SB,SM,CLK,EN45) ISBEGINIF SB='0' OR SM='0' THEN CNT6B<=CNT6B-CNT6B-1;ELSIF(CLK'EVENT AND CLK='1') THENIF EN45='1' THEN CNT6B<=CNT6B+1;ELSIF EN45='0' THEN CNT6B<=CNT6B-CNT6B-1;END IF;END IF;END PROCESS;PROCESS(CNT6B) ISBEGINCASE CNT6B ISWHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000"; WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001"; WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000"; WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111"; WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110"; WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101"; WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100"; WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011"; WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010"; WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001"; WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000"; WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="00111001"; WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000"; WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111"; WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110"; WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101"; WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100"; WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011"; WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";WHEN"101000"=>DOUT45M<="00000101";DOUT45B<="00010000";WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";WHEN"101100"=>DOUT45M<="00000001";DOUT45B<="00000110";WHEN OTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";END CASE;END PROCESS;END ARCHITECTURE ART;◆YMQ的VHDL程序LIBRARY IEEE;--数据译码器将XSKZ产生的BCD码数据转换为数码管显示的段码USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY YMQ ISPORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--数据输入，来源是XSKZ产生的8位数据，在取出高4位和低4位OUT8:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--段码数据END ENTITY YMQ;ARCHITECTURE ART OF YMQ ISBEGINPROCESS(AIN4)BEGINCASE AIN4 IS--将4位BCD码转换为8位段码数据WHEN "0000"=>OUT8<="00111111";WHEN "0001"=>OUT8<="00000110";WHEN "0010"=>OUT8<="01011011";WHEN "0011"=>OUT8<="01001111";WHEN "0100"=>OUT8<="01100110";WHEN "0101"=>OUT8<="01101101";WHEN "0110"=>OUT8<="01111101";WHEN "0111"=>OUT8<="00000111";WHEN "1000"=>OUT8<="01111111";WHEN "1001"=>OUT8<="01101111";WHEN OTHERS=>OUT8<="00000000";END CASE;END PROCESS P2;END ARCHITECTURE ART;◆MXB41的VHDL程序LIBRARY IEEE;--4选一数据选择器，以此实现共阴极数码管动态扫描显示USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUXB41 ISPORT(DATA1,DATA2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--数码管显示的数据段码DATA3,DATA4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);SE: IN STD_LOGIC_VECTOR(1 DOWNTO 0);SEDATA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--选择出的数据SECOM: OUT STD_LOGIC_VECTOR( 2 DOWNTO 0));--产生的位选数据--DATA1：主道低位段码--DATA2：主道高位段码--DATA3：支道低位段码--DATA4：支道高位段码END ENTITY MUXB41;ARCHITECTURE ART OF MUXB41 ISBEGINp1: PROCESS(SE) IS--对选择信号验证，以此产生送到数码管显示的数据BEGINIF SE="00" THEN SEDATA<=DATA1;ELSIF SE="01" THEN SEDATA<=DATA2;ELSIF SE="10" THEN SEDATA<=DATA3;ELSE SEDATA<=DATA4;END IF;END PROCESS P1;P2: PROCESS(SE) IS--对选择信号验证，以此产生送到数码管位选的数据BEGINCASE SE ISWHEN "00"=>SECOM<="000";--主道低位WHEN "01"=>SECOM<="001";--主道高位WHEN "10"=>SECOM<="100";--支道低位WHEN "11"=>SECOM<="101";--支道高位WHEN OTHERS =>SECOM<="111";END CASE;END PROCESS P2;END ARCHITECTURE ART;CTRLS的VHDL程序LIBRARY IEEE;--数码管动态扫描，原理：给一个CLK产生2个信号（4钟组合）将这两个信号送给4选1数据选择器，选出要在数码管上显示的数据，CLK要在24HZ以上USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CTRLS ISPORT(CLK:IN STD_LOGIC;SEL:OUT STD_LOGIC_VECTOR(1 DOWNTO 0));--数据选择器的选择信号END ENTITY CTRLS;ARCHITECTURE ART OF CTRLS ISSIGNAL CNT:STD_LOGIC_VECTOR(1 DOWNTO 0);--数据选择信号的信号变量BEGINPROCESS(CLK) ISBEGINIF CLK'EVENT AND CLK='1'THENIF CNT="11"THEN--选择信号变为11则时信号重新归为00，实现数码动态扫描显示数据CNT<="00";ELSECNT<=CNT+'1';END IF;END IF;END PROCESS;SEL<=CNT;END ARCHITECTURE ART;顶层文件DJTLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DJT ISPORT(SM:IN STD_LOGIC;SB:IN STD_LOGIC;CLK:IN STD_LOGIC;CLK2:IN STD_LOGIC;--此数码管扫描时钟必须在24HZ以上 M_G:OUT STD_LOGIC;M_Y:OUT STD_LOGIC;M_R:OUT STD_LOGIC;B_G:OUT STD_LOGIC;B_Y:OUT STD_LOGIC;B_R:OUT STD_LOGIC;COM:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);DATA:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ENTITY DJT;ARCHITECTURE ART OF DJT ISCOMPONENT JTDKZ ISPORT(CLK:IN STD_LOGIC;SM:IN STD_LOGIC;SB:IN STD_LOGIC;MG:OUT STD_LOGIC;MY:OUT STD_LOGIC;MR:OUT STD_LOGIC;BG:OUT STD_LOGIC;BY:OUT STD_LOGIC;BR:OUT STD_LOGIC);END COMPONENT JTDKZ;COMPONENT CNT45S ISPORT(SM:IN STD_LOGIC;SB:IN STD_LOGIC;CLK:IN STD_LOGIC;EN45:IN STD_LOGIC;DOUT45M:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END COMPONENT CNT45S;COMPONENT CNT05S ISPORT(CLK:IN STD_LOGIC;EN05M:IN STD_LOGIC;EN05B:IN STD_LOGIC;DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END COMPONENT CNT05S;COMPONENT CNT25S ISPORT(SM:IN STD_LOGIC;SB:IN STD_LOGIC;CLK:IN STD_LOGIC;EN25:IN STD_LOGIC;DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT CNT25S;COMPONENT XSKZ ISPORT(EN45:IN STD_LOGIC;AIN45M:IN STD_LOGIC_VECTOR(7 DOWNTO 0);AIN45B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);EN05M:IN STD_LOGIC;EN05B:IN STD_LOGIC;AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0);EN25:IN STD_LOGIC;AIN25M:IN STD_LOGIC_VECTOR(7 DOWNTO 0);AIN25B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUTM:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT XSKZ;COMPONENT CTRLS ISPORT(CLK:IN STD_LOGIC;SEL:OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); END COMPONENT CTRLS;COMPONENT MUXB41 ISPORT (DATA1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DATA2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DATA3:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DATA4:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SE: IN STD_LOGIC_VECTOR(1 DOWNTO 0);SEDATA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);SECOM: OUT STD_LOGIC_VECTOR( 2 DOWNTO 0)); END COMPONENT MUXB41;COMPONENT YMQ ISPORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUT8:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT YMQ;SIGNAL EN1,EN2,EN3,EN4:STD_LOGIC;SIGNAL S45M:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL S45B:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL S05:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL S25M:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL S25B:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL YM:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL YB:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL D1:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL D2:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL D3:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL D4:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINU1:JTDKZ PORT MAP(CLK,SM,SB,EN1,EN2,M_R,EN3,EN4,B_R);U2:CNT45S PORT MAP(SM,SB,CLK,EN1,S45M,S45B);U3:CNT05S PORT MAP(CLK,EN2,EN4,S05);U4:CNT25S PORT MAP(SM,SB,CLK,EN3,S25M,S25B);U5:XSKZ PORT MAP(EN1,S45M,S45B,EN2,EN4,S05,EN3,S25M,S25B,YM,YB); U6:YMQ PORT MAP(YM(3 DOWNTO 0),D1);U7:YMQ PORT MAP(YM(7 DOWNTO 4),D2);U8:YMQ PORT MAP(YB(3 DOWNTO 0),D3);U9:YMQ PORT MAP(YB(7 DOWNTO 4),D4);U10:CTRLS PORT MAP(CLK2,SEL);U11:MUXB41 PORT MAP(D1,D2,D3,D4,SEL,DATA,COM);M_G<=EN1;M_y<=EN2;B_G<=EN3;B_Y<=EN4;END ARCHITECTURE ART;5、实验结果及总结（1）系统仿真结果JTDKZJNT05JNT25JNT45CTRLSYMQ(2)硬件验证。