并行乘法器

EDA技术与应用
实验报告
一、实验目的
1、学习包集和元件例化语句的使用。

（五号+宋体，段前缩进2字符,固定值18磅行距）
2、学习FAU(全加器单元)电路的设计。

3、学习并行乘法器电路的设计。

二、实验内容
1、用VHDL代码描述FAU、与门电路，要求其操作数有a、b两个，每个操作数都是4位宽度。

2、利用元件例化语句构成所需要的基本元件，利用包集声明该元件，在主代码中调用该元件完成设计。

三、实验原理
1、并行乘法器的原理图：
2、TOP 单元：
（格式同上）
p(0)
p(1)
p(2)
p(3)
3、mid 单元
4、lower 单元
四、 实验代码
library ieee;
use ieee.std_logic_1164.all; entity adder is
port (a,b,cin:in std_logic; s,cout:out std_logic); end adder;
architecture adder of adder is begin
s<=a xor b xor cin;
cout<=(a and b)or(a and cin)or(b and cin); end adder;
+
+
+
p(0)
p(1)
p(2)
p(3)
sin(2)
sin(1)
sin(0)
cin(2)
cin(1)
cin(0)
local(0)
local(1)
local(2)
b(3)
b(2)
b(1)
b(0)
library ieee;
use ieee.std_logic_1164.all;
entity and_2 is
port (a,b:in std_logic;
y:out std_logic);
end and_2;
architecture and_2 of and_2 is
begin
y<=a and b;
end and_2;
library ieee;
use ieee.std_logic_1164.all;
use work.my_components.all;
entity top is
port (a:in std_logic;
b:in std_logic_vector(3 downto 0);
s,c:out std_logic_vector(2 downto 0);
p:out std_logic);
end top;
architecture reg of top is
begin
u1:component and_2 port map(a,b(3),s(2)); u2:component and_2 port map(a,b(2),s(1)); u3:component and_2 port map(a,b(1),s(0)); u4:component and_2 port map(a,b(0),p);
c(2)<='0';c(1)<='0';c(0)<='0';
end reg;
library ieee;
use ieee.std_logic_1164.all;
use work.my_components.all;
entity mid is
port (a:in std_logic;
b:in std_logic_vector(3 downto 0);
si,ci:in std_logic_vector(2 downto 0);
s,c:out std_logic_vector(2 downto 0);
p:out std_logic);
end mid;
architecture reg of mid is
signal d:std_logic_vector(2 downto 0);
begin
u1:component and_2 port map(a,b(3),s(2));
u2:component and_2 port map(a,b(2),d(2));
u3:component and_2 port map(a,b(1),d(1));
u4:component and_2 port map(a,b(0),d(0));
u5:component adder port map(si(2),ci(2),d(2),s(1),c(2)); u6:component adder port map(si(1),ci(1),d(1),s(0),c(1)); u7:component adder port map(si(0),ci(0),d(0),p,c(0)); end reg;
library ieee;
use ieee.std_logic_1164.all;
use work.my_components.all;
entity lower is
port (
si,ci:in std_logic_vector(2 downto 0);
p:out std_logic_vector(3 downto 0)
);
end lower;
architecture reg of lower is
signal d:std_logic_vector(2 downto 0);
begin
d(0)<='0';
u1:component adder port map(si(0),ci(0),d(0),p(0),d(1)); u2:component adder port map(si(1),ci(1),d(1),p(1),d(2)); u3:component adder port map(si(2),ci(2),d(2),p(2),p(3)); end reg;
library ieee;
use ieee.std_logic_1164.all;
package my_components is
component and_2 is
port(a,b:in std_logic;y:out std_logic);
end component;
component adder is
port(a,b,cin:in std_logic;s,cout:out std_logic); end component;
component top is
port (a:in std_logic;
b:in std_logic_vector(3 downto 0);
s,c:out std_logic_vector(2 downto 0);
p:out std_logic);
end component;
component mid is
port (a:in std_logic;
b:in std_logic_vector(3 downto 0);
si,ci:in std_logic_vector(2 downto 0);
s,c:out std_logic_vector(2 downto 0);
p:out std_logic);
end component;
component lower is
port (
si,ci:in std_logic_vector(2 downto 0);
p:out std_logic_vector(3 downto 0)
);
end component;
end my_components;
library ieee;
use ieee.std_logic_1164.all;
use work.my_components.all;
entity multiplier is
port (a,b:in std_logic_vector(3 downto 0);
pord:out std_logic_vector(7 downto 0));
end multiplier;
architecture reg of multiplier is
type matrix is array (0 to 3)of
std_logic_vector(2 downto 0);
signal s,c:matrix;
begin
u1:component top port map (a(0),b,s(0),c(0),pord(0));
u2:component mid port map (a(1),b,s(0),c(0),s(1),c(1),pord(1)); u3:component mid port map (a(2),b,s(1),c(1),s(2),c(2),pord(2)); u4:component mid port map (a(3),b,s(2),c(2),s(3),c(3),pord(3)); u5:component lower port map (s(3),c(3),pord(7 downto 4));
end reg;
五、电路仿真结果
六、管脚配制。