离散余弦变换(DCT)的DSP程序设计与实现

D S P课程设计论文题目离散余弦变换(DCT)的DSP实现专业电气工程及其自动化姓名陈梦泽班级 11东电气学号 ******** 执行学期 2014-2015离散余弦变换（DCT）的DSP实现一、实验目的1. 掌握离散余弦变换的概念和实现方法；2. 掌握用 C 语言或汇编语言编写 DSP 程序的方法；3. 熟悉DCT原理；二、实验设备1. 一台装有 CCS 软件的计算机；2. DSP 实验箱的TMS320C5410 主控板；3. DSP 硬件仿真器；三、实验原理论述1、原理离散余弦变换（Discrete Cosine Transform，简称DCT变换）是一种与傅立叶变换紧密相关的数学运算。

在傅立叶级数展开式中，如果被展开的函数是实偶函数，那么其傅立叶级数中只包含余弦项，再将其离散化可导出余弦变换，因此称之为离散余弦变换。

对于给定的实际数据序列x(0),X(1) ，x(2)....X( N-1 )的DCT(FDCT)算法如下：z(k)N ()()cos()=+⎡⎣⎢⎤⎦⎥=-∑22121απk x nn kNnN(1)其中:αα()()kk==≠12for k=01 for k0(2)二维离散余弦变换（FDCT）：z(k,)()()(,)cos ()cos()lN k l x m nm kNn lNmNnN=⎛⎝⎫⎭⎪+⎡⎣⎢⎤⎦⎥+⎡⎣⎢⎤⎦⎥=-=-∑∑221221211ααππ(3)其逆运算是:x m nN k l z k lm kNn lNlNkN(,)()()(,)cos ()cos()=⎛⎝⎫⎭⎪+⎡⎣⎢⎤⎦⎥+⎡⎣⎢⎤⎦⎥=-=-∑∑221221211ααππ(4)其中 N= 8 为 8x8 DCT.2、DCT的DSP 程序设计无论是C语言还是汇编语言，程序流程均分为初始化、行变换、列变换和移位输出四个步骤。

行、列变换具有相似性，如果对行变换的结果矩阵转置，则列变换程序跟行变换一样。

对于汇编而言，初始化部分主要初始化FP指针以指向前一函数地址，初始化数据和指针寄存器以保存返回数据等。

由于DCT行变和列变换过程相似，且列变换是在行变换操作的基础上进行的。

则可利用多种索引寻址寄存器的灵活组合，把行变换结果直接以转置方式存储而不增加实际的存储时间，这样行列变换可使用同一代码循环两次实现，减小了实际代码大小。

本程序实现的是FDCT，可以使用2次一维DCT变换来实现二维DCT变换。

3、DCT的DSP实现二维DCT 变换时结果为两次无理数sqrt（8）相乘，产生了有理项，因此，在程序里首先多乘一次sqrt（8），然后在两次DCT 变换结束以后，使用右移3位以达到正常输出。

四、方案论证及系统设计本次实习有两种方案，C语言和汇编语言实现，由于考虑到DSP程序的特点，我采用汇编语言实现。

1.打开CCS软件，编制程序简化行列变换的代码如下：2.B0 = R0;B3 = R1;B2 = R2; …LSETUP （DCT_START, DCT_END） LC0 = P0;DCT_START:…LSETUP（ROW_START,ROW_END）LC1=P2;ROW_START: …ROW_END:…B1 = B0;B0 = B2;DCT_END:B2 = B1;五、一维DCT变换流程图六、程序模块源程序DSP程序：.mmregs.def entry.sect "INIT"** Initialise*entry NOPNOPSSBX SXM ; set sign extension modeSSBX OVM ; enable saturationLD #0, DP ; set data pageSTM 0FFE0h, PMST ; Init PMST reg.RSBX FRCT.include "fdct_dat.inc" ; FDCT data storage declaration MODE .SET 1 ; MODE=1 TEST ON SIMULATOR PAGE0 .SET 0PAGE4 .SET 4PAGE24 .SET 24dPAGE25 .SET 25dB0 .SET 0200hB1 .SET 0300hB2 .SET 060hPA1BIS .SET 1PA2BIS .SET 2PA3BIS .SET 3PA4BIS .SET 4PA5BIS .SET 5PA6BIS .SET 6* Initialization of the registers.sect "FDCT"INIT LD #PAGE24, DPST #21407, E_P6ST #8867, F_P6ST #2000H, ROUND1TBL: LD #PAGE25, DPST #21407, E_P7ST #8867, F_P7ST #4000H, ROUND2ST #40H, ROUND3START* IF MODE = SIMULATOR.IF MODE=1STM #63, AR0 ; AR0= # of inputs to be taken - 1 STM #X, AR1 ; AR1= address of first input BEG PORTR #PA1BIS, *AR1+ ; Read and store to addr(AR1)BANZ BEG, *AR0- ; Repeat above code 64 times; till all 64 pixels are read .ENDIFSTM #3, AR0STM #X, AR1 ; Reset AR1 to first inputSTM #Y00, AR2 ; Set AR2 to first Y blockDCT1 NOPNOPLD #PAGE24, DPLD *AR1+, 4, A ; + (16)*(X0)ADD *AR1+, 4, A ; + (16)*(X1)ADD *AR1+, 4, A ; + (16)*(X2)ADD *AR1+, 4, A ; + (16)*(X3)ADD *AR1+, 4, A ; + (16)*(X4)ADD *AR1+, 4, A ; + (16)*(X5)ADD *AR1+, 4, A ; + (16)*(X6)ADD *AR1, 4,A ; + (16)*(X7)STL A, Y00 ; = Y00RPTZ A, #7MACP *AR1-, COEF_F1, ASFTA A, 4MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1STH A, 2, Y01 ; = Y01LD ROUND1, -4, A ; (ROUND1)/16LD E_P6, TMAC *AR1+0, A ; + X0*E_P6MAS *AR1+, A ; - X3*E_P6MAS *AR1+0, A ; - X4*E_P6MAC *AR1-, A ; + X7*E_P6LD F_P6, TMAC *AR1-, A ; + X6*F_P6MAS *AR1-0, A ; - X5*F_P6MAS *AR1-, A ; - X2*F_P6MAC *AR1-, A ; + X1*F_P6 STH A, 6, Y02 ; Multiply prev summation by 16; = Y02RPTZ A, #7MACP *AR1+, COEFF2, A ;64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5SFTA A, 4MAR *AR1-ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1STH A, 2, Y03 ; = Y03LD *AR1-, 4, A ; X7*16SUB *AR1-, 4, A ; - X6*16SUB *AR1-, 4, A ; - X5*16ADD *AR1-, 4, A ; + X4*16ADD *AR1-, 4, A ; + X3*16SUB *AR1-, 4, A ; - X2*16SUB *AR1-, 4, A ; - X1*16ADD *AR1, 4, A ; + X0*16STL A, Y04 ; = Y04RPTZ A, #7MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5 SFTA A, 4 ; +C*X6-D*X7)MAR *AR1-ADD ROUND1, A ; + 4*ROUND1STH A, 2, Y05 ; = Y05LD ROUND1, -4, A ; (ROUND1)/16LD F_P6, TMAC *AR1-0, A ; + F_P6*X7MAS *AR1-, A ; - F_P6*X4MAS *AR1-0, A ; - F_P6*X3MAC *AR1+, A ; + F_P6*X0LD E_P6, TMAS *AR1+, A ; - E_P6*X1MAC *AR1+0, A ; + E_P6*X2MAC *AR1+, A ; + E_P6*X5MAS *AR1+, A ; - E_P6*X6STH A, 6, Y06 ; Multiply prev summation by 16; = Y06RPTZ A, #7MACP *AR1-, COEF_F4, A ;64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5SFTA A, 4 ; +C*X6-D*X7)MAR *AR1+ADD ROUND1, A ; + 4*ROUND1STH A, 2, Y07 ; = Y07MAR *+AR1(8) ; Set AR1 to point to the next set ; of 8 inputsDCT3 NOPNOP** PLACE FDCT COEFFICIENTS IN FILE POINTED BY PA2.IF MODE=1STM #63, AR0 ; AR0= # of outputs - 1STM #Z00, AR1 ; AR1= addr of first outputBEG1 PORTW *AR1+, #PA2BIS ; Send output valueBANZ BEG1, *AR0- ; Repeat above process (64x) .ENDIFEXIT NOPB START ; Go to start of program.; Grab another 64 pixelsCOEF_F1 .WORD -22725,-19266,-12873,-4520,4520,12873,19266,22725COEFF2 .WORD 19266,-4520,-22725,-12873,12873,22725,4520,-19266 COEFF3 .WORD 12873,-22725,4520,19266,-19266,-4520,22725,-12873 COEF_F4 .WORD -4520,12873,-19266,22725,-22725,19266,-12873,4520 * with: A = cos(?16)*?*16384 = 22725* B = cos(3?16)*?*16384 = 19266* C = cos(5?16)*?*16384 = 12873* D = cos(7?16)*?*16384 = 4520* E = cos(?8)*?*16384 = 21407* F = cos(3?8)*?*16384 = 8867*.END链接文件：-m fdct.map-o fdct.out-e entryfdct.objMEMORY{PAGE 0: OCDARAM1: origin = 00080h length = 00880h /* on-chip DARAM */OCDARAM2: origin = 00900h length = 00300hOCDARAM4: origin = 00C00h length = 00400hOCDARAM5: origin = 01000h length = 00400hEXTERNAL: origin = 01400h length = 0EB80hINTRVECS: origin = 0FF80h length = 00079hPAGE 1: MMREGS: origin = 00000h length = 00060hSPRAM: origin = 00060h length = 00020hOCDARAM1: origin = 00080h length = 00400h /* on-chip DARAM */OCDARAM2: origin = 00480h length = 0077FhOCDARAM4: origin = 00C00h length = 00400hOCDARAM5: origin = 01000h length = 00400hEXTERNAL: origin = 01400h length = 0EC00h}SECTIONS{INIT > OCDARAM1 PAGE 0FDCT > OCDARAM1 PAGE 0.bss > OCDARAM4 PAGE 1}七、仿真调试及性能分析与实验1.开电，运行CCS软件，打开项目文件fdct.prj，编译运行并下载。