无电阻零电流检测的有源功率校正校正电路

Active Power Factor Correction(PFC)Circuit With Resistor-Free Zero-Current Detection Yong-Seong Roh,Young-Jin Moon,Jung-Chul Gong,and Changsik Yoo,Member,IEEEAbstract—An active power-factor correction(PFC)circuit is presented that employs a newly proposed resistor-free zero-current detection(ZCD).While the conventional ZCD requires either a sensing resistor or auxiliary transformer,the proposed ZCD re-quires only one OFF-chip capacitor.The active PFC circuit with the proposed resistor-free ZCD has been implemented in a0.35-μm BCDMOS process and the power factor is improved up to9%from the one employing the conventional ZCD.The proposed resistor-free ZCD scheme can be applied to any type of switch-mode dc–dc power converter.Index Terms—Critical conduction mode(CRM),discontinuous conduction mode(DCM),power-factor correction(PFC),zero-current detection(ZCD).I.I NTRODUCTIONP OWER factor(PF)is defined as the ratio of real power to apparent power,where real power produces real work and apparent power is the total power that a power company has to supply[1].When PF is not100%,the current waveform does not follow the voltage waveform.This results in power losses and may also cause harmonics that travel down the neutral line and disrupt other devices connected to the line[1],[2].The power-factor-correction(PFC)circuit basically shapes the input current waveform to be the replica of the input voltage waveform and exactly in phase with it.Active PFC is preferred to passive one because of its small form factor and much better PF.Active PFC is usually based on a boost converter where the feedback control can be performed in either continuous conduction mode(CCM),discontinuous con-duction mode(DCM),or critical conduction mode(CRM)[3]. Converter that operates in CCM induces small device current stress and the requirement on inputfilter is relaxed.However, the hard turn-OFF of freewheeling diode increases power lossManuscript received February8,2010;revised April22,2010and June29, 2010;accepted August6,2010.Date of current version February11,2011. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea(NRF)funded by the Ministry of Educa-tion,Science,and Technology under Grant2010–0012551,and by the Samsung Power IC Design(SPID)Center,University of Seoul,Korea.The CAD tools were provided by IDEC.Recommended for publication by Associate Editor J.A.Pomilio.Y.-S.Roh,Y.-J.Moon,and C.Yoo are with the Integrated Circuits Laboratory, Hanyang University,Seoul133–791,Korea(e-mail:amyung@hanyang.ac.kr; worthforj@;csyoo@hanyang.ac.kr).J.-C.Gong is with the Integrated Circuits Laboratory,Hanyang University, Seoul133–791,Korea,and also with Samsung Electro-Mechanics,Suwon 442-743,Korea(e-mail:jungchul.gong@).Color versions of one or more of thefigures in this paper are available online at .Digital Object Identifier10.1109/TPEL.2010.2070080Fig.1.Conventional ZCD techniques.(a)With a sensing resistor R C S.(b)With an auxiliary transformer.and switching noise.DCM is commonly used for low-powerapplication.Freewheeling diode is turned off softly and switchis turned on at zero current,providing high efficiency.CRM thatoperates at the boundary between CCM and DCM has interme-diate characteristics.Both DCM and CRM are often combinedto exploit the advantages of each mode.When downstream con-verter requires large output power,CRM is selected to reducepeak inductor current.When low output power is required,DCMis used to reduce switching frequency for higher efficiency[4].For DCM and CRM operation,the instant when inductor cur-rent becomes zero has to be detected by a zero-current-detection(ZCD)circuit.The simplest way of detecting the instant when the inductorcurrent I L becomes zero is to insert a sensing resistor in serieswith the inductor and sense the voltage drop across it[5].Sincesilicon process technologies allow only limited voltage stresson active devices,it is safer to place a sensing resistor R CSon the ground line,as shown in Fig.1(a).This incurs a powerloss and noise on the ground line,decreasing the efficiency andachievable PF.If an auxiliary transformer is used,as shownin Fig.1(b),the voltage induced in the secondary winding is 0885-8993/$26.00©2010IEEEFig.2.PFC circuit with resistor-free ZCD.The components in the shaded regions are off-chip.utilized to sense the zero current of the primary winding,and the power loss due to sensing resistor can be avoided[6].However, the auxiliary transformer increases the form factor and cost. There have been lots of alternative approaches to overcome the aforementioned issues of the conventional ZCD schemes [7],[18].By monitoring the inductor voltage,ZCD can be per-formed[7],but it cannot be applied to PFC because the inductor voltage may be extremely large in PFC and active devices for ZCD can be exposed to severe voltage stress.Based on the relationship between inductor current and voltage,the input line current can be sensed by monitoring the input and output voltages[8],[9],but high-performance digital signal process-ing(DSP)is required.The optimum duty cycle of switching clock can be stored in memory to remove current sensor[10], but to be operable in universal condition,huge amount of data have to be stored.Lee and Lim implemented a three-phase pulsewidth modulation(PWM)rectifier with a current sensor on ground line[11].The input line current is reconstructed using the sensed ground line current and switching states of the PWM rectifier,but this cannot be applied to a single-phase PFC converter.In[12],the current through switch transistor is sensed with a sensing resistor instead of inductor current. In[13]–[18],techniques for removing current sensor and/or voltage sensor are described.With the technique in[13],PF can be greatly degraded in the presence of harmonic components in the input voltage.Fast DSP is required to implement the scheme in[14].The scheme in[15]requires extremely large RC time constant to implement a differentiator and envelop detec-tor.In[16]and[17],the output current is predicted from digital data streams of digitally controlled electronic load in dc–dc con-verters,and therefore,this scheme cannot be used for general applications.In[18],current sensor is removed by employing a phase shifter,but the improvement of PF is limited under various load conditions.In this paper,a new ZCD is proposed where the instant of zero inductor current is detected by monitoring the input andoutput Fig.3.Waveform of the inductor current in DCM and CRM.In CRM t3is zero.voltage instead of inductor current or voltage.The proposed scheme does not require any sensing resistor,and therefore,is called resistor-free ZCD.For resistor-free ZCD,only one exter-nal capacitor is additionally required.In Section II,the opera-tion principle is explained and its implementation detail is given in Section III.The experimental results follow in Section IV, andfinally,Section V concludes this paper.II.R ESISTOR-F REE ZCD T ECHNIQUEFig.2shows the active PFC circuit employing the proposed resistor-free ZCD technique.The resistor-free ZCD circuit de-tects the instant of zero inductor current by monitoring input and output voltages.The bandgap reference provides an accurate reference voltage level with which the resistor-divided output voltage V out div is compared to generate the error voltage V err. Fig.3shows the waveform of the inductor current in DCM and CRM,where t3is zero in CRM.Ignoring the voltage drop across the diode D1,the voltage across the inductor is V in and V in−V out when the power switch M N is turned on and off,Fig.4.(a)Resistor-free ZCD circuit where the capacitor C1is off-chip and (b)multiplied by two circuits.respectively.Therefore,t1and t2are related with each other ast2=V inV out−V int1.(1)If V in and V out are known,t2is predictable because t1is the internally generated timing.The inductor current is zero at t= t1+t2and the instant of zero inductor current is predictable. Since the switching frequency for PFC control is much higher than the frequency of the input line voltage,the rectified line voltage V in can be safely assumed to be dc.III.I MPLEMENTATIONA.Resistor-Free ZCD CircuitThe resistor-free ZCD circuit is very simple as shown in Fig.4(a).The signalΦ1is the gate-driving signal of the power switch M N.WhenΦ1is high,the capacitor C1is charged by the current source I1that is designed to be V in div/R B,where V in div is the scaled input voltage,as shown in Fig.2.The voltage V C1across C1is amplified by the multiply-by-two circuit in Fig.4(b)to get V C2.At t=t1,V C1is I1t1/C1,and therefore, V C2is2I1t1/C1,which is held on C2whileΦ1is low.WhenΦ1 is low,C1is charged by I2,which is(V out div−V in div)/R B, where V out div is the scaled output voltage,as shown in Fig.2. The output of the comparator is high when V C1becomes larger than V C2.At this instant,V C1is given asV C1=I1t1C1+I2t 2C1=2I1t1C1(2) and t2can be rearranged ast 2=I1t1I2=V in div/R B(V out div−V in div)/R Bt1.(3)If the resistance ratios R1/R2and R3/R4of the input and output voltage dividers of Fig.2are equal to each other,t 2is given ast 2=V inV out−V int1.(4) We can see that t 2in(4)is equal to t2in(1),and therefore, when the comparator output V comp becomes high and dead time (DT)is set to high,the inductor current is zero.The timing of the resistor-free ZCD circuit is shown in Fig.5.The additional advantage of the resistor-free ZCD circuit, shown in Fig.4(a),is the overcurrent protection(OCP)that can be performed without a sensing resistor by detecting V C1during t1because V C1is proportional to the input line current during t1.However,the current chip does not utilize this feature,and a sensing resistor is inserted between the source of M N and ground in Fig.2for OCP.In the conventional ZCD scheme employing a sensing resistor on the ground line,the magnitude of the sensing resistor should be small to avoid substantial power loss.However,near the zero-current condition,the current level is very small and the ZCD with small sensing resistance can be very susceptible to noise.In the proposed resistor-free ZCD,the sensing resistor inserted between the source of M N and ground is to detect overcurrent condition.Therefore,even with small sensing resistance,OCP is rather immune to noise.B.Current Generator for I1and I2For proper operation of the resistor-free ZCD,the currents I1and I2are precisely generated by the current generator shown in Fig.6.The currents through the transistors M1and M2are regulated to be V in div/R B and V out div/R B,respec-tively,by gain-boosted cascode stages.The current through M1 is copied to the transistor M20that provides the current out-put I1=V in div/R B.The current through M2is copied to the transistor M11from which V in div/R B is subtracted to have cur-rent(V out div−V in div)/R Bflow through the transistor M18, which provides the current output I2.In order to improve the matching property between the two resistors,dummy resistors are used and the common centroid layout technique is applied.The phase margin of the feedback loop composed of A1,M1,and R B(A2,M2,and R B)is81◦, while the loop gain is60dB and the unity gain frequency is 32MHz.C.V tO NProcessing CircuitFrom Fig.3,the average input current can be calculated asI in,avg=t1(t1+t2)V in2LT.(5)Fig.5.Timing diagram of resistor-free ZCD in(a)DCM and(b)CRM.If PFC operates in CRM where t1+t2=T,the average input current is proportional to the input voltage for constant t1,and thus,PF is properly corrected.However,in DCM,the aforementioned statement does not apply,and from(1),the average input current can be expressed asI in,avg=t21V in V out2LT(V out−V in).(6)It is clear that the average input current is not proportionalto V in and the harmonics may be present in the input current,resulting in poor PF.In order to improve PF in DCM,the errorvoltage V err is postprocessed with the V tO Nprocessing circuit[5].The V tO Nprocessing circuit is redrawn in Fig.7(a)and itstiming diagram is shown in Fig.7(b).Assuming the operationalamplifier to be ideal,the following relationship holds:V x−V errR p1=C p1d(V err−V y)dt.(7)Since the error voltage V err in Fig.2is nearly dc,the slope ofV y is given asdV ydt=V err−V xR p1C p1.(8)When DT is low,V x is equal to V y and V y is discharged asmuch asΔV y|D T=low=−t1+t2dV y=−1R p1C p1t1+t2(V err−V y)dt.(9)Since the time constant R p1C p1in Fig.7(a)is set to be muchlarger than the clock period T,it can be safely assumed that V y isdischarged linearly when DT is low.Then,(9)can be rearrangedasΔV y|D T=low=−t1+t2R p1C p1V err−V y,min−ΔV y|D T=low2.(10)When DT is high(zero inductor current),V x is0V and V y ischarged as much asΔV y|D T=high=t1+t2+t3t1+t2dV y=V err t3R p1C p1.(11)Since the net change of V y during one period T should be zeroin the steady stateΔV y=ΔV y|D T=low=ΔV y|D T=high(12)andV err=t1+t2TV y,min+ΔV y2.(13)The average value of V y can be calculated asV y,avg=V y,min+12ΔV y(14)and from(13)V y,avg=Tt1+t2V err.(15)For further suppression of the ripple in V y,additional low-passfilter,composed of R p2and C p2,is used,and the outputV tO Nof the low-passfilter is equal to the average value of V yV tO N=T(t1+t2)V err.(16)Fig.6.Current generator for I 1and I 2of the resistor-free ZCD circuit shown in Fig.4(a).Fig.7.(a)V t O N processing circuit and (b)its timing diagram.If the slope of the ramp signal is S ,the high pulsewidth t 1of Φ1is V t O N /S and the average input current isI in ,avg =V err2LS×V in(17)that is proportional to the input line voltage.Therefore,we can achieve good PF both in CRM and DCM.D.Clock and Ramp GeneratorThe clock and ramp generator shown in Fig.8(a)is used for PWM (PWM)control.The current through M 2charges the capacitor C t and when V G 4becomes high ,the transistor M 4turns on and discharges the capacitor C t .The ON-resistanceFig.8.(a)Clock and ramp generator and its timing diagram in (b)DCM and (c)CRM.Fig.9.Microphotograph of the PFC circuit.of the transistor M4is designed to be small enough to fully discharge the capacitor C t.In order to support both DCM and CRM,the ZCD signal DT is AND-gated with the SR-latch output Q latch.If the inductor current becomes zero(DT=high)before the ramp signal V ramp reaches V H,as shown in Fig.8(b),the clock signal CLK hasfixed frequency determined as V ref/V H C t R t and the PFC operates in DCM.In Fig.8(c),the inductor current becomes zero(DT= high)after the ramp signal V ramp becomes larger than V H. Then,the clock signal CLK is synchronized to DT and the PFC operates in CRM.It should be noted,as shown in Fig.8(b)and (c),that pulse DT always occurs before the CLK pulse.Due to use of the delay line D T in Fig.8(a)whose nominal delay is 100ns,the interval from the DT pulse to the next switching cycle is100ns when the PFC operates in CRM.By adding a capacitor across the power switch M N in Fig.2, the resonant frequency at the drain node of M N can be adjusted; therefore,the next switching cycle begins when the drain node voltage is zero,achieving valley switching.IV.E XPERIMENTAL R ESULTSThe PFC circuit has been implemented in a0.35-μm BCDMOS process and its microphotograph is shown in Fig.9. The area of the whole chip is2.03mm2.The PFC circuit is designed so that it can select one between the conventional ZCD with a sensing resistor and the proposed resistor-free ZCD.The conventional ZCD with a sensing resistor includesthe V tO N processing circuit as well,and its sensing resistor is0.1Ω.For performance comparison with the conventional ZCD scheme using an auxiliary transformer,the commercial PFC controller IC,FAN7530,is used to implement a PFC circuit, while the same power stage is utilized as for the proposed ZCD scheme[6].The PFC circuit provides390-V dc output from ac input line voltage of85–267V rms.The maximum outputcurrent Fig.10.Measured PF when the input line voltage is(a)100V rm s, (b)150V rm s,(c)200V rm s,and(d)230V rm s.is500mA,while6mA is dissipated internally for the operation of the PFC controller.In Fig.10,the measured PF is shown for the input line voltage of100,150,200,and230V rms.As can be seen in thefigure,the proposed resistor-free ZCD can improve PF by up to9%from the one using a sensing paring the ZCD with an auxiliary transformer,the proposed resistor-free ZCD shows similar or better PF.The performance of the implemented PFC circuit employing the proposed resistor-free ZCD scheme is summarized in Table I.TABLE IP ERFORMANCE SUMMARYV .C ONCLUSIONThe inductor current of active PFC circuit is monitored by the resistor-free ZCD.The resistor-free ZCD requires only one off-chip capacitor,and therefore,can provide much smaller form factor than the conventional ZCD schemes.The PFC circuit employing the proposed resistor-free ZCD is implemented in a 0.35-μm BCDMOS process and PF is improved up to 9%from the one employing the conventional ZCD.The proposed resistor-free ZCD scheme can be applied to any type of switch-mode dc–dc power converter.A CKNOWLEDGMENTThe authors would like to thank Prof.J.Choi and Prof.K.-C.Kim of University of Seoul,Korea and Prof.K.-Y .Lee of Konkuk University,Seoul for their help during this study.The CAD tools were provided by the IC Design Education Center (IDEC).R EFERENCES[1]Power Factor Correction Basics,Application Note 42047,Fairchild Semi-conductor,South Portland,ME,2004.[2]Power Factor Correction Handbook,ON Semiconductor,Phoenix,AZ,Sep.2007.[3]R.W.Erickson and D.Maksimovic,Fundamental of Power Electronics ,2nd ed.Boston,MA:Kluwer,2001,pp.609–630.[4]L.Huber,B.T.Irving,and M.M.Jovanovic,“Effect of valley switch-ing and switching-frequency limitation on line-current distortions of DCM/CCM boundary boost PFC converters,”IEEE Trans.Power Elec-tron.,vol.24,no.2,pp.339–347,Feb.2009.[5]Data Sheet of NCP 1605,ON Semiconductor,Phoenix,AZ,2009.[6]Data Sheet of FAN 7530,Fairchild Semiconductor,South Portland,ME,Apr.2006.[7]H.-P.Le,C.-S.Chae,M.-C.Lee,S.-W.Wang,S.-I.Kim,and G.-H.Cho,“Integrated zero-inductor-current detection circuit for step-up DC-DC converters,”IET Electron.Lett.,vol.42,no.16,pp.943–944,Aug.2006.[8]S.Sivakumar,K.Natarajan,and R.Gudelewicz,“Control of power factorcorrecting boost converter without instantaneous measurement of input current,”IEEE Trans.Power Electron.,vol.10,no.4,pp.435–445,Jul.1995.[9]S.Bhowmik,A.van Zyl,R.Spee,and J.H.R.Enslin,“Sensorless currentcontrol for active rectifiers,”IEEE Trans.Ind.Appl.,vol.33,no.3,pp.765–773,May/Jun.1997.[10] A.Garcia,A.de Castro,O.Garcia,and F.J.Azcondo,“Pre-Calculatedduty cycle control implemented in FPGA for power factor correction,”in Proc.35th Annu.Conf.IEEE Ind.Electron.(IECON’2009),pp.2955–2960.[11] D.C.Lee and D.S.Lim,“AC voltage and current sensorless control ofthree-phase PWM rectifiers,”IEEE Trans.Power Electron.,vol.17,no.6,pp.883–890,Nov.2002.[12]J.Sun and M.Chen,“Nonlinear average current control using partialcurrent measurement,”IEEE Trans.Power Electron.,vol.23,no.4,pp.1641–1648,Jul.2008.[13]T.Ohnishi and M.Hojo,“DC voltage sensorless single-phase PFC con-verter,”IEEE Trans.Power Electron.,vol.19,no.2,pp.404–410,Mar.2004.[14]T.Noguchi,H.Tomiki,S.Kondo,and I.Takahashi,“Direct power controlof PWM converter without power-source voltage sensors,”IEEE Trans.Ind.Appl.,vol.34,no.3,pp.473–479,May/Jun.1998.[15] D.Y .Qiu,S.C.Yip,H.S.H.Chung,and S.Y .Ron Hui,“Single currentsensor control for single-phase active power factor correction,”IEEE Trans.Power Electron.,vol.17,no.5,pp.623–632,Sep.2002.[16]S.Chae,B.Hyun,P.Agarwal,W Kim,and B.Cho,“Digital predictivefeed-forward controller for a DC-DC converter in plasma display panel,”IEEE Trans.Power Electron.,vol.23,no.2,pp.627–634,Mar.2008.[17]O.Trescases,G.Wei,A.Prodic,and W.T.Ng,“Predictive efficiencyoptimization for DC-DC converters with highly dynamic digital loads,”IEEE Trans.Power Electron.,vol.23,no.4,pp.1859–1869,Jul.2008.[18]H.Chen,“Duty phase control for single-phase boost-type SMR,”IEEETrans.Power Electron.,vol.23,no.4,pp.1927–1934,Jul.2008.Yong-Seong Roh received the B.S.(with the highest honors)degree in electrical and computer engineer-ing,in 2007,from Hanyang University,Seoul,Korea,where he is currently working toward the Ph.D.degree.His current research interests include power-management ICdesign.Young-Jin Moon received the B.S.degree in electri-cal and computer engineering,in 2008,from Hanyang University,Seoul,Korea,where he is currently work-ing toward the Ph.D.degree.His current research interests include power-management IC design.Jung-Chul Gong received the B.S.degree in elec-tronics from Kwangwoon University,Seoul,Korea, in2000,and is currently working toward the M.S. degree in electrical and computer engineering from Hanyang University,Seoul.He joined Samsung Electro-Mechanics,Suwon, Korea,in2000,where he is currently a Senior De-sign Engineer.His research interests include power-management ICdesign.Changsik Yoo(S’92–M’00)received the B.S.(withthe highest honors),M.S.and Ph.D.degrees in elec-tronics engineering from Seoul National University,Seoul,Korea,in1992,1994,and1998,respectively.From1998to1999,he was a Member of Re-search Staff at Integrated Systems Laboratory(IIS),Swiss Federal Institute of Technology(ETH),Zurich,Switzerland,where he was involved in the researchon CMOS RF circuits.From1999to2002,he was atSamsung Electronics,Hwasung,Korea.Since2002,he has been an Associate Professor at Hanyang Uni-versity,Seoul.His research interests include CMOS RF transceiver design, mixed-mode CMOS circuit design,high-speed interface circuit design,and power-management IC design.Dr.Yoo is the winner or co-winner of several technical awards including the Samsung Best Paper Bronze Award in2006International SoC Design Confer-ence,the Silver Award in2006IDEC Chip Design Contest,the Best Paper Award in2006Silicon RF IC Workshop,and the Golden Prize for research achievement in the next-generation DRAM design from Samsung Electronics in2002.He is a member of the technical committee of IEEE International Solid-State Circuits Conference(ISSCC),the Very Large Scale Integration(VLSI)Circuits Sympo-sium(SOVC),and the European Solid-State Circuits Conference(ESSCIRC).。