时序及面积约束

Agenda: Day 2
DAY 2
Unit 5 6 7 8 9 Topic Timing and Area Environmental Attributes Time and Load Budgeting Timing Analysis DC Tcl - Introduction Lab
5-1
Timing and Area
5-9
Method: 1. Define the clocks 2. Define the I/O timing relative to the clocks
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Paths N & S are still unconstrained!
Timing and Area
EXTERNAL CIRCUIT
5-13
TO_BE_SYNTHESIZED
Clk (50 MHz)
CLK-OUTPUT 7.4 ns (worst)
A
N
D Q
Clk
U1
create_clock -period 20 [get_ports Clk] set_dont_touch_network [get_clocks Clk] set_input_delay -max 7.4 -clock Clk [get_ports A]
Launch Edge Capture Edge
Clk B
Valid new data
TClk-q + TS TT + TSETUP
(Output Delay)
Timing and Area
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Constraining Output Paths in DC
TO_BE_SYNTHESIZED
D Q FF1 QB Clk M N D Q FF2 QB X D Q FF3 QB S T D Q FF4 QB
5-6
What information must you provide to constrain all the register-to-register paths in your design? Does the duty cycle of your clock matter?
Launch Edge Capture Edge
You specify how much time is used by external logic... DC calculates how much time is left for the internal logic
4

delay of time left for external internal logic logic
0.0 10.0 20.0
Clk A
7.4
Constraint of YOUR input path
Timing and Area
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set_input_delay: Effect on Input Paths
Timing and Area
Synopsys 31833-000-S16 Chip Synthesis Workshop
Timing Goals: Synchronous Designs, I/O
Path X constrained by create_clock
TO_BE_SYNTHESIZED D Q FF1 QB Clk M N D Q FF2 X D Q FF3 S T D Q FF4 QB
U3 Launches Data
Clk
5-14
External Flip-Flop captures data
TO_BE_SYNTHESIZED
U3 D Q
External Logic B T D Q
S
TClk-q
Ts
TT
TSETUP
What information must you provide to constrain the output paths?
If U1 has a 1 ns setup requirement: What is the maximum delay for TN?
Timing and Area
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Constraining Output Paths of a Design
Timing and Area
Synopsys 31833-000-S16 Chip Synthesis Workshop
set_input_delay: Exercise
EXTERNAL CIRCUIT TO_BE_SYNTHESIZED A
5-12
Clock (50 MHz)
CLK-OUTPUT 7.4 ns (worst)
No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Analysis
No
Met Constraints? Yes
Timing and Area
Synopsys 31833-000-S16
Chip Synthesis Workshop
5-15
dc_shell-t> set_output_delay -max 5.4 -clock Clk
[get_port B]
The set_output_delay command constrains output paths
You specify how much time is needed by external logic... DC calculates how much time is left for internal logic
Synopsys 31833-000-S16 Chip Synthesis Workshop
Unit Objectives
After completing this unit, you should be able to: Constrain a design for area Constrain a design for timing
TClk-q
TM
TN
TSETUP
What information must you provide to constrain the input paths?
Clk A
(TClk-q + TM)
(Input Delay)
Timing and Area
Synopsys 31833-000-S16 Chip Synthesis Workshop
Valid new data
(TN + TSETUP)
Constraining Input Paths in DC
5-11
dc_shell-t> set_input_delay -max 4 -clock Clk [get_ports A]
The set_input_delay command constrains input paths
5-4
Units are those of target library, defined by the vendor
2-input-NAND-gate transistors square mils
Timing and Area
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Specifying an Area Goal
dc_shell-t> dc_shell-t> dc_shell-t> dc_shell-t> current_design current_design PRGRM_CNT_TOP PRGRM_CNT_TOP set_max_area set_max_area 100 100
Example: Clock Period = 10ns Setup = 1ns
What is the max delay requirements for the register-to-register paths in the block TO_BE_SYNTHESIZED?
Timing and Area
5-2
Timing and Area
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RTL Block Synthesis
Rewrite
5-3
Write RTL HDL Code
No
Simulate OK? Yes
Yes
Major Violations?
TO_BE_SYNTHESIZED
5-7
Clk
N
D Q FF2
X
Period
D Q FF3
S
Clk
1 Clock Cycle
Timing and Area
Synopsys 31833-000-S16 Chip Synthesis Workshop
Defining a Clock in Design Compiler
all input logic paths the internal (register to register) paths, and all output paths
Timing and Area