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REALTEK RTL8208DESIGN AND LAYOUT GUIDE1. IntroductionThis document provides detailed design and layout guidelines to achieve the best performance for implementing a 2-layer board design with the RTL8208 Octal PHY.The RTL8208 is the smallest Oct-PHY in the industry, having the smallest foot-print. To benefit BOM costs, one external PNP transistor is used to generate a 2.5V power source. Care needs to be taken, however, to prevent signals from cross-talk and interference due to the small package, and most importantly, to support a stable 2.5V power plane which determines the performance of data recovery and transmit jitter.RMII Signal Diagram RMII Signal Diagram50MHz Oscillator Solution 25MHz Crystal Solution2. General Design and Layout GuideIn order to achieve maximum performance with the RTL8208, good design attention is required throughout the design and layout process. The following recommendations will help implement a high performance system.2.1 General Guidelines• Create a good power source, minimizing noise from switching power supply circuits (<50mV).• Verify the quality of the components, such as clock source and transformer, to meet the application requirements. • Keep power and ground noise levels below 50mV.• Use bulk capacitors (4.7uF-10uF) between the power and ground planes.•Use 0.1uF decoupling capacitors to reduce high-frequency noise on the power and ground planes. • Keep decoupling capacitors as close as possible to the RTL8208. • Provide termination on all high-speed switching signals.2.2 Differential Signal Layout Guidelines• Keep differential pairs as close as possible and route both traces as identically as possible, meaning width, length and location.• Avoid vias and layer changes if possible.• Keep the transmit and receive pairs as far from each other as possible. Run them orthogonally or separated by a ground plane if possible.• Avoid right-angle signal tracesBbad !Bgood !2.3 Clock Circuit• The clock should be 25M/50MHz/125MHz 100ppm with jitter less than 0.5ns.• The length of the clock path to the RTL8208 should be equal to the length of the clock path to the MAC. • If possible, surround the clock by ground traces to minimize high-frequency emissions.• Keep the MDC trace away from the crystal X1 input path, to avoid unnecessary interference. This is especially important while using a crystal solution.• Keep signal traces from running parallel to clock traces. Traces parallel to clock traces are a worst case design and will pick up interference from the clock.2.4 2.5V Power• Do not connect a bead directly between the collector of the PNP transistor and VDDAL. Use of a bead will affect the stability of the 2.5V power significantly.• Use a bulk of capacitor (4.7uF-10uF) between the collector of the PNP transistor and the ground plane.• Do not use one PNP transistor for more than one RTL8208 chip, even if the rating is enough. Use one transistor for each RTL8208.8 2 0 88 2 0 82.5 Power Planes• Divide the power plane into 2.5V digital, 2.5V analog and 3.3V analog if you design a 4-layer PCB layout.• It is recommended to combine both 2.5V digital and analog power as a connected power-ring when designing a 2-layer PCB layout.• Use 0.1µF decoupling capacitors and bulk capacitors between each power plane and ground plane.2.6 Ground Planes• Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board.• Place a moat (gap) between the system ground and chassis ground.• Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.3. Transformer Options• The magnetics support AutoMDIX and with 1:1 turn ratio on both the transmit and receive paths are valid for RTL8208. There are many venders improving their magnetics design to meet this requirement, and several are listed below.Vendor Model Vendor Model40ST1041AXPulse H1164 BothHandMagnetic 1 ML164 GTS FC-638L• The center-tap of the primary side of the transformer should not be connected to ground with capacitors, because of the RTL8208’s special design.4. 2.5V Power GenerationThe RTL8208 uses a PNP transistor to generate 2.5V from the 3.3V power supply. This 2.5V provides for digital core and analog receive circuits. When designs require more than one RTL8208 chip (a system greater than 8 ports), do not use one PNP transistor for all of the RTL8208 chips even if the rating is sufficient. Use one PNP transistor for each RTL8208 chip.VDDAH: 3.3VVDDAL: 2.5V2SB1197K47uFUsing a PNP Transistor to Produce 2.5VDo not connect any beads directly between the collector of the PNP transistor and VDDAL. This will affect the stability of the 2.5V power significantly if a bead is used in this manner.2.5V power withoutbeadPNP 2SB1197KThe power transistor is a 2SB1197K, and follows the following specifications. Absolute maximum ratings (Ta=25°C)Parameter Symbol Limits Unit Collector-base voltage VCBO -40 V Collector-emitter voltage VCEO -32 V Emitter-base voltage VEBO -5 V Collector current IC -0.8 A(DC) Collector power dissipation PC 0.2 W Junction temperature Tj 150 °C Storage temperature Tstg -55~+150 °CFor more information, refer to 5. Layout Guidelines for 2-layer BoardSome experimentation can determine better layout guidelines to achieve good performance according to the characteristics of the RTL8208. The illustrations in this section describe some critical points on layout to improve chip and thus system performances. This section includes a feedback control signal, VCTRL, and MDC vs. X1 signal, and power vs. ground descriptions.5.1 VCTRL SignalVCTRL controls the current flow to stabilize 2.5V power. Any beads between the PNP collector and the RTL8208 will affect the internal feedback circuit adjusting current flowing through the VCTRL trace.Better designs will provide an uninterrupted signal trace for the VCTRL signal, with no vias between the PNP transistor and the RTL8208. Vias tend to appear and act like a choke to the current.VCTRL With Two Vias(worst case layout)5.2 MDC and X1 LayoutA great deal of transmit jitter will be created if the MDC interferes with the X1 (crystal) signal. This interference and jitter will cause CRC errors on the link partner receive path. It is strongly recommended to keep the MDC and X1 signal traces as far from each other as possible, and to keep the traces in a non-parallel configuration to avoid interference. This is especially important in a 2-layer board design. Removing the interfering source on clock will gain significant improvement in Tx jitter.Avoid Running Traces Parallel to the X1 SignalKeeping the MDC and X1 Traces Separated and Divergent5.3Power and GroundIt is not easy to implement a dual-voltage layout in a 2-layer board design. For the RTL8208, keeping a stable 2.5V power source is more important than the 3.3V power source when problems occur. However, a continuous and solid ground plane is also important to reduce power bouncing and thus improve signal integrity. Bulk capacitors for power traces and decoupling capacitors for each power pin of the RTL8208 are necessary. The decoupling capacitors should be as close as possible to the RTL8208 chip.5.3.1 2.5V PowerThe 2.5V power source determines data recovery performance and transmit jitter. As high as a 2ns transmit jitter may cause CRC errors on the link partner. For 2-layer board designs, a power-ring around the RTL8208 is used instead of a power plane, which is, in turn, used for a ground plane to reduce possible EMI and power bouncing. 47µF bulk capacitors are placed on the corners of this ring to support large current. 0.1µF decoupling capacitors are placed around, and as close as possible to the RTL8208. The 2.5V power-ring is on the top layer of the PCB as illustrated below. There are no beads on the ring to separate digital and analog power. Also, there are no beads between the PNP transistor and the power-ring.2.5V Power-ring with Two 47uF and 0.1uF Capacitors5.3.2 3.3V powerThe 3.3V power source determines the transmit waveform. This power source contributes less impact on the receiver of the link partner compared to transmit jitter, which is dominated by the 2.5V power.The illustration below shows the 3.3V power trace on the bottom side of the board, with bulk and decoupling capacitors.3.3V Power Trace5.3.3 GroundA continuous solid ground plane reduces EMI and power bouncing issues and creates better signal integrity and chip performance. As illustrated below, the ground plane lies beneath the RTL8208 on both the top and bottom layers of the PCB. Also, a ground ring around the RTL8208 is used to supply the decoupling capacitors with a current return path for both 2.5V and 3.3V power.Chip Ground Plane and Ground Ring5.4 REFCLKWhen RTL8208 uses 25MHz crystal or 25MHz OSC as clock source at pin 114 and works in 10Base-T mode, depending on loading and power on timing, some CRC/alignment error packets may be observed due to the timing skew. Descriptions:Systems designed based on 50MHz oscillator are immune to this problem.Since the problem is related to the internal timing when RTL8208 is power on. This problem can be reproduced and observed much easier by power-off/on the system several times. And then start packet transmission after power on each time to take sample. The setting on the packet generator is basically irrelevant. However, continuous stream of packet transmission may increase the rate of error packet observed.Analysis of the captured error packets consistently shows that the last bit of each error packet is corrupted by RTL8208. Further analysis shows that the REFCLK output from RTL8208 may determine whether the data transferred from the controller is correctly received by RTL8208.Workaround:To remove this problem for current version of RTL8208, an additional 15pF capacitor placed on the trace to REFCLK pin is required.1.The 15pF capacitor should be placed on the side closed to RTL8208, rather than controller/MAC side. And it musthave the precision of at least 10%. (Note: Maximum capacitance should be limited to 18pF. )2.It is recommended that damping resistor on REFCLK pin to be removed or replaced with 0-ohm resistor. Thedamping resistor may cause unnecessary setup/hold time issues depending on trace length of REFCLK output from RTL8208.Please find a simplified schematic below,Realtek Semiconductor Corp.Headquarters1F, No. 2, Industry East Road IX, Science-basedIndustrial Park, Hsinchu, 300, Taiwan, R.O.C.Tel : 886-3-5780211 Fax : 886-3-5776047WWW: 。