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包络提取在冲击损伤成像方法中的应用

包络提取在冲击损伤成像方法中的应用

包络提取在冲击损伤成像方法中的应用
李明;肖迎春;韩晖
【期刊名称】《振动、测试与诊断》
【年(卷),期】2014(000)003
【摘要】为了提高复合材料冲击损伤的监测效率和定位精度,提出了一种基于希尔伯特-黄变换的损伤成像方法。

利用希尔伯特-黄变换对信号包络进行提取后再成像,可以有效简化原始信号,同时提高模式走时提取精度和损伤监测效率。

试验表明:在对复合材料层合板的冲击损伤进行成像的过程中,利用时域信号包络进行损伤成像可以明显改善成像效果,而不改变损伤定位精度;相对于短时傅里叶变换,希尔伯特-黄变换在信号包络提取和成像效果方面更具有优势。

【总页数】5页(P503-507)
【作者】李明;肖迎春;韩晖
【作者单位】中国飞机强度研究所全尺寸飞机结构静力/疲劳航空科技重点实验室西安,710065;中国飞机强度研究所全尺寸飞机结构静力/疲劳航空科技重点实验室西安,710065;中国飞机强度研究所全尺寸飞机结构静力/疲劳航空科技重点实验室西安,710065
【正文语种】中文
【中图分类】TB302.5;TN911.72
【相关文献】
1.ISAR成像中包络对齐方法研究
2.矿井反射槽波包络叠加成像方法及其应用
3.窄带包络相关在舰船辐射噪声包络谱提取中的应用研究
4.复合材料冲击损伤监测的概率成像方法
5.应用EMD和倒包络谱分析的故障提取方法
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Tris缓冲体系下NiTi表面制备聚多巴胺薄膜提高其耐蚀性能

Tris缓冲体系下NiTi表面制备聚多巴胺薄膜提高其耐蚀性能

作者: 元博[1];宋高臣[1];李莹[1];孙展鹏[1];尹永奎[1]
作者机构: [1]牡丹江医学院,黑龙江牡丹江157011
出版物刊名: 化工管理
页码: 91-92页
年卷期: 2019年 第4期
主题词: Tris缓冲体系;聚多巴胺;耐腐蚀
摘要:Tris缓冲体系下,通过在NiTi表面包裹聚多巴胺薄膜来提高其耐腐蚀性能。

研究分别在10mMTris pH=8.5和50mMTris p H=8.5条件下,改变多巴胺的初始浓度,考察了成膜后的NiTi 耐蚀性能。

结果表明,10mM的Tris体系下,聚多巴胺修饰NiTi的耐蚀性能并不是随着多巴胺的浓度增加而增强;相比之下,50mM的Tris体系下,聚多巴胺修饰NiTi的耐腐蚀性能随着多巴胺浓度的增加而增强。

自适应谱线增强器在生物雷达中的应用

自适应谱线增强器在生物雷达中的应用
自适 应 谱 线 增 强器 在 生物 雷达 中 的应 用 陈 铁 军 , 等
白适 应 谱 线 增 强器 在 生 物 雷 达 中的应 用
Ap l a i ft e Ad p ie S e ta n a c n Bi a a pi t c on o h a t p c r lE h n eri or d r v
能力 , 其原理如 图 1 所示 。
因此 , 对采集信号处 理 的效果 直接决 定 了生命 探测仪
性能的优劣。

为解决这一 问题 , 基于变步长 自适应算法的各种信 号处理的方法不断 涌现 。传统 的变步长 自适应 算 一 法均需要预先给定参考信 号。但在救援环境 复杂以及 废墟下存活人体的个体差异 , 在生物雷达信号处理 中很
难找到一个 理想 的信号作 为参考信号。为解决 这一 问
图 1 自 适 应 谙 线 增 强 器 原 理 图
F g 1 T e p i cp eo d p ie s e t l n a c r i . h r i l fa a t p cr h n e n v ae
Ke wod :Boa a E rrc agn ae y r s ird r r h n igrt Ad pieset leh n e n L at a qae L ) Ma a R b s es o a t pcr na c met e s mensu r ( MS v a t b o ut s l n
自适应谱线增强器最早 是 由 Wir do w等 人于 17 95 年提 出的。 目前 , 基于 自适 应线性 组合器 的 自适 应谱
线增强器 已广泛应用 于频谱估算 、 谱线估 计 以及 窄带 检测等领域 。在窄带信 号加上 宽带信号 的情况 下 , 白 适应谱线增强方法无 需独立 的参考 信号就 能将信号分

大脑视网膜调制传递函数曲线特性分析

大脑视网膜调制传递函数曲线特性分析

大脑视网膜调制传递函数曲线特性分析
曾碧新;陈式苏
【期刊名称】《生物医学工程学杂志》
【年(卷),期】2001(18)3
【摘要】探索视网膜对比敏感传递函数曲线特性 ,寻找表征疾病特征和鉴别诊断各种眼疾的方法。

用最小二乘法对 MTF曲线 (对数坐标下 )进行二、三次项拟合 ,求
得拟合参数。

对正常眼和一些眼疾的 MTF数据进行二、三次项拟合 ,得出回归曲
线和反映回归曲线特性的参数。

对于对称型MTF曲线(对数坐标下)用k1 、k2 、k3及偏差表征每一种疾病并鉴别之 ,对于非对称型 MTF(对数坐标下 )曲线增加一
个非对称参数 k4。

【总页数】3页(P400-402)
【关键词】MTF;拟合曲线;特异性;视网膜;调制传递函数
【作者】曾碧新;陈式苏
【作者单位】温州医学院物理教研室
【正文语种】中文
【中图分类】R774.1
【相关文献】
1.视网膜大脑系统的时空调制传递函数测量装置 [J], 陈式苏;金成鹏
2.调制传递函数联合视觉电生理对糖尿病视网膜病变早期诊断的意义 [J], 黄小明;李英姿;王勤美
3.调制传递函数联合视觉电生理对糖尿病视网膜病变早期诊断的意义 [J], 黄小明;李英姿;王勤美
4.全息光栅法视网膜调制传递函数测定装置的实验研究 [J], 金晨晖;滕坚;杨伟斌
5.矩形光栅法视网膜调制传递函数测定技术的研究 [J], 金晨晖;金成鹏;刘晓玲;陶育华
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干扰素刺激基因15抗病毒感染的分子机制

干扰素刺激基因15抗病毒感染的分子机制

·综述·Chinese Journal of Animal Infectious Diseases中国动物传染病学报摘 要:干扰素刺激基因15(ISG15)是由病原微生物或干扰素诱导产生的一种大小为15 kDa 的泛素样蛋白。

在干扰素诱导的数百个干扰素刺激基因中,ISG15是诱导最强烈、最快的ISG 蛋白之一。

研究表明,ISG15对多种病毒具有抗病毒作用。

此外,ISG15在调节宿主损伤、DNA 修复,调节信号通路及抗原递呈中也发挥着重要的作用。

文章介绍了ISG15的概况,并阐述了近年来ISG15在抗病毒、免疫调节和调节宿主信号通路过程中的作用。

关键词:干扰素刺激基因15;抗病毒作用;免疫调节中图分类号:S852.4 文献标志码:A 文章编号:1674-6422(2023)06-0170-07Molecular Mechanism of Interferon-Stimulated Gene 15 Antiviral InfectionTANG Jingyu 1, DU Hanyu 1,2, JIA Nannan 1, TANG Aoxing 1, LIU Chuncao 1, ZHU Jie 1, MENGChunchun 1, LI Chuanfeng 1, LIU Guangqing 1(1. Shanghai V eterinary Research Institute, CAAS, Shanghai 200241, China; 2. Xinjiang Agricultural University, Xinjiang 830052, China)收稿日期:2021-11-02作者简介:国家重点研发计划项目(2016YFD0500108);中国农业科学院创新工程项目作者简介:唐井玉,女,博士研究生,预防兽医学专业通信作者:刘光清,E-mail:**************.cn干扰素刺激基因15抗病毒感染的分子机制唐井玉1,杜汉宇1,2,贾楠楠1,汤傲星1,刘春草1,朱 杰1,孟春春1,李传峰1,刘光清1(1.中国农业科学院上海兽医研究所 小动物传染病预防与控制创新团队,上海200241;2.新疆农业大学,乌鲁木齐830052)2023,31(6):170-176Abstract: Interferon-stimulated gene 15 (ISG15) is a ubiquitin-like protein of approximately 15 kDa induced by pathogenic microorganisms or interferons. Among the hundreds of interferon-stimulated genes induced by interferons, ISG15 is one of the most strongly and fastest induced ISG proteins. Studies have shown that ISG15 has antiviral effects against a variety of viruses. In addition, ISG15 plays an important role in regulating host damage, DNA repair, and regulating signaling pathways and antigen delivery. The article presented an overview of ISG15 and described the role of ISG15 in the process of antiviral, immunomodulation and regulation of host signaling pathways in recent years.Key words: Interferon-stimulated gene 15; antiviral infection; immunomodulation先天性免疫应答是抵抗入侵病原体的第一道防线,病原体可以通过宿主模式识别受体来感知。

突触蛋白在学习记忆过程中的作用

突触蛋白在学习记忆过程中的作用

突触蛋白在学习记忆过程中的作用
陈菁菁;印大中
【期刊名称】《生命的化学》
【年(卷),期】2006(26)4
【摘要】学习和记忆是脑的高级功能。

学习指人和动物获得外界知识的神经过程;记忆指将获得的知识储存和读出的神经过程。

突触蛋白(synapsin)是一种与突触结构和功能密切相关的膜蛋白,在突触的可塑性以及长时程增强(long-timepotentiation,LTP)中起着重要作用。

而突触可塑性是突触对内外环境变化作出反应的能力,是学习记忆的神经生物学基础。

LTP一直被认为是学习记忆的神经基础之一,是突触可塑性的功能指标,也是研究学习记忆的理想模型。

该文介绍突触蛋白在学习记忆过程中的作用及机制、突触蛋白在学习记忆研究中的应用。

【总页数】3页(P334-336)
【关键词】学习记忆;突触蛋白;突触可塑性;长时程增强
【作者】陈菁菁;印大中
【作者单位】湖南师范大学生命科学学院衰老生化实验室
【正文语种】中文
【中图分类】Q189;Q73
【相关文献】
1.神经肽在学习记忆过程中的作用 [J], 郑元林;吴馥梅
2.PKA-CREB信号通路在大鼠纹状体边缘区及海马空间学习记忆过程中的作用 [J],
常铉;舒斯云;包新民;江刚
3.内源性noggin对学习记忆过程中海马神经发生的调控作用 [J], 范晓棠;徐海伟;罗峻;蔡文琴
4.记忆力在英语学习过程中的作用探究 [J], 杨上杭
5.肉苁蓉多糖对衰老过程中学习记忆影响的体内外作用 [J], 邢海燕;赵璐璐;王胜男;李刚
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神经科学中的突触可塑性从长时程增强到抑制

神经科学中的突触可塑性从长时程增强到抑制突触可塑性是神经科学中一个重要的研究领域,突触可塑性是指神经元之间突触连接的强度和效能可以通过学习和经验调整的能力。

这一现象在突触长时程增强(LTP)和抑制(LTD)中得到了广泛的研究和讨论。

本文将从LTP的机制和调控、LTD的机制和调控、LTP和LTD之间的转换等方面进行论述。

一、LTP的机制和调控LTP是突触可塑性中最为经典的一种形式,它被广泛应用于神经网络的学习和记忆过程中。

LTP的机制主要通过神经递质的释放和受体的激活来实现。

当突触前神经元对突触后神经元产生频繁的刺激时,突触后神经元的NMDA受体将被激活,导致钙离子的内流。

这些钙离子的内流会引起突触中多种信号传递分子的活化,最终导致突触连接的强化。

LTP的调控涉及多个因素,包括突触前和突触后神经元的活动、突触中的信号调节分子以及神经递质的调节等。

例如,突触前神经元的频率和模式可以对LTP的发生和持续产生影响。

同时,突触中的信号调节分子,如cAMP、蛋白激酶和突触后神经元的二磷酸腺苷等也能够对LTP的表现产生影响。

二、LTD的机制和调控LTD是LTP的对应形式,它可以使突触连接的强度降低,从而在神经网络的学习和记忆过程中起到重要的作用。

LTD的机制主要通过突触中受体的活化和信号传导通路的调节来实现。

与LTP相比,LTD的机制相对复杂,涉及到多个分子和信号通路的调节。

LTD的调控与LTP类似,它同样受到突触前和突触后神经元的活动模式、突触中的信号调节分子以及神经递质的影响。

例如,突触前神经元的低频刺激和突触后神经元的高频刺激可以引起LTD的发生。

此外,突触中的信号调节分子,如cAMP、蛋白激酶和蛋白酶等也能够对LTD的发生和持续产生影响。

三、LTP和LTD之间的转换LTP和LTD之间的转换是神经科学中一个备受关注的课题。

不同的刺激模式和神经递质的变化可以导致LTP和LTD之间的切换。

例如,较强的刺激模式和突触后神经元的活动会促使LTP的发生,而较弱的刺激模式和突触前神经元的活动会促使LTD的发生。

改进的LMS算法自适应滤波器的DSP实现

改进的LMS算法自适应滤波器的DSP实现
赵巧红;曾照福
【期刊名称】《微型机与应用》
【年(卷),期】2009(028)009
【摘要】分析了变步长LMS算法自适应滤波器基本原理,使用MATLAB对其进行仿真,并应用SZ-EPP5402评估板进行了DSP实现,结果表明,变步长LMS算法能够克服固定步长LMS算法的矛盾,具有较快收敛速度与较小稳态误差.
【总页数】4页(P67-69,72)
【作者】赵巧红;曾照福
【作者单位】湖南科技大学,信息与电气工程学院,湖南,湘潭,411201;湖南科技大学,信息与电气工程学院,湖南,湘潭,411201
【正文语种】中文
【中图分类】TP911.72
【相关文献】
1.基于改进NLMS算法的回声消除器研究与DSP实现 [J], 张艳凤;张振川
2.一种改进的变步长LMS算法及其DSP实现 [J], 王俊峰
3.自适应滤波器LMS算法的DSP实现 [J], 马俊;段新文;赵建飞
4.用FPGA和改进的LMS算法实现自适应滤波器 [J], 汤书森;苟煜春;张文强;詹佳伟
5.驾驶室主动降噪的改进FxLMS算法及DSP实现 [J], 龚孝平;郭勇;刘强;朱再胜
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中质协六西格玛黑带2015年真题

中国质量协会2015年注册黑带考试题一、单项选择题(84道题,84分)1.试验设计是质量改进的有效工具,最早基于农业试验提出方差分析与试验设计理论的是:A.休哈特(W.A.Shewhart)B.道奇和罗米格(H.F.Dodge and H.G.Romig)C.费希尔(R.A.Fisher)D.戴明(R.E.Deming)2.在六西格玛推进过程中,黑带的主要角色是:A.带领团队使用六西格玛方法完成项目B.合理分配资源C.确定公司发展战略D.核算六西格玛项目收益3.在对老产品改型的六西格玛设计(DMADV)项目中,测量阶段的主要工作是:A.测量产品新设计的关键质量特性(CTQ)B.基于关键质量特性(CTQ)确定测量对象C.识别顾客需求D.确定新过程能力4.SWOT分析是战略策划的基础性分析工具。

在使用SWOT分析为组织制定六西格玛推进战略时,以下哪项不.是.主要内容?A.分析组织能够成功推进六西格玛的有利条件B.分析组织推进六西格玛的必要性C.确定组织推进六西格玛的具体负责部门D.分析六西格玛推进方法的比较优势5.水平对比又称为标杆管理(benchmarking)。

以下关于水平对比的说法中,错误..的是:A.水平对比可用于发现改进机会B.水平对比可以用于确定六西格玛项目的目标C.不同类型的企业也可以进行水平对比D.标杆企业或产品的选择应该随机6.在评价六西格玛项目的收益时,若收益率为10%,净现值为零,说明该项目:A.投资回报率低于10% B.项目收益为零,经济上不可行C.每年的净现金流量为零D.投资回报率等于10%7.以下关于六西格玛项目目标的描述,符合SMART原则是:A.公司产品的毛利率要在未来实现翻一番B.公司产品的市场占有率要达到行业第一C.公司某产品的终检不良率要在5个月内从1%降低到0.3%D.公司要通过技术创新,在未来三年使产品的市场占有率有突破性提高8.某六西格玛项目的目标是缩短生产周期,该项目涉及生产、检测、工艺等部门。

MATLAB环境下的单神经元自适应实时控制系统

基金项目:国家自然科学基金(60274020,69974017);河北自然科学基金(602621);广西自然科学基金(0135065)收稿日期:2003-06-13 收修改稿日期:2004-02-10MAT LAB 环境下的单神经元自适应实时控制系统王俊国,王永骥,万淑芸(华中科技大学控制科学与工程系自动化研究所,湖北武汉 430074) 摘要:利用神经元模型和自学习功能构成自适应PI D 控制器,在Matlab 实时开发环境xPC T arget 下建立液位实时控制系统。

给出了单神经元自适应PI D 控制器的结构和控制算法,介绍了基于xPC T arget 的快速原型设计方法,即通过拖拉S imulink 模块搭建被控对象的实时原型,同时以神经元自适应PI D 控制器完成系统的实时控制。

为检验控制效果还采用了PI D 控制器进行液位实时控制。

最终结果表明:单神经元自适应控制能克服传统PI D 控制器不稳定的缺点,使系统具有较好的稳定性。

关键词:神经元;S imulink ;xPC T arget ;自适应控制中图分类号:TP273 文献标识码:A 文章编号:1002-1841(2004)04-0021-01R eal 2time Single N euron Adaptive Control System B ased on Matlab E nvironmentWANG Jun 2guo ,WANG Yong 2ji ,WAN Shu 2yun(Institute of Automation ,Department of C ontrol Science and Engineering ,Huazhong University of Science and T echnology ,Wuhan 430074,China )Abstract :Real 2time level process control system was devised on the basis of xPC T arget s oftware environment of Matlab.Meanwhile an adaptive PI D controller were designed by means of neuron m odel and self 2learning alg orithm.The architecture and alg orithm of the single neuron adaptive PI D controller were discussed.The rapid prototyping process which created block diagrams in S imulink using sim 2ple drag and drop operations was introduced in detail.The real 2time control system adopted adaptive PI D controller was created through S imulink m odel with xPC T arget.In order to verify the performance of tw o approaches ,the PI D alg orithm was als o used to control the lev 2el system.The results indicate that the proposed method can overcome the shortcoming of the traditional PI D controller and achieve satis 2factory stability.K ey Words :Neuron ;S imulink ;xPC T arget ;Adaptive C ontrol1 引言在工业控制中,传统的PI D 控制至今仍处于主导地位,其缺点主要是PI D 参数一般由人工整定,且一次性整定得到的PI D 参数很难保证其控制效果始终处于最佳状态[1]。

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March 2007 (vol. 8, no. 3), art. no. 0703-o30011541-4922 © 2007 IEEEPublished by the IEEE Computer SocietyRapid System PrototypingGaining Insight into Executable Models during Runtime: Architecture and MappingsPhilipp Graf and Klaus D. Müller-Glaser •University of KarlsruheAn extension to a seamless, model-based development approach provides an architecture for debugging models that execute on target systems or in dedicated rapid-prototyping environments.During development, the ever-increasing design complexity of embedded systems frequently comes into conflict with cost, time-to-market, and quality. This complexity results from increasing functionality, the expanding design space, the distribution of functionality to distributed control units, the optimization of power dissipation, and performance requirements. For example, as of today, a luxury car includes up to 80 electronic control units that communicate over various networks. An Airbus A380 contains more than 1,000 field-programmable gate arrays (FPGAs).As complexity increases, the development focus shifts from electronic and pure control-based systems toward software-based systems. The embedded-software development community is increasingly accepting the object-oriented paradigm, and a growing number of graphical tools for computer-aided systems and software engineering (CASE) support it. Relevant notations include the Unified Modeling Language (UML),1 statecharts,2 and signalflow-based modeling. Graphical approaches usually feature a higher level of abstraction, as putting platform-dependent nonbusiness logic into transformations such as the Object Management Groups’s (OMG) Model-Driven Architecture (MDA) suggests.3 Such approaches logically follow the progress from low-level assembly language programs to high-level languages to the object-oriented paradigm for specifying embedded software.Other than pure simulation approaches, only a few tools let you find errors in embedded software at the graphical-modeling level. When a code generator transforms a model into code, its structure will likely change dramatically. A simple Stateflow diagram consisting of just a few states generates several hundred lines of C code. Also, the developer didn’t write the code; it was generated, making a source-code-level view seem inappropriate while debugging. Insight into processing the model on a real target system or in the context of a processor-in-the-loop or hardware-in-the-loop simulation isn’t possible. If the system was heterogeneously developed using specialized development tools, finding errors in the complete system is possible only at the source-code level. So, the challenge is to construct a system that leverages the debugging of executable models at the model level and that allows debugging executable models across notation boundaries.Model-based development of software for embedded systemsHere, we briefly describe our development process for specifying software targeted at embedded systems according to different modeling domains and transforming it to an executable binary that’s appropriate for rapid prototyping. You can access a longer, more complete description of our approach and tool support elsewhere.4In our eyes, defining a complete, potentially complex design process for our approach would be too rigid. Nevertheless, the approach puts constraints on the development process, and you can incorporate those constraints in different process models.Figure 1 presents a basic top-down design flow. We used the software tool aquintos.GS (formerly GeneralStore), a commercially available research spin-off from our department, to realize and support our design process. It offers versioned model and user management, allowing concurrent engineering of large-scale heterogeneous models.Figure 1. Top-down design flow from requirements to executable.The design process starts from a textual specification document, which is the basis for the requirements specification phase that follows. From there, the system architect can extract a preliminary, roughly outlined class model. Subsequently, the architect divides the embedded system’s model into different domain submodels, each of which is a software component, a subsystem in the control domain, or a statechart in the time-discrete domain.Now, developers can use their CASE tool of choice in their preferred notation. The aquintos.GS integration platform automatically integrates them bidirectionally into a UML-metamodel-based top-level model. With respect to the runtime mapping concept we introduce later, it’s important to emphasize that we provide a complete structural transformation to and from the UML. So, for example, our database stores state diagrams modeled using Matlab Stateflow and based on the UML state diagram metamodel.You must link the various model parts so that they can communicate. You can do this by linking the system parts at the code level, but this approach is inflexible, error prone, and difficult to maintain. Alternatively, you can specify interfaces between the modeling domains at the model level in the overall UML system representation and transform them into a generatable class model before code generation.The aquintos.GS platform lets you partition the whole system into subsystems. So, we enable the use of different domain-specific code generators. Each code generator has benefits in specialized application fields. For control systems, there are commercial code generators such as Embedded Coder or MicroC. In the software domain, we provide a code generator as a plug-in to enable structural and behavioral code generation directly from a UML model.The generated source code is transformed to an executable binary during the last step. The developer can then deploy the executable file to the execution target, allowing validation of the model.Debugging and simulationDebugging and simulation focus on the same task during development: searching for and removing defects in a model that could lead to errors or even cause the whole system to fail. They do this in four phases: detecting, finding, analyzing, and eliminating defects. Although testing can detect errors or failures, finding and analyzing defects requires tool assistance that, in principle, both debugging and simulation approaches can provide.Whereas debugging requires code generation and execution on the target system or a rapid-prototyping device, simulation approaches interpret the model. However, this interpretation can include code generation—for example, to compile accelerated simulation kernels.5Simulation doesn’t require using the target system. Using a debugger implies that the model executes on a target system or a rapid prototyping device that is (or at least resembles) the target unit.Designing embedded software using models imposes additional constraints on a simulation approach. Generally, embedded software exists in the context of peripherals and the surrounding environment. For simulation, this means that you must implement actuators and sensors and simulate the environment. The semantic equivalence of the simulated peripherals to the real system, however, is problematic. The need to model and implement these along with the software adds complexity and additional sources of defects to the design.Following a model-based approach and automatically transforming this model to code adds yet another level of complexity. In the case of simulation, the simulator provides execution semantics that might not be exactly the same as those implicitly assigned to the model during its transformation into source code. When a developer specifies statecharts, execution semantics can vary among tools, simulators, and code generators.Simulation offers pure functional validation. When simulating a model’s execution, we know of no ways to validate nonfunctional requirements, especially concerning performance characteristics. Testing on real-time constraints or detecting and resolving race conditions requires execution on a platform as similar to the target platform as possible.For a heterogeneous development environment (such as the one our work focuses on), simulators can be coupled. The visualization is usually accomplished using dedicated simulation tools or a visualization inside the design tools. For debugging, we couple the model before code generation, as we described earlier. The execution is then visualized using either the development tools or a dedicated visualization layer. We chose the latter approach, mainly because existing CASE tools’ back-annotation facilities are, if available at all, proprietary, undocumented, and rather rudimentary. A debugging tool exists for models developed with Telelogic (formerly I-Logix) Rhapsody.However, some advantages we’ve mentioned for debugging could also be advantageous for a simulation approach. This particularly holds true for early design phases, where hardware and peripherals don’t yet exist and pure functional validation is sufficient. Also, simulation can provide better reproducibility.Runtime models and synchronizationYou can think of debugging a system that was developed using a model-based method as reversing the various transformation steps, from the model down to executable code.Figure 2 illustrates the situation. The software design results in a model, which is detailed enough to be transformed into source code in a high-level language (for example, C or C++ in embedded software). The source code is transformed again using a compiler, resulting in an executable binary ready for deployment to the target platform. Following the OMG’s MDA approach, we can regard artifacts on all three layers as models.Figure 2. Mappings between model layers.The binary file (for example, the model on the lowest level) executes on the target platform. Basically, the debugger extracts runtime information out of the executed binary from the target platform and transports this information back through the abstraction layers to the model level.Fortunately, modern source-level debuggers already accomplish the first step—extracting information from the runtime level to the source-code level. Examples include the GNU Debugger (GDB, a part of the GNU Compiler toolchain), the Java Debug Interface (JDI), or proprietary source-level interfaces to debuggers for embedded processors.The extracted information refers to debugging artifacts at the source level, such as lines of code, variables, and other source-level symbols. Because we want to obtain model-level information (for example, the active state of an executed state diagram), we must provide a mapping to the runtime information’s model level.However, you shouldn’t confuse this “reversion” with reverse engineering, which aims to reconstruct the modeling artifacts themselves. From the executed model’s viewpoint, artifacts can be static (elements originating from development) or dynamic (runtime information).To hold and link the artifacts, the UML metamodel, which is based on the Meta Object Facility (MOF),6 is extended with a runtime metamodel. Figure 3 shows this extension’s relation to OMG’s metalayer concept. Each layer is an abstraction of the underlying layer, with the top layer (M3) at the highest abstraction level. The bottom layer (M0) comprises the information that we wish to describe. On the model layer (M1) is the metadata of the M0 layer, the so-called model. Object-oriented software is typically described on the M1 layer as a UML model. The runtime information is also stored on this layer and linked with the existing modeling artifacts. The metamodel on the M2 layer consists of descriptions that define the metadata’s structure and semantics (for example, the structure of a valid UML model). These metamodels—for example, UML 1.4 or UML 1.5—define the language and notation for describing different kinds of data respectively (M1). We extend the metamodel on this level to allow storage of runtime information. The extension lets our debugger dynamically gather the debugging data needed for debugging and link it with elements of the static-model part on M1. Finally,M3 contains the self-describing meta-metamodel MOF. It’s used to describe metamodels and define their structure, syntax, and semantics—that is, it’s an object-oriented language for defining metadata.Figure 3. Object Management Group metamodel layers and runtime information.The model debugger can use the runtime information on the model level to visualize the executable’s internal state. The visualization can also use static artifacts. For example, to visualize a state chart’s runtime state, the static information is used to render the diagram itself. The dynamic artifacts are used only to annotate or assign a different color to the active states in the diagram.Mapping example: Executable Stateflow diagramsHere, we clarify the work a typical mapper accomplishes by describing the time-discrete execution of Stateflow diagrams and the mapping involved. Matlab Stateflow, frequently used by control engineers, is a CASE tool that lets developers describe event-discrete models in syntax and semantics similar to UML state diagrams. Using the Real-Time Workshop Embedded Coder extension, we can generate optimized C code. The source code is integrated into the framework code generated from a UML-based supermodel using the coupling approach we mentioned earlier.When considering an executable Stateflow diagram at runtime and the artifacts that are of interest to the user during debugging, the following questions arise:x Which basic states in the diagram are currently active (active state)?x Which events were triggered and will be relevant for the coming model time step (triggered events)?x What are the values of the data context in Stateflow (data values)? (Data values are data storage elements similar to variables in programming languages.)x Which transitions were triggered during the past time step (transitions)?Using this information, an application developer can gain insight into the model’s state and execution properties. Additionally, runtime control must switch from stepping through lines of code to stepping ahead one or several time steps in the execution of Stateflow diagrams.Our model-level debugger acquires the model artifacts through mappers and model-level run-control of the target using a controller. The controller is based on setting source-level breakpoints at strategic positions. Resuming execution at the source level makes the target stop whenever the next model-level time step is completed.To allow the mapping of runtime data for later display to the user, the UML metamodel containing static model artifacts is extended with metaclasses that allow storage of the data the mapper acquires. Figure 4 shows a detail of this extension for Stateflow diagrams. While modeling and code generation is accomplished through Stateflow, the debugger works on the representation of the model that was transformed to the UML metamodel. Figure 4 shows the UML metamodel for state diagrams and a simple extension for data values (called Guards in UML). The basis for the runtime model is the DebugContext, to which the debugger can attach any number of GuardValues. Each GuardValue is linked to the static Guard it stores the value for.Figure 4. Extension of the UML state diagram metamodel to hold dynamic runtime information.Mappers fill the data structures with values. As an example, we describe the mapping of the currently active basic state from the runtime information available from the source-level debugger.Figure 5 shows a simple Stateflow diagram (see figure 5a) and the corresponding data structures in C code when rendering it using the Real-Time Workshop Embedded Coder. Every composite XOR state is rendered into one variable (see figure 5b) containing information on the activity of its direct substates in the hierarchy. The model debugger can reconstruct these variables purely from model information—namely, the state name and number depending on its position in the hierarchy (this follows a deterministic rule). These numeric values must be mapped to model information again. Figure 5c shows the mapping. Every level has its own alphabetically sorted enumeration.Figure 5. The Real-Time Workshop Embedded Coder uses (a) a Stateflow diagram to generate data structures, which contain (b) variables that store state information. These variables encode model information using (c) a specific state encoding.Based on these observations, we let the debugger perform the mapping using the following algorithm:1.Begin with the top-level composite state—for example, the diagram.2.Reconstruct a variable name that contains activity information for this level (as we describedearlier).3.Acquire a value from the target via the driver layer.4.Reconstruct the active substate from the value.5.Check the type of substate. If it’s a basic state, add it to the runtime model. If it’s a compositenonconcurrent state, perform step 2 (recursion) on that substate. If the substate is acomposite concurrent state, iterate over all its children, performing step 2 (recursing) onevery child.By applying this algorithm, we obtain a list of all concurrently active basic states in the Stateflow diagram. The debugger uses this information for visualization later on.Architecture for debugging heterogeneous systemsFigure 6 shows the architecture resulting from the approach we introduced in the “Runtime models and synchronization” section. It’s built up from layers that continuously abstract further from the target architecture, source-level debugger, and programming language toward model-level visualization.Figure 6. Layered debugging architecture.The starting point is the modeled software that executes on the embedded target platform. Different target architectures include or support different source-level debuggers that allow extraction of runtime information over proprietary interfaces. Examples are the JDI, which integrates into the debuggee’s class path; GDB’s text-based interface; and proprietary debugging hardware for embedded processors.The driver layer unifies these source-level debuggers as far as possible. Because the debuggers don’t offer the same set of features and information, we defined interfaces that group sets of capabilities. Drivers generally implement only a set of the interfaces, influencing the capabilities that the debug system can offer to the higher levels. Common interfaces include run-control (starting, stopping, resetting, and stepping), access to symbol data (memory addresses of methods), and expression evaluation (reading variable values). Hardware-based debuggers often also offer an interface for acquiring and reading real-time trace data from the target.Viewed from the topmost layer (see figure 6), the architecture offers the user different viewpoints of the debugger. A viewpoint defines a specific view of the system and mediates between the target system and the visualization layer that’s on top of it. A typical debugging session for heterogeneously modeled software uses several viewpoints. The object configuration of the object-oriented software-intensive part is visualized using a UML object diagram, and every embedded statechart shows the behavior of components, classes, or port protocols. The complete set of viewpoints offers insight to all aspects of the running model.The visualization layer is based on the open source development platform Eclipse and the associated diagramming framework Graphical Editor Framework. The diagram model is based on the Diagram Interchange (DI) metamodel, which has been part of the UML specification since UML 2.0.Between a viewpoint and driver are a mapper and controller that bridge the model layers. The viewpoint uses the controller to control the system from the model’s viewpoint. An execution step in a statechart corresponds to a complex sequence of commands at the source-code level. The mapper updates the runtime information model that provides the basis for the visualization with information from the source-level debug drivers. We outlined an example of mapping Stateflow charts in the “Mapping example: Executable Stateflow diagrams” section.PrototypeFigure 7 shows a screen capture of our current model debugger implementation. The tool extends the Eclipse platform using various plug-ins that allow handling of models and visual debugging.Figure 7. The model debugger’s user interface.The prototype lets the user open models from XMI (XML Media Interchange, the format for exchanging UML models) or Matlab Simulink files using the standard Eclipse Navigator view. These files can be visualized using a view showing a model tree of all model artifacts and a tabular detail view of properties and relations (the lower right part of figure 7). The user can open the DI-based diagrams these models contain in a graphical viewer.Debugging centers on the DebugSession view in the upper-left corner of figure 7. After connecting to a debug target through a driver, the user can add viewpoints, each opening a view or a graphical diagram editor as its visualization component. In the figure, one viewpoint shows a Stateflow chart. This diagram is already augmented with information on the active states in the running target.The DebugSession view’s toolbar lets the user run, reset, and time step the target on the basis of the selected viewpoint. In the figure’s lower left part, the DebugContext view provides insight into the model’s dynamic part, as we described earlier based on a tree view.Automated transformation of models into executable code to enable rapid system development is becoming increasingly common. It requires new model-based ways to debug and monitor such models directly on an embedded target platform. Our architecture allows the definition of various debugging perspectives and views independent of the actual execution platform, maximizing reusability inside the architecture.One key achievement is that our approach maximizes reusability while covering various aspects of heterogeneity:x Development using different domain-specific modeling tools. Through adapted viewpoints, the user or developer can obtain adequate views of the various subsystems.x Different development tool chains and target systems. By implementing a driver, you can integrate other target platforms running with different processors, operating systems, anddebugging interfaces. Higher-level layers might remain untouched. One example would be to use the real-time tracing capabilities of embedded-processor-debugging hardware to reduceimpact on timing.x Distributed systems. Using various driver instances, you can debug models that execute concurrently on different hardware nodes using one instance of the debugger platform.x Heterogeneous architectures. Model-based hardware and software codesign can be supported by hardware and software co-debugging. As reconfigurable hardware and parallel hardwareand software development become increasingly important, a model-based approach allowslate decisions on the execution platform of functionality. We plan to further investigate thetransparent debugging of such systems.References1.Unified Modeling Language (UML) Specification, version 1.5, Object Management Group, 2003.2. D. Harel, “Statecharts: A Visual Formalism for Complex Systems,” Science of ComputerProgramming, vol. 8, no. 3, 1987, pp. 231–274.3.MDA Guide, version 1.0.1, Object Management Group, 2003.4.P. Graf and K. Müller-Glaser, “Dynamic Mapping of Runtime Information Models for DebuggingEmbedded Software,”Proc. 17th IEEE Int’l Workshop Rapid System Prototyping, IEEE CSPress, 2006, pp. 3–9.5.R. Dreier et al., “Partitioning and FPGA-Based Co-simulation of Statecharts,” Proc. 15th Ann.European Simulation Symp. (ESS 03), SCS Europe, 2003.6.Meta Object Facility (MOF) Specification, version 1.4, Object Management Group, 2001.Philipp Graf is a scientific assistant and PhD candidate at the University of Karlsruhe’s Institute forInformation Processing Technologies. His research interests include UML-based design methodologies forembedded electronic systems, executable models, and debugging of such models. He received his Dipl.-Ing.in electrical engineering from the University of Karlsruhe. Contact him at the Institut für Technik derInformationsverarbeitung, Universität Karlsruhe (TH), Engesserstr. 5, D-76131 Karlsruhe, Germany;graf@itiv.uni-karlsruhe.de.Klaus D. Müller-Glaser is a director of the University of Karlsruhe FZI Forschungszentrum Informatik(Research Center for Information Technologies). He is also a professor at the University of Karlsruhe andhead of the university’s Institute of Information Processing Technologies. His research interests includemethods and tools for the design of electronic systems, microsystems and systems-on-chip, executablespecifications, and model-based design. He received his Dr.-Ing. from the University of Karlsruhe. Contacthim at the Institut für Technik der Informationsverarbeitung, Universität Karlsruhe (TH), Engesserstr. 5, D-76131 Karlsruhe, Germany; mueller-glaser@itiv.uni-karlsruhe.de.Related Linksx DS Online's Real-Time and Embedded Systems Communityx Proc. 17th IEEE Int'l Workshop Rapid Systems Prototyping (RSP 06)Cite this article:Philipp Graf and Klaus D. Müller-Glaser, "Gaining Insight into Executable Models during Runtime: Architecture and Mappings,"IEEE Distributed Systems Online, vol. 8, no. 3, 2007, art. no. 0703-o3001.IEEE Distributed Systems Online (vol. 8, no. 3), art. no. 0703-o3001 11。

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