A Linearization Technique for CMOS RF Power Amplifiers

IntroductionThe next generation of wireless transceivers for LAN applicationswill support data rates many orders of magnitude higher than today’smainly voiceband wireless devices. They will accomplish this withspectrally efficient modulation schemes, such as multi-level QAM,and also pack more channels into the available operating frequencyband in every microcell. This requires a highly linear, yet efficientpower amplifier in the transmitter.This paper describes a compact, yet general, linearization methodwell-suited to CMOS power amplifiers. It is intended for use in ahigh bit-rate wireless system signalling with 64-QAM, and usingevery channel in each cell. The latter demands higher power ampli-fier linearity, as is now explained. 3rd-order intermodulation distor-

tion between the tones comprising a modulated spectrum causesenergy to spill over into the immediately adjacent channels (Fig.1),while the much smaller 5th-order distortion spills energy into the

alternate channels. For this reason, wireless systems today use ev-ery other channel in a given cell, guaranteeing that a transmitter inthe alternate channel spills only a small energy into a given channel,and does not significantly interfere with the user assigned this chan-nel. Our system consumes more spectrum per channel to carry dataat rates > 10Mb/s, but makes up some of the lost capacity with amore linear power amplifier which allows use of every channel in acell. The specification is to leak less than –50 dBc into the adjacentand other channels at an RF output power of 20 mW (2.8V ptp into50⍀). A power-added efficiency of 5 to 10% is acceptable in such ahigh performance transceiver.System-level methods, such as predistortion [1], feedforwarderror-cancellation [2], and Cartesian feedback [3], have been pro-posed to linearize efficient, and therefore nonlinear, power amplifi-ers. However, they all require complex hardware, and may be bettersuited to base stations. A transistor-level linearization is more ap-propriate for the power amplifier in the handset.

The Linearization Technique

Any CMOS amplifier with balanced input and output very effec-tively suppresses the dominant 2nd-order distortion, a method that is

widely used in accurate continuous-time analog CMOS circuits. Atissue here is 3rd-order distortion, however, of which relatively littleis known, particularly in short-channel MOSFETs. Representing apower amplifier FET (Fig.2(a)) as a nonlinear transconductor,i=a1v+a2v2+a3v3 driving a 50⍀ load, it may be calculated that to

deliver the specified maximum power at the desired linearity withgm=a1=70 mS, as used in our prototype, |a3|<0.007. a3 is not this low

anywhere in the I-V characteristic (Fig.2(b)) except in the vicinityof its zero crossings, and those regions are not flat enough acrossthe necessary current swing of 20 mA ptp. However, a flat region

with very low a3 may be synthesized with two or more FETs, by

cancelling the negative a3 of one FET in saturation with the positivea3 of a second FET in triode. If a common-source FET (M1) is bi-

ased in saturation at some VGS, a second FET (M2) may be forcedinto the triode region at the same VGS by stacking on it a cascodeFET (M3) (Fig.3(a)), and the two FET currents then summed toachieve the cancellation in the 3rd-order coefficient, a3.

The nonlinearity cancellation is strictly true only at DC. TheFET currents do not sum in-phase at RF because of the unequaldelays in the two paths. The delays are balanced by splitting theFET M1 into two FETs, M1A and M1B, in series (Fig.3(b)). AsM1A and M2 both now operate in triode, the nonlinearity cancella-tion approximately still holds if they are merged into a single FET,M1 (Fig.3(c)). This compound FET is used in the power amplifier.Linearity is retained with M3 gate bias, VC, in the range 1.45 to1.75V, optimally at VC=VGS(M1)=1.6V.

Nonlinear drain resistance, rDS, appearing in parallel with thefixed antenna load is another significant source of distortion in thesingle-FET common-source amplifier. The cascode FETs, M2 andM3, boost the total output resistance and thereby alleviate this sourceof distortion in the compound FET.

Experimental Results

Compound FETs have been fabricated in 0.6µm CMOS, withW(M1)=1000µm, W(M2)=700µm, and W(M3)=300µm. First, the3rd-order distortion coefficient, a3, in the measured DC I-V charac-

teristic of the compound FET is compared with that measured for asingle common-source FET of size 1000/1.2µm (Fig.4). a3 of the