ADC0832

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ADC0832

ADC0831/ADC0832/ADC0834/ADC08388-Bit Serial I/O A/D Converters with Multiplexer OptionsGeneral DescriptionThe ADC0831series are 8-bit successive approximation A/D converters with a serial I/O and configurable input multiplex-ers with up to 8channels.The serial I/O is configured to comply with the NSC MICROWIRE ™serial data exchange standard for easy interface to the COPS ™family of proces-sors,and can interface with standard shift registers or µPs.The 2-,4-or 8-channel multiplexers are software configured for single-ended or differential inputs as well as channel as-signment.The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value.In addition,the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8bits of resolution.Featuresn NSC MICROWIRE compatible —direct interface to COPS family processorsn Easy interface to all microprocessors,or operates “stand-alone”n Operates ratiometrically or with 5V DC voltage referencen No zero or full-scale adjust requiredn 2-,4-or 8-channel multiplexer options with address logic n Shunt regulator allows operation with high voltage suppliesn 0V to 5V input range with single 5V power supply n Remote operation with serial digital data link n TTL/MOS input/output compatiblen 0.3"standard width,8-,14-or 20-pin DIP package n 20Pin Molded Chip Carrier Package (ADC0838only)n Surface-Mount PackageKey Specificationsn Resolution8Bitsn Total Unadjusted Error ±1⁄2LSB and ±1LSBn Single Supply 5V DC n Low Power15mW nConversion Time32µsTypical ApplicationTRI-STATE ®is a registered trademark of National Semiconductor Corporation.COPS ™and MICROWIRE ™are trademarks of National Semiconductor Corporation.DS005583-1August 1999ADC0831/ADC0832/ADC0834/ADC08388-Bit Serial I/O A/D Converters with Multiplexer Options©1999National Semiconductor Corporation Connection DiagramsADC08388-Channel MuxSmall Outline/Dual-In-Line Package(WM and N)DS005583-8Top ViewADC08344-Channel MUXSmall Outline/Dual-In-Line Package(WM and N)DS005583-30COM internally connected to A GND Top ViewTop ViewADC08322-Channel MUX Dual-In-Line Package (N)DS005583-31COM internally connected to GND.V REF internally connected to V CC .Top ViewTop ViewADC08322-Channel MUX Small Outline Package (WM)DS005583-41Top ViewADC0831Single Differential Input Dual-In-Line Package (N)DS005583-32Top ViewADC0831Single Differential Input Small Outline Package (WM)DS005583-42Top ViewADC08388-Channel MUX Molded Chip Carrier (PCC)Package (V)DS005583-33 2Ordering InformationPart Number Analog Input Total Package TemperatureChannels Unadjusted Error RangeADC0831CCN1±1Molded(N)0˚C to+70˚CADC0831CCWM SO(M)0˚C to+70˚CADC0832CIWM2±1SO(M)−40˚C to+85˚CADC0832CCN Molded(N)0˚C to+70˚CADC0832CCWM SO(M)0˚C to+70˚CADC0834BCN4±1⁄2Molded(N)0˚C to+70˚CADC0834CCN±1Molded(N)0˚C to+70˚CADC0834CCWM SO(M)0˚C to+70˚CADC0838BCV8±1⁄2PCC(V)0˚C to+70˚CADC0838CCV±1PCC(V)0˚C to+70˚CADC0838CCN Molded(N)0˚C to+70˚CADC0838CIWM SO(M)−40˚C to+85˚CADC0838CCWM SO(M)0˚C to+70˚CSee NS Package Number M14B,M20B,N08E,N14A,N20A or V20A3Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Current into V+(Note3)15mA Supply Voltage,V CC(Note3) 6.5V VoltageLogic Inputs−0.3V to V CC+0.3V Analog Inputs−0.3V to V CC+0.3V Input Current per Pin(Note4)±5mA Package±20mA Storage Temperature−65˚C to+150˚C Package Dissipationat T A=25˚C(Board Mount)0.8W Lead Temperature(Soldering10sec.)Dual-In-Line Package(Plastic)260˚C Molded Chip Carrier PackageVapor Phase(60sec.)215˚C Infrared(15sec.)220˚C ESD Susceptibility(Note5)2000V Operating Ratings(Notes1,2)Supply Voltage,V CC 4.5V DC to6.3V DC Temperature Range T MIN≤T A≤T MAX ADC0832/8CIWM−40˚C to+85˚C ADC0834BCN,ADC0838BCV,ADC0831/2/4/8CCN,ADC0838CCV,ADC0831/2/4/8CCWM0˚C to+70˚CConverter and Multiplexer Electrical Characteristics The following specifications apply for V CC=V+=V REF=5V,V REF≤V CC+0.1V,T A=T j=25˚C,and f CLK=250kHz unless otherwise specified.Boldface limits apply from T MIN to T MAX.Parameter Conditions CIWM Devices BCV,CCV,CCWM,BCNand CCN DevicesTyp Tested Design Typ Tested Design Units (Note12)Limit Limit(Note12)Limit Limit(Note13)(Note14)(Note13)(Note14)CONVERTER AND MULTIPLEXER CHARACTERISTICSTotal Unadjusted Error V REF=5.00VADC0838BCV(Note6)±1⁄2±1⁄2ADC0834BCN±1⁄2±1⁄2LSB(Max) ADC0838CCV±1±1ADC0831/2/4/8CCN±1±1ADC0831/2/4/8CCWM±1±1ADC0832/8CIWM±1Minimum Reference 3.5 1.3 3.5 1.3 1.3kΩInput Resistance(Note7)Maximum Reference 3.5 5.9 3.5 5.4 5.9kΩInput Resistance(Note7)Maximum Common-ModeInput Range(Note8)V CC+0.05V CC+0.05V CC+0.05VMinimum Common-ModeInput Range(Note8)GND−0.05GND−0.05GND−0.05V DC Common-Mode Error±1/16±1⁄4±1/16±1⁄4±1⁄4LSB Change in zero15mA into V+error from V CC=5V V CC=N.C.to internal zener V REF=5Voperation(Note3)111LSB V Z,internal MIN15mA into V+ 6.3 6.3 6.3diode breakdown MAX8.58.58.5V (at V+)(Note3)Power Supply Sensitivity V CC=5V±5%±1/16±1⁄4±1⁄4±1/16±1⁄4±1⁄4LSBI OFF,Off Channel Leakage On Channel=5V,−0.2−0.2−1µACurrent(Note9)Off Channel=0V−1On Channel=0V,+0.2+0.2+1µAOff Channel=5V+14Converter and Multiplexer Electrical Characteristics The following specifications apply for V CC=V+=V REF=5V,V REF≤V CC+0.1V,T A=T j=25˚C,and f CLK=250kHz unless otherwise specified.Boldface limits apply from T MIN to T MAX.(Continued)Parameter Conditions CIWM Devices BCV,CCV,CCWM,BCNand CCN DevicesTyp Tested Design Typ Tested Design Units (Note12)Limit Limit(Note12)Limit Limit(Note13)(Note14)(Note13)(Note14)CONVERTER AND MULTIPLEXER CHARACTERISTICSI ON,On Channel Leakage On Channel=0V,−0.2−0.2−1µA Current(Note9)Off Channel=5V−1On Channel=5V,+0.2+0.2+1µAOff Channel=0V+1DIGITAL AND DC CHARACTERISTICSV IN(1),Logical“1”Input V CC=5.25V 2.0 2.0 2.0V Voltage(Min)V IN(0),Logical“0”Input V CC=4.75V0.80.80.8V Voltage(Max)I IN(1),Logical“1”Input V IN=5.0V0.00510.00511µA Current(Max)I IN(0),Logical“0”Input V IN=0V−0.005−1−0.005−1−1µA Current(Max)V OUT(1),Logical“1”Output V CC=4.75VVoltage(Min)I OUT=−360µA 2.4 2.4 2.4VI OUT=−10µA 4.5 4.5 4.5VV OUT(0),Logical“0”Output V CC=4.75V0.40.40.4V Voltage(Max)I OUT=1.6mAI OUT,TRI-STATE Output V OUT=0V−0.1−3−0.1−3−3µA Current(Max)V OUT=5V0.130.1+3+3µAI SOURCE,Output Source V OUT=0V−14−6.5−14−7.5−6.5mA Current(Min)I SINK,Output Sink Current(Min)V OUT=V CC168.0169.08.0mAI CC,Supply Current(Max)ADC0831,ADC0834,0.9 2.50.9 2.5 2.5mA ADC0838ADC0832Includes Ladder 2.3 6.5 2.3 6.5 6.5mACurrentAC CharacteristicsThe following specifications apply for V CC=5V,t r=t f=20ns and25˚C unless otherwise specified.Typ Tested Design Limit Parameter Conditions(Note12)Limit Limit Units(Note13)(Note14)f CLK,Clock Frequency Min10kHzMax400kHzt C,Conversion Time Not including MUX Addressing Time81/f CLK Clock Duty Cycle Min40% (Note10)Max60%t SET-UP,CS Falling Edge or250ns Data Input Valid to CLKRising Edget HOLD,Data Input Valid90ns after CLK Rising Edge5AC Characteristics(Continued)The following specifications apply for V CC =5V,t r =t f =20ns and 25˚C unless otherwise specified.TypTested Design Limit ParameterConditions(Note 12)Limit Limit Units(Note 13)(Note 14)t pd1,t pd0—CLK Falling C L =100pF Edge to Output Data Valid Data MSB First 6501500ns (Note 11)Data LSB First 250600ns t 1H ,t 0H ,—Rising Edge of C L =10pF,R L =10k125250ns CS to Data Output and (see TRI-STATE ®Test Circuits)SARS Hi–ZC L =100pf,R L =2k500ns C IN ,Capacitance of Logic 5pF InputC OUT ,Capacitance of Logic 5pFOutputsNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.Note 2:All voltages are measured with respect to the ground plugs.Note 3:Internal zener diodes (6.3to 8.5V)are connected from V+to GND and V CC to GND.The zener at V+can operate as a shunt regulator and is connected to V CC via a conventional diode.Since the zener voltage equals the A/D’s breakdown voltage,the diode insures that V CC will be below breakdown when the device is powered from V+.Functionality is therefore guaranteed for V+operation even though the resultant voltage at V CC may exceed the specified Absolute Max of 6.5V.It is recommended that a resistor be used to limit the max current into V+.(See Figure 3in Functional Description Section 6.0)Note 4:When the input voltage (V IN )at any pin exceeds the power supply rails (V IN <V −or V IN >V +)the absolute value of current at that pin should be limited to 5mA or less.The 20mA package input current limits the number of pins that can exceed the power supply boundaries with a 5mA current limit to four.Note 5:Human body model,100pF discharged through a 1.5k Ωresistor.Note 6:Total unadjusted error includes offset,full-scale,linearity,and multiplexer errors.Note 7:Cannot be tested for ADC0832.Note 8:For V IN (−)≥V IN (+)the digital output code will be 00000000.Two on-chip diodes are tied to each analog input (see Block Diagram)which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V CC supply.Be careful,during testing at low V CC levels (4.5V),as high level analog inputs (5V)can cause this input diode to conduct —especially at elevated temperatures,and cause errors for analog inputs near full-scale.The spec allows 50mV forward bias of either diode.This means that as long as the analog V IN or V REF does not exceed the supply voltage by more than 50mV,the output code will be correct.To achieve an absolute 0V DC to 5V DC input voltage range will therefore require a minimum supply voltage of 4.950V DC over temperature varia-tions,initial tolerance and loading.Note 9:Leakage current is measured with the clock not switching.Note 10:A 40%to 60%clock duty cycle range insures proper operation at all clock frequencies.In the case that an available clock has a duty cycle outside of these limits,the minimum,time the clock is high or the minimum time the clock is low must be at least 1µs.The maximum time the clock can be high is 60µs.The clock can be stopped when low so long as the analog input voltage remains stable.Note 11:Since data,MSB first,is the output of the comparator used in the successive approximation loop,an additional delay is built in (see Block Diagram)to allow for comparator response time.Note 12:Typicals are at 25˚C and represent most likely parametric norm.Note 13:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 14:Guaranteed but not 100%production tested.These limits are not used to calculate outgoing quality levels.Typical Performance CharacteristicsUnadjusted Offset Error vs V REF VoltageDS005583-43Linearity Error vs V REF VoltageDS005583-44Linearity Error vs TemperatureDS005583-45 6Typical Performance Characteristics(Continued)Leakage Current Test CircuitLinearity Error vs f CLKDS005583-46Power Supply Current vs Temperature (ADC0838,ADC0831,ADC0834)DS005583-47Note:For ADC0832add I REF .Output Current vs TemperatureDS005583-48Power Supply Current vs f CLKDS005583-29DS005583-37TRI-STATE Test Circuits and WaveformsTiming Diagramst 1HDS005583-49t 0HDS005583-50t 1H DS005583-51t 0HDS005583-52Data Input TimingDS005583-24Data Output TimingDS005583-25ADC0831Start Conversion TimingDS005583-26 8Timing Diagrams(Continued)ADC0831TimingDS005583-27*LSB first output not available on ADC0831.ADC0832TimingDS005583-28ADC0834TimingDS005583-59Timing Diagrams(Continued)A D C 0838T i m i n gD S 005583-6*M a k e s u r e c l o c k e d g e #18c l o c k s i n t h e L S B b e f o r e S E i s t a k e n l o w10ADC0838Functional Block DiagramD S 005583-7*S o m e o f t h e s e f u n c t i o n s /p i n s a r e n o t a v a i l a b l e w i t h o t h e r o p t i o n s .N o t e 1:F o r t h e A D C 0834,D 1i s i n p u t d i r e c t l y t o t h e D i n p u t o f S E L E C T 1.S E L E C T 0i s f o r c e d t o a “1”.F o r t h e A D C 0832,D I i s i n p u t d i r e c t l y t o t h e D I i n p u t o f O D D /S I G N .S E L E C T 0i s f o r c e d t o a “0”a n d S E L E C T 1i s f o r c e d t o a “1”.11Functional Description 1.0MULTIPLEXER ADDRESSINGThe design of these converters utilizes a sample-data com-parator structure which provides for a differential analog in-put to be converted by a successive approximation routine. The actual voltage converted is always the difference be-tween an assigned“+”input terminal and a“−”input terminal. The polarity of each input terminal of the pair being con-verted indicates which line the converter expects to be the most positive.If the assigned“+”input is less than the“−”in-put the converter responds with an all zeros output code.A unique input multiplexing scheme has been utilized to pro-vide multiple analog channels with software-configurable single-ended,differential,or a new pseudo-differential option which will convert the difference between the voltage at any analog input and a common terminal.The analog signal con-ditioning required in transducer-based data acquisition sys-tems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage.A particular input configuration is assigned during the MUX addressing sequence,prior to the start of a conversion.The MUX address selects which of the analog inputs are to be enabled and whether this input is single-ended or differential.In the differential case,it also assigns the polarity of the channels.Differential inputs are restricted to adjacent chan-nel pairs.For example channel0and channel1may be se-lected as a different pair but channel0or1cannot act differ-entially with any other channel.In addition to selecting differential mode the sign may also be selected.Channel0 may be selected as the positive input and channel1as the negative input or vice versa.This programmability is best il-lustrated by the MUX addressing codes shown in the follow-ing tables for the various product options.The MUX address is shifted into the converter via the DI line. Because the ADC0831contains only one differential input channel with a fixed polarity assignment,it does not require addressing.The common input line on the ADC0838can be used as a pseudo-differential input.In this mode,the voltage on this pin is treated as the“−”input for any of the other input channels. This voltage does not have to be analog ground;it can be any reference potential which is common to all of the inputs. This feature is most useful in single-supply application where the analog circuitry may be biased up to a potential other than ground and the output signals are all referred to this potential.TABLE1.Multiplexer/Package OptionsPart Number of Analog Channels Number ofNumber Single-Ended Differential Package PinsADC0831118ADC0832218ADC08344214ADC08388420 12Functional Description(Continued)TABLE2.MUX Addressing:ADC0838Single-Ended MUX ModeMUX Address Analog Single-Ended Channel#SGL/ODD/SELECT01234567COMDIF SIGN101000+−1001+−1010+−1011+−1100+−1101+−1110+−1111+−TABLE3.MUX Addressing:ADC0838Differential MUX ModeMUX Address Analog Differential Channel-Pair#SGL/ODD/SELECT0123DIF SIGN10012345670000+−0001+−0010+−0011+−0100−+0101−+0110−+0111−+TABLE4.MUX Addressing:ADC0834Single-Ended MUX ModeMUX Address Channel#SGL/ODD/SELECTDIF SIGN10123100+101+110+111+COM is internally tied to A GNDTABLE5.MUX Addressing:ADC0834Differential MUX ModeMUX Address Channel#SGL/ODD/SELECTDIF SIGN10123000+−001+−010−+011−+13Functional Description(Continued)TABLE6.MUX Addressing:ADC0832Single-Ended MUX ModeMUX Address Channel#SGL/ODD/01DIF SIGN10+11+COM is internally tied to A GNDTABLE7.MUX Addressing:ADC0832Differential MUX ModeMUX Address Channel#SGL/ODD/01DIF SIGN00+−01−+Since the input configuration is under software control,it can be modified,as required,at each conversion.A channel can be treated as a single-ended,ground referenced input for one conversion;then it can be reconfigured as part of a dif-ferential channel for another conversion.Figure1illustrates the input flexibility which can be achieved.The analog input voltages for each channel can range from 50mV below ground to50mV above V CC(typically5V)with-out degrading conversion accuracy.2.0THE DIGITAL INTERFACEA most important characteristic of these converters is their serial data link with the controlling ing a serial communication format offers two very significant system im-provements;it allows more function to be included in the converter package with no increase in package size and it can eliminate the transmission of low level analog signals by locating the converter right at the analog sensor;transmitting highly noise immune digital data back to the host processor. To understand the operation of these converters it is best to refer to the Timing Diagrams and Functional Block Diagram and to follow a complete conversion sequence.For clarity a separate diagram is shown of each device.1.A conversion is initiated by first pulling the CS(chip select) line low.This line must be held low for the entire conversion. The converter is now waiting for a start bit and its MUX as-signment word.2.A clock is then generated by the processor(if not provided continuously)and output to the A/D clock input.14Functional Description(Continued)3.On each rising edge of the clock the status of the data in (DI)line is clocked into the MUX address shift register.The start bit is the first logic “1”that appears on this line (all lead-ing zeros are ignored).Following the start bit the converter expects the next 2to 4bits to be the MUX assignment word.4.When the start bit has been shifted into the start location of the MUX register,the input channel has been assigned and a conversion is about to begin.An interval of 1⁄2clock pe-riod (where nothing happens)is automatically inserted to al-low the selected MUX channel to settle.The SAR status line goes high at this time to signal that a conversion is now in progress and the DI line is disabled (it no longer accepts data).5.The data out (DO)line now comes out of TRI-STATE and provides a leading zero for this one clock period of MUX set-tling time.6.When the conversion begins,the output of the SAR com-parator,which indicates whether the analog input is greater than (high)or less than (low)each successive voltage from the internal resistor ladder,appears at the DO line on each falling edge of the clock.This data is the result of the conver-sion being shifted out (with the MSB coming first)and can be read by the processor immediately.7.After 8clock periods the conversion is completed.The SAR status line returns low to indicate this 1⁄2clock cycle later.8.If the programmer prefers,the data can be provided in an LSB first format [this makes use of the shift enable (SE)con-trol line].All 8bits of the result are stored in an output shift register.On devices which do not include the SE control line,the data,LSB first,is automatically shifted out the DO line,after the MSB first data stream.The DO line then goes low and stays low until CS is returned high.On the ADC0838the SE line is brought out and if held high,the value of the LSB remains valid on the DO line.When SE is forced low,the data is then clocked out LSB first.The ADC0831is an excep-tion in that its data is only output in MSB first format.9.All internal registers are cleared when the CS line is high.If another conversion is desired,CS must make a high to low transition followed by address information.The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire.This is possible because the DI input is only “looked-at”during the MUX addressing interval while the DO line is still in a high impedance state.8Single-EndedDS005583-538Pseudo-DifferentialDS005583-544Differential DS005583-55Mixed ModeDS005583-56FIGURE 1.Analog Input Multiplexer Options for the ADC083815Functional Description(Continued)3.0REFERENCE CONSIDERATIONSThe voltage applied to the reference input to these convert-ers defines the voltage span of the analog input (the differ-ence between V IN(MAX)and V IN(MIN))over which the 256possible output codes apply.The devices can be used in ei-ther ratiometric applications or in systems requiring absolute accuracy.The reference pin must be connected to a voltage source capable of driving the reference input resistance of typically 3.5k Ω.This pin is the top of a resistor divider string used for the successive approximation conversion.In a ratiometric system,the analog input voltage is propor-tional to the voltage used for the A/D reference.This voltage is typically the system power supply,so the V REF pin can be tied to V CC (done internally on the ADC0832).This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintain-ing the same output code for a given input condition.For absolute accuracy,where the analog input varies be-tween very specific voltage limits,the reference pin can be biased with a time and temperature stable voltage source.The LM385and LM336reference diodes are good low cur-rent devices to use with these converters.The maximum value of the reference is limited to the V CC supply voltage.The minimum value,however,can be quite small (see Typical Performance Characteristics)to allow di-rect conversions of transducer outputs providing less than a 5V output span.Particular care must be taken with regard to noise pickup,circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1LSB equals V REF /256).4.0THE ANALOG INPUTSThe most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling proces-sor with a highly noise immune serial bit stream.This in itself greatly minimizes circuitry to maintain analog signal accu-racy which otherwise is most susceptible to noise pickup.However,a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common-mode voltage.The differential input of these converters actually reduces the effects of common-mode input noise,a signal common to both selected “+”and “−”inputs for a conversion (60Hz is most typical).The time interval between sampling the “+”in-put and then the “−”input is 1⁄2of a clock period.The change in the common-mode voltage during this short time interval can cause conversion errors.For a sinusoidal common-mode signal this error is:where f CM is the frequency of the common-mode signal,V PEAK is its peak voltage valueand f CLK ,is the A/D clock frequency.For a 60Hz common-mode signal to generate a 1⁄4LSB error (≈5mV)with the converter running at 250kHz,its peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input limits.Due to the sampling nature of the analog inputs short spikes of current enter the “+”input and exit the “−”input at the clock edges during the actual conversion.These currents decay rapidly and do not cause errors as the internal com-parator is strobed at the end of a clock period.Bypass ca-pacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source.Bypass capacitors should not be used if the source resistance is greater than 1k Ω.This source resistance limitation is important with regard to the DC leakage currents of input multiplexer as well.The worst-case leakage current of ±1µA over temperature will create a 1mV input error with a 1k Ωsource resistance.An op amp RC active low pass filter can provide both imped-ance buffering and noise filtering should a high impedance signal source be required.DS005583-57a)Ratiometric DS005583-58b)Absolute with a reduced SpanFIGURE 2.Reference Examples16Functional Description(Continued)5.0OPTIONAL ADJUSTMENTS5.1Zero ErrorThe zero of the A/D does not require adjustment.If the mini-mum analog input voltage value,V IN(MIN),is not ground a zero offset can be done.The converter can be made to out-put00000000digital code for this minimum input voltage by biasing any V IN(−)input at this V IN(MIN)value.This utilizes the differential mode operation of the A/D.The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V IN(−)input and applying a small magnitude positive voltage to the V IN(+)input.Zero error is the differ-ence between the actual DC input voltage which is neces-sary to just cause an output digital code transition from0000 0000to00000001and the ideal1⁄2LSB value(1⁄2LSB=9.8 mV for V REF=5.000V DC).5.2Full-ScaleThe full-scale adjustment can be made by applying a differ-ential input voltage which is11⁄2LSB down from the desired analog full-scale voltage range and then adjusting the mag-nitude of the V REF input(or V CC for the ADC0832)for a digi-tal output code which is just changing from11111110to1111 1111.5.3Adjusting for an Arbitrary Analog Input Voltage RangeIf the analog zero voltage of the A/D is shifted away from ground(for example,to accommodate an analog input signal which does not go to ground),this new zero reference should be properly adjusted first.A V IN(+)voltage which equals this desired zero reference plus1⁄2LSB(where the LSB is calculated for the desired analog span,using1LSB= analog span/256)is applied to selected“+”input and the zero reference voltage at the corresponding“−”input should then be adjusted to just obtain the00HEX to01HEX code tran-sition.The full-scale adjustment should be made[with the proper V IN(−)voltage applied]by forcing a voltage to the V IN(+)in-put which is given by:where:V MAX=the high end of the analog input rangeandV MIN=the low end(the offset zero)of the analog range.(Both are ground referenced.)The V REF(or V CC)voltage is then adjusted to provide a code change from FE HEX to FF HEX.This completes the adjust-ment procedure.6.0POWER SUPPLYA unique feature of the ADC0838and ADC0834is the inclu-sion of a zener diode connected from the V+terminal to ground which also connects to the V CC terminal(which is the actual converter supply)through a silicon diode,as shown in Figure3.(Note3)This zener is intended for use as a shunt voltage regulator toeliminate the need for any additional regulating components.This is most desirable if the converter is to be remotely lo-cated from the system power source.Figure4and Figure5il-lustrate two useful applications of this on-board zener whenan external transistor can be afforded.An important use of the interconnecting diode between V+and V CC is shown in Figure6and Figure7.Here,this diodeis used as a rectifier to allow the V CC supply for the converterto be derived from the clock.The low current requirements ofthe A/D and the relatively high clock frequencies used(typi-cally in the range of10k–400kHz)allows using the smallvalue filter capacitor shown to keep the ripple on the V CC lineto well under1⁄4of an LSB.The shunt zener regulator canalso be used in this mode.This requires a clock voltageswing which is in excess of V Z.A current limit for the zener isneeded,either built into the clock generator or a resistor canbe used from the CLK pin to the V+pin.DS005583-11FIGURE3.An On-Chip Shunt Regulator Diode 17。

adc0832模块程序

adc0832模块程序/* ADC0832差分00工作方式*/#include#include"adc0832.h"#include"1602.h"sbit ADC_CS =P2^0;sbit ADC_CLK=P2^1;sbit ADC_DO =P2^2;sbit ADC_DI =P2^3;unsigned char adval;unsigned char ReadADC(void) //把模拟电压值转换成8位二进制数并返回{unsigned char i,ch,bb,cc,dd;ch=0;ADC_CS=0;ADC_DO=0;//片选，DO为高阻态for(i=0;i<10;i++){;}ADC_CLK=0;delay(2);ADC_DI=1;ADC_CLK=1;delay(2); //第一个脉冲，起始位ADC_CLK=0;delay(2);ADC_DI=1;ADC_CLK=1;delay(2); //第二个脉冲，DI=1表示双通道单极性输入ADC_CLK=0;delay(2);ADC_DI=1;ADC_CLK=1;delay(2); //第三个脉冲，DI=1表示选择通道1（CH2）ADC_DI=0;ADC_DO=1;//DI转为高阻态，DO脱离高阻态为输出数据作准备ADC_CLK=1;delay(2);ADC_CLK=0;delay(2);//经实验，这里加一个脉冲AD便能正确读出数据，//不加的话读出的数据少一位（最低位d0读不出?for(i=0;i<8;i++){ADC_CLK=1;delay(2);ADC_CLK=0;delay(2);ch=(ch<<1)|ADC_DO;//在每个脉冲的下降沿DO输出一位数据，最终ch为8位二进制数}ADC_CS=1;//取消片选，一个转换周期结束adval=ch;returnadval;}。

ADC0832课程设计

ADC0832课程设计一、教学目标本课程的教学目标是使学生掌握ADC0832芯片的基本原理、功能、应用及其编程方法。

通过本课程的学习，学生将能够：1.描述ADC0832芯片的结构、工作原理和性能特点；2.理解ADC0832在不同领域的应用，如模拟信号处理、数据采集等；3.掌握ADC0832的编程方法，包括初始化、数据采集、数据转换等；4.能够运用ADC0832芯片解决实际问题，如设计简单的数据采集系统。

二、教学内容本课程的教学内容主要包括以下几个部分：1.ADC0832芯片的基本原理：介绍ADC0832的结构、工作原理和性能特点，使学生了解其在电路设计中的应用背景；2.ADC0832的功能与应用：讲解ADC0832的各个引脚功能、工作模式，并通过实例分析其在不同领域的应用，如模拟信号处理、数据采集等；3.ADC0832的编程方法：详细介绍ADC0832的编程步骤、初始化过程以及数据采集、转换的方法，让学生能够熟练操作ADC0832芯片；4.实践项目：安排适量的实践项目，让学生动手设计并实现基于ADC0832的数据采集系统，巩固所学知识。

三、教学方法为了提高教学效果，本课程将采用多种教学方法相结合的方式，包括：1.讲授法：讲解ADC0832的基本原理、功能、应用和编程方法，使学生掌握课程的基本知识；2.案例分析法：通过分析实际案例，使学生更好地理解ADC0832的应用场景和编程技巧；3.实验法：安排实践项目，让学生动手操作ADC0832芯片，培养学生的实际动手能力；4.讨论法：学生进行小组讨论，分享学习心得和经验，提高学生的合作能力和沟通能力。

四、教学资源为了支持本课程的教学，我们将准备以下教学资源：1.教材：选用国内权威出版的ADC0832相关教材，作为学生学习的主要参考资料；2.参考书：推荐学生阅读一些与ADC0832相关的书籍，以拓宽知识面；3.多媒体资料：制作PPT、教学视频等多媒体资料，辅助学生更好地理解课程内容；4.实验设备：准备ADC0832芯片、开发板等实验设备，为学生提供动手实践的机会。

ADC0832的数字电压表设计说明

目录1. 引言 (1)2. 方案设计 (1)2.1设计要求 (1)2.2设计方案 (1)3. 硬件设计 (2)3.1单片机最小系统 (2)3.2显示驱动部分 (2)3.3转换电路 (3)3.4单片机驱动部分 (3)4. 软件设计 (4)4.1软件流程 (4)4.2子程序模板 (5)5实验结果与讨论 (5)5.1实验仿真 (5)5.2结果讨论 (5)6心得体会 (6)7参考文献 (13)8附录8.1程序 (7)8.2原理图 (7)1. 引言随着片机技术的飞速发展，，现代的电子产品几乎渗透到了社会的各个领域，有力地推动了社会生产力的发肢和社会信息化程度的提商，人们为了寻求最好的科技，为了方便人类在使用科技产品的快速性，准确性。

例如数字电压表能够准确的，快速的量出电压。

利用ADC0832和AT89C52的结合再通过LCD来显示出来。

ADC0832是一个8位D/A转换器。

单电源供电，从+5V〜+15V均可正常工作。

基准电压的围为土10V;电流建立时间为1卩S; CMOS：艺，低功耗20mWADC0832 转换器芯片为20引脚，双列直插式封装。

该转换器由输入寄存器和DAC寄存器构成两级数据输入锁存。

使用时数据输入可以采用两级锁存(双锁存)形式，或单级锁存(一级锁存，一级直通)形式，或直接输入(两级直通)形式。

2. 方案设计2.1设计要求按系统要实现功能，设计必须达到以下的几个步骤的要求(1)主电路系统是由ADC0832单片机AT89C52和LCD显示屏组成。

(2)ADC083是模拟数字转换芯片，是将外侧电压信号转换成数字信号再通过AT89C52处理，再通过LCD显示出来(3)能测量0-5V的数字电压(4)测量误差不大于0.1V2.2设计方案2.1.1 单片机的选择本设计选用单片机AT89C52它是一种带8K字节闪烁可编程可擦除只读存储器的低电压，足够本设计之用，高性能CMOS位微处理器该器件采用ATME高密度非易失存储器制造技术制造，与工业标准的MCS-51指令系统及8052产品引脚兼容,功能强大、使用方便的AT80C52单片机适用于许多较为复杂的应用场合。

ADC0832模数转换之5v内电压测量

void main(void) //入口函数
{
unsigned char i=0;
unsigned int tmp;
RST=0;
while(1)
{
if(i==0) //这里为循环255个周期读取一次0831，因CPU运行比较快，没必要每次循环都去读取
{
tmp=ad0832read(1,0)*100;//ad0832read函数里的两个参数代表的意义分别是：
ADC0832.c /*************************************************************************** 标题： ADC0832模数转换程序，电压表效果：调节模拟采集量电位器，数码管显示相应的分压。说明：做这个例子的朋友，先看完这段话，一定要看完再做实验。
0xbf,0x86,0xdb,0xcf,0xe6,0xed,0xfd,0x87,0xff,0xef, 0x40, 0x3e, 0x00};
"0-9"，第二行是"0-9且有小数点的" ，接下来三行分别是"-"、 "U" 、"空" unsigned char l_tmpdate[]={0,0,0,0}; //存放显示内容的数组
//第一个上升沿
SDA=SGL;_nop_();_nop_(); SCL=1;_nop_();_nop_(); SCL=0;_nop_();_nop_();
//输入数据SGL //第二个上升沿
SDA=ODD;_nop_();_nop_(); SCL=1;_nop_();_nop_(); SCL=0;_nop_();_nop_();

ADC0832驱动程序讲解

物理与电子工程系《电子设计与实践》
2011年春
（4）如资料所示，当此2 位数据为“1”、“0”时，只对 CH0 进行单通道转换。当2位数据为“1”、“1”时，只对 CH1进行单通道转换。当2 位数据为“0”、“0”时，将 CH0作为正输入端IN+，CH1作为负输入端IN-进行输入。当2 位数据为“0”、“1”时，将CH0作为负输入端IN-， CH1 作为正输入端IN+进行输入。
for(i=0;i<8;i++) { clk=1; _nop_();_nop_(); clk=0; _nop_();_nop_(); dat1=dat1<<1| (uchar)(dio); } for(i=0;i<8;i++) { dat2=dat2|((uchar)(dio)<<i); clk=1; _nop_();_nop_(); clk=0; _nop_();_nop_(); } cs=1; return (dat1==dat2)?dat1:0; }
1、建立连接，启动转换； 2、接收数据； 3、数据处理。
物理与电子工程系《电子设计与实践》
2011年春
二、C语言程序设计
1、建立连接，启动转换
ADC0832时序图
物理与电子工程系《电子设计与实践》 2011年春
2、接收数据
sbit cs=P1^0; sbit clk=P1^1; sbit dio=P1^2;
物理与电子工程系《电子设计与实践》
2011年春
MSB（Most Significant Bit），意为最高有效位； LSB（Least Significant Bit）。
ADC0832时序图

adc0832数字电压表(程序+仿真图)

adc0832数字电压表(程序+仿真图)仿真图：/*********************************包含头文件********************************/#include <reg51.h>#include <intrins.h>/*********************************端口定义**********************************/sbit CS = P3^5;sbit Clk = P3^3;sbit DATI = P3^4;sbit DATO = P3^4;sbit P20=P2^0 ;/*******************************定义全局变量********************************/unsigned char dat = 0x00; //AD值unsigned char count = 0x00; //定时器计数unsigned char CH; //通道变量unsigned char dis[] = {0x00, 0x00, 0x00}; //显示数值/*******************************共阳LED 段码表*******************************/unsigned char i,test,adval;adval = 0x00;test = 0x00;Clk = 0; //初始化DATI = 1;_nop_();CS = 0;_nop_();Clk = 1;_nop_();if ( CH == 0x00 ) //通道选择{Clk = 0;DATI = 1; //通道0的第一位_nop_();Clk = 1;_nop_();Clk = 0;DATI = 0; //通道0的第二位_nop_();Clk = 1;_nop_();}else{Clk = 0;DATI = 1; //通道1的第一位_nop_();Clk = 1;_nop_();Clk = 0;DATI = 1; //通道1的第二位_nop_();Clk = 1;_nop_();}Clk = 0;DATI = 1;for( i = 0;i < 8;i++ ) //读取前8位的值{_nop_();adval <<= 1;Clk = 1;_nop_();Clk = 0;if (DATO)adval |= 0x01;elseadval |= 0x00;}for (i = 0; i < 8; i++) //读取后8位的值{test >>= 1;if (DATO)test |= 0x80;elsetest |= 0x00;_nop_();Clk = 1;_nop_();Clk = 0;}if (adval == test) //比较前8位与后8位的值，如果不相同舍去。

基于ADC0832数字电压表

阿坝师范高等专科学校电子信息工程系课程设计基于ADC0832数字电压表学生姓名任银鹏专业名称电子信息工程技术班级电信班学号20113026基于ADC0832数字电压表一、设计要求设计一个在单片机AT89S52作用下基于ADC0832数字电压表.二、系统设计方案１. 模块图２. 模块作用该电压表由单片A/D转换器构成，在很大的电压情况下，电压表去测量时会对其并联很大的电阻分掉高压，然后再进行测量，这本来很大的电压，到后来测出来的电压就会很小，这就是A/D转换实现低压电压表测量高压三、硬件原理１.LCD1602图3.1 LCD1602外观如图3.1 LCD1602外观，从LCD1602参数手册知道芯片工作电压为4.5~5.5V,工作电流20mA。

模块最佳工作电压为5V。

引脚作用说明如下表3.1：表3.1引脚作用说明从参数手册知道LCD1602与单片机8051系列连接方式如图3.2所示，LCD1602引用电路如图3.3：图3.2 LCD1602与单片机8051系列连接方式图3.3 LCD1602引用电路如图3.3 LCD1602引用电路，单片机P2口与LCD1602的7-14脚连接，单片机14脚与LCD1602的6脚连接，单片机15脚与LCD1602的4脚连接。

２. ADC0832ADC0832具有8位分辨率;双通道A/D转换;输入输出电平与TTL/CMOS相兼容;5V电源供电时输入电压在0-5V之间,工作频率为250KHz,转换时间为32us;一般功耗仅为15Mw的特点。

ADC0832芯片引脚说明如图3.4：图3.4ADC0832芯片引脚说明:cs:片选使能，低电平芯片使能；cho：模拟输入通道0，或作为IN+/-使用；ch1：模拟输入通道:1，或作为IN+/-使用；GND：芯片参考0电位；DI：数据信号输入，悬着通道控制；DO：数据信号输出，转换数据输出；CLK:芯片时钟输入；Vcc/REF:电源输入及参考电压输入。

模数转换电路分析(ADC0832)18页

PSEN ALE EA
CH1 作为RV正2 输入端RINV1+进行输入。
96% 100%
10k
10k
1 2 3 4
CS CH0 CH1 GND
VCC CLK
DI DO
8 7 5 6
U2 ADC0832
+88.8
Volts
+88.8
Volts
1 2 3 4 5 6 7 8
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
（1）当要进行A/D转换时，须先将CS使能端置于低电平并且保持低电平直到转换完全结束。此时芯片开始转换工作；
（2）同时由处理器向芯片时钟输入端CLK 输入时钟脉冲，DO/DI端则使用DI端输入通道功能；
（3）在第1 个时钟脉冲的下沉之前DI端必须是高电平，表示启始信号。在第2、3个脉冲下沉之前 DI端应输入2 位数据用于选择通道功能；
模数转换（ADC0832）应用
一、 ADC0832介绍二、C语言程序设计三、实训
一、 ADC0832介绍
1、Feature
8-Bit Resolution; Easy Microprocessor interface or Stand-Alone Operation; Operates Ratiometrically or With 5-V Reference; Single Channel or Multiplexed Twin Channels With Single-Ended or Differential Input Options; Input Range 0 to 5 V With Single 5-V Supply; Inputs and Outputs Are Compatible With TTL and MOS Conversion Time of 32 ms at CLK = 250 kHz; Designed to Be interchangeable With National Semiconductor ADC0831 and ADC0832

ADC0832引脚图

adc0832引脚图:ADC0832 是美国国家半导体公司生产的一种8 位分辨率、双通道A/D转换芯片。

由于它体积小，兼容性强，性价比高而深受单片机爱好者及企业欢迎，其目前已经有很高的普及率。

学习并使用ADC0832 可是使我们了解A/D转换器的原理，有助于我们单片机技术水平的提高。

ADC0832 具有以下特点：· 8位分辨率；·双通道A/D转换；·输入输出电平与TTL/CMOS相兼容；· 5V电源供电时输入电压在0~5V之间；·工作频率为250KHZ，转换时间为32μS；·一般功耗仅为15mW；· 8P、14P—DIP（双列直插）、PICC 多种封装；·商用级芯片温宽为0°C to +70°C，工业级芯片温宽为−40°C to +85°C；芯片顶视图：（图1、图2）ADC0832程序:程序占用资源有累加器A，工作寄存器R7,通用寄存器B 和特殊寄存器CY。

通道功能寄存器和转换值共用寄存器B。

在使用转换子程序之前必须确定通道功能寄存器B 的值，其赋值语句为“MOV B,#data”（00H~03H）。

运行转换子程序后的转换数据值被放入B 中。

子程序退出后即可以对B 中数据处理。

ADC0832 芯片接口程序[汇编] ：/*------------------------------------------- 子程序名：ADC0832子程序编写人：杜洋初写时间：2005年10 月10日程序功能：将模拟电压量转换成数字量实现方法：串行通信。

CPU说明：MCS-51植入说明：占用A、B、CY、R7-------------------------------------------*/ ;以下接口定义根据硬件连线更改ADCS BIT P3.5 ;使能接口ADCLK BIT P3.4 ;时钟接口ADDO BIT P3.3 ;数据输出接口（复用）ADDI BIT P3.3 ;数据输入接口;以下语句在调用转换程序前设定MOV B,#00H ;装入通道功能选择数据值;以下为ADC0832读取数据子程序;==== ADC0832读数据子程序==== ADCONV:SETB ADDI ;初始化通道选择NOPNOPCLR ADCS ;拉低/CS端NOPNOPSETB ADCLK ;拉高CLK端NOPCLR ADCLK ;拉低CLK端,形成下降沿MOV A,BMOV C,ACC.1 ;确定取值通道选择MOV ADDI,CNOPNOPSETB ADCLK ;拉高CLK端NOPNOPCLR ADCLK ;拉低CLK端,形成下降沿2 MOV A,BMOV C,ACC.0 ;确定取值通道选择MOV ADDI,CNOPNOPSETB ADCLK ;拉高CLK端NOPNOPCLR ADCLK ;拉低CLK端,形成下降沿3 SETB ADDINOPNOPMOV R7,#8 ;准备送下后8个时钟脉冲AD_1:MOV C,ADDO ;接收数据MOV ACC.0,CRL A ;左移一次SETB ADCLKNOPCLR ADCLK ;形成一次时钟脉冲NOPNOPDJNZ R7,AD_1 ;循环8次MOV C,ADDO ;接收数据MOV ACC.0,CMOV B,AMOV R7,#8AD_13:MOV C,ADDO ;接收数据MOV ACC.0,CRR A ;左移一次SETB ADCLKNOPNOPCLR ADCLK ;形成一次时钟脉冲NOPNOPDJNZ R7,AD_13 ;循环8次CJNE A,B,ADCONV ;数据校验SETB ADCS ;拉高/CS端CLR ADCLK ;拉低CLK端SETB ADDO ;拉高数据端,回到初始状态RET;====子程序结束====。

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6.1。

3。

2 8位串行A/D 转换器ADC0832
1。

功能特点
ADC0832是NS （National Semiconductor)公司生产的串行接口8位A/D 转换器，通过三线接口与单片机连接,功耗低，性能价格比较高，适宜在袖珍式的智能仪器仪表中使用。

ADC0832 为8位分辨率A/D 转换芯片，其最高分辨可达256级,可以适应一般的模拟量转换要求。

芯片具有双数据输出可作为数据校验，以减少数据误差，转换速度快且稳定性能强。

独立的芯片使能输入，使多器件连接和处理器控制变得更加方便。

通过DI 数据输入端，可以轻易的实现通道功能的选择。

其主要特点如下：
● 8位分辨率，逐次逼近型,基准电压为5V; ● 5V 单电源供电；
● 输入模拟信号电压范围为0～5V ； ● 输入和输出电平与TTL 和CMOS 兼容；
● 在250KHZ 时钟频率时，转换时间为32us ； ● 具有两个可供选择的模拟输入通道； ● 功耗低，15mW 。

2.外部引脚及其说明
ADC0832有DIP 和SOIC 两种封装，DIP 封装的ADC0832引脚排列如图6。

21所示。

各引脚说明如下：
● CS ——片选端，低电平有效。

● CH0，CH1-—两路模拟信号输入端。

● DI ——两路模拟输入选择输入端。

● DO-—模数转换结果串行输出端。

● CLK ——串行时钟输入端。

● Vcc/REF ——正电源端和基准电压输入端。

● GND ——电源地。

3。

单片机对ADC0832 的控制原理
一般情况下ADC0832与单片机的接口应为4条数据线，分别是CS 、CLK 、DO 、DI 。

但由于DO 端与DI 端在通信时并未同时有效并与单片机的接口是双向的，所以电路设计时可以将DO 和DI 并联在一根数据线上使用。

当ADC0832未工作时其CS 输入端应为高电平，此时芯片禁用，CLK 和DO/DI 的电平可任意.当要进行A/D 转换时,须先将CS 端置于低电平并且保持低电平直到转换完全结束。

此时芯片开始转换工作，同时由处理器向芯片时钟输入端CLK 提供时钟脉冲，DO/DI 端则使用DI 端输入通道功能选择的数据信号。

在第1个时钟脉冲到来之前DI 端必须是高电平，表示启动位。

在第2、3个时钟脉冲到来之前DI 端应输入2位数据用于选择通道功能，其功能项见表6.4.
输入形式配置位选择通道
CH0 CH1 CHO CH1
差分输入 0 0 + —
0 1 - +
单端输入 1 0 + 1 1 +
如表6。

4所示，当配置位2位数据为1、0时，只对CH0 进行单通道转换。

当配置2位数据为1、1时，只对
CH1进行单通道转换。

当配置2位数据为0、0时，将CH0作为正输入端IN+，CH1作为负输入端IN-进行输入.当配置2位数据为0、1时，将CH0作为负输入端IN-，CH1 作为正输入端IN+进行输入。

到第3个时钟脉冲到来之后DI 端的输入电平就失去输入作用，此后DO/DI 端则开始利用数据输出DO 进行转换数据的读取。

从第4个时钟脉冲开始由DO 端输出转换数据最高位D7，随后每一个脉冲DO 端输出下一位数据。

直到第11个脉冲时发出最低位数据D0，一个字节的数据输出完成。

也正是从此位开始输出下一个相反字节的数据，即从第11个时钟脉冲输出D0.随后输出8位数据，到第19 个脉冲时数据输出完成,也标
图6.21 ADC0832引脚表6.4 ADC0832配置位
志着一次A/D 转换的结束。

最后将CS 置高电平禁用芯片,直接将转换后的数据进行处理就可以了。

图6.22为ADC0832时序图.
4.ADC0832典型应用
（1）单片机串行口方式0与ADC0832接口
AT89S51ADC0832
RXD
TXD P1.7CS CLK DO CH0CH1
DI
如图6。

23所示，AT89C51的P1。

7为片选信号端,TXD 是时钟信号输出端，RXD 为启动信号，模拟通道选择信号发送端以及A/D 转换后输出数据的接收端。

ADC0832的时钟频率最高为400KHZ ，单片机AT89C51晶振选用4MHZ,在TXD 端的输出频率为4MHZ/12=333KHZ ，符合要求。

ADC0832 输出的串行数据共15位，由两段8位数据组成,前一段是最高位在先，后一段是最高位在后,两段数据的最低位共用。

只有在时钟的下降沿，ADC0832的串行数据才移出一位。

由单片机控制时钟信号进行发送，并由TXD 发出,以达到控制ADC0832输出数据位的目的。

为了得到一列完整的8位数据，单片机分两次采集含有不同位的数据，再合成一列完整的8位数据。

当REN=0时，AT89C51连续一次向ADC0832发送8个时钟脉冲，前3个脉冲发送的是启动位和模拟通道选择位，共计3位；从第4个脉冲下降沿开始,ADC0832发出转换数据D7～D4(在脉冲上升沿单片机方可接收）。

但由于REN=0，单片机不予接收，丢失D7～D4数据。

当REN=1时，单片机又向ADC0832连续发出8个时钟脉冲，其输出转换数据D3，D2,D1，和d0，d1,d2，d3,d4,存入累加器A 形成如下结构: 累加器A
d4 d3 d2 d1 d0 D1 D2 D3
上述数据右移3位,并屏蔽掉高3位，暂存于寄存器B ，得到如下结构：寄存器B
0 0 0 d4 d3 d2 d1 d0
单片机第二次接收,可得到下列数据：累加器A
X X X X X d7 d6 d5
图6。

22 ADC0832时序
图6.23 ADC0832与单片
以上数据左移5位，并屏蔽低5位，送入累加器A ，得到如下结构: 累加器A
进行（A ）+(B ）→（A)运算，得到如下结构：累加器A
从而得到一个完整的8位A/D 转换结果.
根据图6。

23对CH1通道的模拟输入信号实行A/D 转换的程序如下:
CADA ： CLR P1.7 ；CS=0
MOV SCON,#00H ；串行口方式0，REN=0
MOV A ，＃07H ；通道配置位为11，启动位为1 MOV SBUF,A ；启动发送
LOOPA1: JNB T1, LOOPA1 ;发送等待
MOV SCON,＃10H ；REN=1,RI=0，启动接收
LOOPA2： JNB R1，LOOPA2 ；接受等待
MOV A ，SBUF RR A RR A RR A
ANL A ，＃1FH ；屏蔽高3位 MOV B,A
MOV SCON ，＃10H ；第二次启动接收
LOOPA3： JNB RI,LOOPA3
MOV A,SBUF RL A SWAP A
ANL A ，＃0E0H ADD A ，B SETB P1.7
RET
（2）SPI 串行接口方式
SPI 是MOTOROLA 公司推出的一种同步串行外设接口，允许MCU 也各个厂家生产工具的标准外围设备直接
接口，以串行方式交换信息.SPI 使用4条线与主机（MCU ）连接:串行时钟SCK ，主机输入/从机输出数据线SO ，主机输出/从机输入数据线SI 和低电平有效的从机选择线CS 。

SPI 串行扩展系统的主器件单片机,可以带有SPI 接口,也可以不带SPI 接口，但从器件必须具有SPI 接口。

AT89S51
ADC0832
P1.2P1.1P1.0CS CLK DO CH0CH1
DI P1.3
ADC0832具有SPI接口,图6。

24为AT89S51与ADC0832的SPI串行接口方式，将DO和DI分别连接于P1。

0和P1.1.对CH0通道的模拟信号进行A/D转换，转换结果存于累加器A中。

程序如下：
CADB: CLR P1。

3 ；CS=0
MOV A,#03H ；起始位和配置位为011
MOV R7,#03H
LOOPB1: CLR P1.2 ；CLK=0
RRC A
MOV P1.1,C
NOP
SETB P1.2 ；CLK=1
DJNZ R7，LOOPB1
CLR P1.2 ；通道稳定脉冲
NOP
SETB P1.2 ;CLK=1
MOV R7,#08H
LOOPB2: CLR P1.2 ;CLK=0
MOV C，P1.0 ；读入一位数据
RLC A
SETB P1。

2 ；CLK=1
DJNZ R7，LOOPB2
SETB P1.3 ；CS=1
RET。