CMOS大规模集成电路

CMOS VLSI Design
Slide 2
Power and Energy
Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: P(t ) iDD (t )VDD Energy:
32mA Pstatic I staticVDD 38mW
All devices exhibit gate leakage. On average, half the transistors are off.
18: Design for Low Power CMOS VLSI Design Slide 17
I pull-up b 2 24μA Ppull-up VDD I pull-up 29μW Pstatic (31 24) Ppull-up 1.6 mW
18: Design for Low Power CMOS VLSI Design Slide 14
Leakage Example
2
18: Design for Low Power
CMOS VLSI Design
Slide 11
Static Power
Static power is consumed even when chip is quiescent. – Ratioed circuits burn power in fight between ON transistors – Leakage draws power from nominally OFF devices
Introduction to CMOS VLSI Design
Lecture 18: Design for Low Power
Outline
Power and Energy Dynamic Power Static Power Low Power Design
18: Design for Low Power
18: Design for Low Power
CMOS VLSI Design
Slide 9
Dynamic Example
Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current.
18: Design for Low Power
CMOS VLSI Design
Slide 10
Dynamic Example
Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance.
Pdynamic 1 iDD (t )VDD dt T 0 VDD iDD (t )dt T 0 VDD TfswCVDD T CVDD 2 f sw
fsw
18: Design for Low Power CMOS VLSI DesignTTVDFra bibliotek iDD(t)
C
Slide 6
18: Design for Low Power
CMOS VLSI Design
Slide 13
Ratio Example
The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high Find static power drawn by the ROM – b = 75 mA/V2 – Vtp = -0.4V 2 Solution: VDD Vtp
180 10 4l 0.05mm / l 45.6 10 mm
6 6
I static 2.4 106 m m 20nA / m m / 2 3nA / m m
6
45.6 10 mm 0.02nA / mm / 2 0.002nA / mm
18: Design for Low Power
P aCVDD2 f dynamic
CMOS VLSI Design Slide 7
Short Circuit Current
When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are comparable for input and output
Activity Factor
Suppose the system clock frequency = f Let fsw = af, where a = activity factor – If the signal is a clock, a = 1 – If the signal switches once per cycle, a = ½ – Dynamic gates: • Switch either 0 or 2 times per cycle, a = ½ – Static gates: • Depends on design, but typically a = 0.1 Dynamic power:
Vgs Vt
I ds I ds 0e
nvT
Vds vT 1 e
Vt Vt 0 Vds
18: Design for Low Power

s Vsb s

Slide 12
CMOS VLSI Design
Ratio Example
The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high Find static power drawn by the ROM – b = 75 mA/V2 – Vtp = -0.4V
fsw
18: Design for Low Power CMOS VLSI Design
C
Slide 4
Dynamic Power Cont.
Pdynamic
VDD iDD(t)
fsw
18: Design for Low Power CMOS VLSI Design
C
Slide 5
Dynamic Power Cont.
18: Design for Low Power CMOS VLSI Design Slide 15
Leakage Example Cont.
Estimate static power:
18: Design for Low Power
CMOS VLSI Design
Slide 16
Leakage Example Cont.
The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage: – 20 nA/mm for low Vt – 0.02 nA/mm for high Vt Gate leakage: – 3 nA/mm for thin oxide – 0.002 nA/mm for thick oxide Memories use low-leakage transistors everywhere Gates use low-leakage transistors on 80% of logic
18: Design for Low Power
CMOS VLSI Design
Slide 8
Example
200 M transistor chip – 20M logic transistors • Average width: 12 l – 180M memory transistors • Average width: 4 l – 1.2 V 100 nm process – Cg = 2 fF/mm
Estimate static power: – High leakage: 20 106 0.2 12l 0.05mm / l 2.4 106 mm – Low leakage: 20 106 0.812l 0.05mm / l
32mA Pstatic I staticVDD 38mW
Leakage Example Cont.
Estimate static power: 6 6 – High leakage: 20 10 0.2 12l 0.05mm / l 2.4 10 mm – Low leakage: 20 106 0.812l 0.05mm / l