Lecture 1 Opamp Overview
t240xw01v1讲课讲稿
NO ItemCOVERCONTENTSRECORD OF REVISIONS1 GENERAL DESCRIPTION2 ABSOLUTE MAXIMUM RATINGS3 ELECTRICAL SPECIFICATION3-1 ELECTRICAL CHARACTERISTICS3-2 INTERFACE CONNECTIONS3-3 SIGNAL TIMING SPECIFICATIONS3-4 SIGNAL TIMING WAVEFORMS3-5 COLOR INPUT DATA REFERENCE3-6 POWER SEQUENCE3-7 BACKLIGHT SPECIFICATION4 OPTICAL SPECIFICATION5 MECHANICAL CHARACTERISTICS6 RELIABILITY TEST ITEMS7 INTERNATIONAL STANDARD7-1 EMC8 PACKING9 PRECAUTIONS9-1 MOUNTING PRECAUTIONS9-2 OPERATING PRECAUTIONS9-3 ELECTROSTATIC DISCHARGE CONTROL9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE9-5 STORAGE9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM 9-7 ADDITIONAL6. Raliability Test Items1 THB 3 50℃/80%, 72hrs2 TST3 0.5hr/-20℃,0.5hr/ 60℃,72 hrs3 Shock test3wave form :half sine waveshock level : 50G、20msdirection : ±x, ±y, ±zone time each direction4 Vibration test 3 Radom wave (1.5G RMS, 100—200Hz)30mins/Per each X.Y.Z axesPanel label:XXXXXXXXXXXX-ZM01XXXXXXXXXXXXXX: Panel Serial numberZM01: BVCH internal codeXX: 若头位为H，即为H?时表示BLU为BVCH自组，若为其他形式的数字或字符表示BLU 为AUO整组。
VCP6培训资料-M02_VirtualizationIntro
2-4
Lesson 1: Introduction to the SoftwareDefined Data Center
2-5
Learner Objectives
By the end of this lesson, you should be able to meet the following objectives:
Applications Operating System Physical Host
Ethernet
FCoE Storage
Fibre Channel
iSCSI Storage
NFrk
Fibre Channel Storage
2-7
VMware vSphere: Install, Configure, Manage
• •
Virtualization, VMware ESXi™, and the virtual machine The fundamental vSphere components and how vSphere can be used in the software-defined data center
2-8
About Virtual Machines
A virtual machine is a software computer that, like a physical computer, runs an operating system and applications.
Virtual Machine
Virtual Machines Hypervisor ESXi Host
Ethernet
FCoE Storage
Fibre Channel
IBM Spectrum Accelerate Overview
Ø 简化架构，减少管理人人员所需要的专业技能要求
Flat & Simple DC
Page 13
存储方案专家级课程
IBM Spectrum Family
Remote & Branch Office
Ø 适合于小小型环境的可靠存储
l 保证分支支机构业务运行行 l 可靠安全的备份和恢复机制 l 低成本的容灾
软件定义存储市场概览
Ø SDS市场有超过20个厂厂商
Software Defined Storage
Software Only
External Storage Pooling Internal & External Storage Pool
§ § § § § DataCore Software PernixData Sanbolic (Melio) Atlantis Computing IBM Elastic Storage
IBM Spectrum Protect
通过数据备份和恢复功能实现数据保护 控制平面
IBM Spectrum Control
对存储和数据的自动化控制和优化
Page 5
存储方案专家级课程
IBM Spectrum Family
XIV Gen3 集成系统 is …
已优化、高高性能的⺴网网络化硬件 XIV 软件(5639-YYB)
Appliance
Hyper Converged Appliance
Internal Storage Pooling
Storage Appliance
§ § § § § § § § § § § § § §
XIV SDS VMware VSAN EMC ScaleIO NetApp Edge HP Red Hat Microsoft Gridstore Swiftstack Scality CloudByte Nexenta Maxta Amplidata
微机原理与应用的英语
微机原理与应用的英语Introduction:- CPU (Central Processing Unit)- Memory (RAM and ROM)- Input and output devices- Storage devicesChapter 2: Microprocessor Architecture2.1 Overview of Microprocessors- Definition and functions of microprocessors- Different types of microprocessors2.2 Instruction Set Architecture- Types of instructions- Addressing modes2.3 Internal Architecture of Microprocessors- Overview of the internal structure of microprocessors - Registers and their functions- Control unit and ALU (Arithmetic and Logic Unit)3.1 Types of Memory- RAM (Random Access Memory)- ROM (Read-Only Memory)- Cache memory- Virtual memory3.2 Memory Organization and Interfacing- Memory organization techniques (byte addressing, word addressing)- Memory mapping and address decoding- Interfacing memory with microprocessorsChapter 4: Input and Output Systems4.1 Input Devices- Keyboard- Mouse- Scanner- Microphone4.2 Output Devices- Monitor- Printer- Speaker- Plotter4.3 I/O Interfaces- Serial and parallel interfaces- USB (Universal Serial Bus)- Ethernet5.1 Overview of Operating Systems- Definition and functions of operating systems- Types of operating systems (Windows, macOS, Linux) 5.2 Booting Process- POST (Power-On Self-Test)- Boot loader- Kernel initialization5.3 File Systems- FAT (File Allocation Table)- NTFS (New Technology File System)- EXT4 (Fourth Extended File System)6.1 Office Applications- Word processing- Spreadsheet- Presentation software- Image editing- Video editing- Audio editing6.3 Internet and Networking Applications - Web browsing- Email- Instant messaging6.4 Gaming and Entertainment Applications - PC games- Online gaming- Streaming servicesConclusion:。
SPICE实战手册
Perface最初写作本文的目的是希望提供一份中文版的Hspice手册从而方便初学者的使用，本文的缘起是几位曾经一起工作过的同事分别进入不同的新公司，而公司主要是使用Hspice，对于已经熟悉了Cadence 的GUI界面的使用者转而面对Hspice的文本格式，其难度是不言而喻的，而Hspice冗长的manual（长达2000页以上）更让人在短时间内理不出头绪。
鉴于我曾经使用过相当一段时间的Hspice，于是我向他们提供了一份简单而明了的handbook来帮助他们学习，本来是准备借助一个具体运放的设计例子，逐步完善成为一份case by case的教程，但由于工作比较浩大，加之时间的关系，一直难以完成，愈拖愈久，在几个朋友的劝说下，与其等其日臻完善后再发布，不如先行发布在逐步完善，以便可以让更多的朋友及早使用收益。
本文虽通过网络发表，但作者保留全部的著作权，转载时务请通知本人。
由于水平的有限，讨论范围的局限及错误不可避免，恳请读者指正。
联系方式为e-mail: *****************。
一、HSPICE基础知识Avant! Start-Hspice（现在属于Synopsys公司）是IC设计中最常使用的电路仿真工具，是目前业界使用最为广泛的IC设计工具，甚至可以说是事实上的标准。
目前，一般书籍都采用Level 2的MOS Mod el进行计算和估算，与Foundry经常提供的Level 49和Mos 9、EK V等Library不同，而以上Model要比Level 2的Model复杂的多，因此Designer除利用Level 2的Model进行电路的估算以外，还一定要使用电路仿真软件Hspice、Spectre等进行仿真，以便得到精确的结果。
本文将从最基本的设计和使用开始，逐步带领读者熟悉Hspice的使用，并对仿真结果加以讨论，并以一个运算放大器为例，以便建立I C设计的基本概念。
在文章的最后还将对Hspice的收敛性做深入细致的讨论。
Ovation I O Reference Manual
This publication adds the Eight Channel RTD module to the Ovation I/O Reference Manual. It should be placed between Sections 19 and 20.Date: 04/03IPU No.243Ovation ® Interim Publication UpdatePUBLICATION TITLEOvation I/O Reference ManualPublication No. R3-1150Revision 3, March 2003Section 19A. Eight Channel RTDModule19A-1. DescriptionThe Eight (8) channel RTD module is used to convert inputs from Resistance Temperature Detectors (RTDs) to digital data. The digitized data is transmitted to the Controller.19A-2. Module Groups19A-2.1. Electronics ModulesThere is one Electronics module group for the 8 channel RTD Module:n5X00119G01 converts inputs for all ranges and is compatible only with Personality module 5X00121G01 (not applicable for CE Mark certified systems).19A-2.2. Personality ModulesThere is one Personality module groups for the 8 channel RTD Module:n5X00121G01 converts inputs for all ranges and is compatible only with Electronics module 5x00119G01 (not applicable for CE Mark certified systems).19A-2.3. Module Block Diagram and Field Connection WiringDiagramThe Ovation 8 Channel RTD module consists of two modules an electronics module contains a logic printed circuit board (LIA) and a printed circuit board (FTD). The electronics module is used in conjunction with a personalty module, which contains a single printed circuit board (PTD). The block diagram for the 8 channel RTD moduleis shown in Figure 19A-1.Table 19A-1. 8 Channel RTD Module Subsystem ChannelsElectronic Module Personality Module85X00119G015X00121G01Figure 19A-1. 8 Channel RTD Module Block Diagram and Field Connection Wiring Diagram19A-3. SpecificationsElectronics Module (5X00119)Personality Module (5X00121)Table 19A-2. 8 Channel RTD Module SpecificationsDescription ValueNumber of channels8Sampling rate50 HZ mode: 16.67/sec. normally. In 3 wire mode, leadresistance measurement occurs once every 6.45 sec.during which the rate drops to 3/sec.60 HZ mode: 20/sec. normally. In 3 wire mode, leadresistance measurement occurs once every 6.45 sec.during which the rate drops to 2/sec.Self Calibration Mode: Occurs on demand only. The ratedrops to 1/sec. once during each self calibration cycle.RTD ranges Refer to Table 19A-3.Resolution12 bitsGuaranteed accuracy (@25°C)0.10% ±[0.045 (Rcold/Rspan)]% ± [((Rcold + Rspan)/4096 OHM)]% ± [0.5 OHM/Rspan]% ±10 m V ± 1/2LSBwhere:Rcold and Rspan are in Ohms.Temperature coefficient 10ppm/°CDielectric isolation:Channel to channel Channel to logic 200V AC/DC 1000 V AC/DCInput impedance100 M OHM50 K OHM in power downModule power 3.6 W typical; 4.2 W maximumOperating temperature range0 to 60°C (32°F to 140°F)Storage temperature range-40°C to 85°C (-40°F to 185°F)Humidity (non-condensing)0 to 95%Self Calibration On Demand by Ovation ControllerCommon Mode Rejection120 dB @ DC and nominal power line frequency+/- 1/2%Normal Mode Rejection100 dB @ DC and nominal power line frequency+/- 1/2%Table 19A-3. 8 Channel RTD RangesScale #(HEX)Wires Type Tempo FTempo CRcold(ohm)Rhot(ohm)Excitationcurrent(ma)Accuracy± ±countsAccuracy± ±% ofSPAN1310OhmPL0 to1200–18 t o6496106.3 1.090.222310OhmCU 0 to302–18 t o1508.516.5 1.0 130.32D350OhmCU 32 to2840 to1405080 1.0110.2711350OhmCU 32 to2300 to1105378 1.0120.30193100Ohm PL –4 to334–16 t o16892163.671.0110.27223100Ohm PL 32 to5200 to269100200 1.0100.25233100Ohm PL 32 to10400 to561100301 1.0100.25253120Ohm NI –12 t o464–11 t o240109360 1.0100.25263120Ohm NI 32 to1500 to70120170 1.0130.32283120Ohm NI 32 to2780 to122120225 1.0110.27804100Ohm PL 32 to5440 to290100 208 1.0100.25814100Ohm PL 356 t o446180 t o230168 186 1.0300.74824200Ohm PL 32 to6980 to370200 473 1.0120.30834200Ohm PL 514 t o648268 t o342402452 1.0290.71844100Ohm PL 32 to1240 to51100120 1.0190.47854100Ohm PL 32 to2170 to103100 140 1.0130.3286 4100Ohm PL 32 to4120 to211100 180 1.0110.27874100Ohm PL 32 to7140 to379100 240 1.0100.25884120Ohm PL 511 t o662266 t o350200230 1.0240.5919A-4. 8 Channel RTD Terminal Block Wiring Information19A-4.1. Systems Using Personality Module 5X00121G01 Each Personality module has a simplified wiring diagram label on its side, which appears above the terminal block. This diagram indicates how the wiring from the field is to beconnected to the terminal block in the base unit. The following table lists and defines the abbreviations used in this diagram.Table 19A-4. Abbreviations Used in the DiagramAbbreviation Definition+IN, -IN Positive and negative sense input connectionEarth ground terminal. Used for landing shields when the shield is to begrounded at the module.PS+, PS-Auxiliary power supply terminals.RTN Return for current source connection.SH Shield connector. used for landing shields when the shield is to begrounded at the RTD.SRC Current source connection.Note:PS+ and PS- are not used by this module.19A-5. 8 Channel RTD Module Address Locations19A-5.1. Configuration and Status RegisterWord address 13 (D in Hex) is used for both module configuration and module status. The Module Status Register has both status and diagnostic information. The bit information contained within these words is shown in Table 19A-5.Definitions for the Configuration/Module Status Register bits:Bit 0:This bit configures the module (write) or indicates the configuration state of the module (read). A “1” indicates that the module is configured. Note that until the module is configured, reading from addresses #0 through #11 (B in Hex) will produce an attention status.Bit 1:This bit (write “1”) forces the module into the error state, resulting in the error LED being lit. The read of bit “1” indicates that there is an internal module error,or the controller has forced the module into the error state. The state of this bit is always reflected by the module’s Internal Error LED. Whenever this bit is set,an attention status is returned to the controller when address #0 through #11(B in Hex) are read.Table 19A-5. 8 Channel RTD Configuration/Status Register (Address 13 0xD in Hex)Bit Data Description -Configuration Register (Write)Data Description -Status Register (Read)0Configure Module Module Configured(1 = configured; 0 = unconfigured)1Force errorInternal or forced error(1 = forced error; 0 = no forced error)250/60 Hz select (0 = 60Hz, 1 = 50Hz)50/60 Hz System (1 = 50Hz) d(read back)3SELF_CAL (Initiates Self Calibration)Warming bit (set during power up or configuration)40050060Module Not Calibrated 708CH.1 _ 3/4 Wire.CH.1 _ 3/4 Wire - Configuration (read back)9CH.2 _ 3/4 Wire.CH.2 _ 3/4 Wire - Configuration (read back)10CH.3 _ 3/4 Wire.CH.3 _ 3/4 Wire - Configuration (read back)11CH.4 _ 3/4 Wire.CH.4 _ 3/4 Wire - Configuration (read back)12CH.5 _ 3/4 Wire.CH.5 _ 3/4 Wire - Configuration (read back)13CH.6 _ 3/4 Wire.CH.6 _ 3/4 Wire - Configuration (read back)14CH.7 _ 3/4 Wire.CH.7 _ 3/4 Wire - Configuration (read back)15CH.8 _ 3/4 Wire.CH.8 _ 3/4 Wire - Configuration (read back)Bit 2:The status of this bit (read) indicates the conversion rate of the module, write to this bit configures the conversion rate of A/D converters as shown below.see Table 19A-6.Bit3:Write: This bit is used to initiate self-calibration. Read: This bit indicates that the module is in the “Warming” state. this state exists after power up and ter-minates after 8.16 seconds. the module will be in the error condition during the warm up period.Bit4 & 5:These bits are not used and read as “0” under normal operation.Bit 6:This bit (read) is the result of a checksum test of the EEPROM. A failure of this test can indicate a bad EEPROM, but it typically indicates that the module has not been calibrated. A “0” indicates that there is no error condition. If an error is present, the internal error LED is lit and attention status will be returned for all address offsets 0-11 (0x0 - 0xB). The “1” state of this bit indicates an unre-coverable error condition in the field.Bit 7:This bits is not used and read as “0” under normal operation.Bit 8 - 15:These bits are used to configure channels 1 - 8 respectively for 3 or 4 wire op-eration. A “0” indicates 3 wire and a “1” indicates 4 wire operation, see Table 19A-7 and Table 19A-8).Word address 12 (0xC) is used to configure the appropriate scales for Channels 1 - 4 (refer to Table 19A-7 and Table 19A-8).Table 19A-6. Conversion Rate Conversion Rate (1/sec.)Bit 260 (for 60Hz systems)050 (for 50Hz systems)1Table 19A-7. Data Format for the Channel Scale Configuration Register(0xC)Bit Data Description Configuration (Write)Data Description Status (Read)0 Configure Channel #1scale - Bit 0Channel #1 scale configuration (read back) - Bit 01Configure Channel #1scale - Bit 1Channel #1 scale configuration (read back) - Bit 12Configure Channel #1scale - Bit 2Channel #1 scale configuration (read back) - Bit 23Configure Channel #1scale - Bit 3Channel #1 scale configuration (read back) - Bit 34Configure Channel #2 scale - Bit 0Channel #2 scale configuration (read back) - Bit 05Configure Channel #2 scale - Bit 1Channel #2 scale configuration (read back) - Bit 16Configure Channel #2 scale - Bit 2Channel #2 scale configuration (read back) - Bit 27Configure Channel #2 scale - Bit 3Channel #2 scale configuration (read back) - Bit 38Configure Channel #3 scale - Bit 0Channel #3 scale configuration (read back) - Bit 09Configure Channel #3 scale - Bit 1Channel #3 scale configuration (read back) - Bit 1Caution:Configuring any or all channel scales while the system is running will cause all channels to return attention status for up to two seconds following the reconfiguration.Caution:Configuring any or all channel scales while the system is running will cause all channels to return attention status for up to two seconds following the reconfiguration.10Configure Channel #3 scale - Bit 2Channel #3 scale configuration (read back) - Bit 211Configure Channel #3 scale - Bit 3Channel #3 scale configuration (read back) - Bit 312Configure Channel #4 scale - Bit 0Channel #4 scale configuration (read back) - Bit 013Configure Channel #4 scale - Bit 1Channel #4 scale configuration (read back) - Bit 114Configure Channel #4 scale - Bit 2Channel #4 scale configuration (read back) - Bit 215Configure Channel #4 scale - Bit 3Channel #4 scale configuration (read back) - Bit 3Table 19A-8. Data Format for the Channel Scale Configuration Register(0xE)Bit Data Description Configuration (Write)Data Description Status (Read)0 Configure Channel #5 scale - Bit 0Channel #5 scale configuration (read back) - Bit 01Configure Channel #5 scale - Bit 1Channel #5 scale configuration (read back) - Bit 12Configure Channel #5 scale - Bit 2Channel #5 scale configuration (read back) - Bit 23Configure Channel #5 scale - Bit 3Channel #5 scale configuration (read back) - Bit 34Configure Channel #6 scale - Bit 0Channel #6 scale configuration (read back) - Bit 05Configure Channel #6 scale - Bit 1Channel #6 scale configuration (read back) - Bit 16Configure Channel #6 scale - Bit 2Channel #6 scale configuration (read back) - Bit 27Configure Channel #6 scale - Bit 3Channel #6 scale configuration (read back) - Bit 38Configure Channel #7 scale - Bit 0Channel #7 scale configuration (read back) - Bit 09Configure Channel #7 scale - Bit 1Channel #7 scale configuration (read back) - Bit 110Configure Channel #7 scale - Bit 2Channel #7 scale configuration (read back) - Bit 211Configure Channel #7 scale - Bit 3Channel #7 scale configuration (read back) - Bit 312Configure Channel #8 scale - Bit 0Channel #8 scale configuration (read back) - Bit 013Configure Channel #8 scale - Bit 1Channel #8 scale configuration (read back) - Bit 114Configure Channel #8 scale - Bit 2Channel #8 scale configuration (read back) - Bit 215Configure Channel #8 scale - Bit 3Channel #8 scale configuration (read back) - Bit 3Table 19A-7. Data Format for the Channel Scale Configuration Register(0xC)19A-6. Diagnostic LEDsTable 19A-9. 8 Channel RTD Diagnostic LEDsLED DescriptionP (Green)Power OK LED. Lit when the +5V power is OK.C (Green)Communications OK LED. Lit when the Controller is communicatingwith the module.I (Red)Internal Fault LED. Lit whenever there is any type of error with themodule except to a loss of power. Possible causes are:n - Module initialization is in progress.n - I/O Bus time-out has occurred.n - Register, static RAM, or FLASH checksum error.n - Module resetn - Module is uncalibrated.n - Forced error has been received from the Controllern - Communication between the Field and Logic boards failedCH1 - CH 8 (Red)Channel error. Lit whenever there is an error associated with a channel or channels. Possible causes are:n - Positive overrangen - Negative overrangen Communication with the channel has failed。
运算放大器原理
运算放大器原理，集成运算放大器原理运算放大器原理运算放大器（Operational Amplifier,简称OP、OPA、OPAMP）是一种直流耦合﹐差模（差动模式）输入、通常为单端输出（Differential-in, single-ended output）的高增益（gain）电压放大器，因为刚开始主要用于加法，乘法等运算电路中，因而得名。
一个理想的运算放大器必须具备下列特性：无限大的输入阻抗、等于零的输出阻抗、无限大的开回路增益、无限大的共模排斥比的部分、无限大的频宽。
最基本的运算放大器如图1-1。
一个运算放大器模组一般包括一个正输入端(OP_P)、一个负输入端(OP_N)和一个输出端(OP_O)。
图1-1通常使用运算放大器时，会将其输出端与其反相输入端（inverting input node）连接，形成一负反馈（negative feedback）组态。
原因是运算放大器的电压增益非常大，范围从数百至数万倍不等，使用负反馈方可保证电路的稳定运作。
但是这并不代表运算放大器不能连接成正回馈（positive feedback），相反地，在很多需要产生震荡讯号的系统中，正回馈组态的运算放大器是很常见的组成元件。
开环回路图1-2开环回路运算放大器开环回路运算放大器如图1-2。
当一个理想运算放大器采用开回路的方式工作时，其输出与输入电压的关系式如下：V out = ( V+ -V-) * Aog其中Aog代表运算放大器的开环回路差动增益（open-loop differential gai由于运算放大器的开环回路增益非常高，因此就算输入端的差动讯号很小，仍然会让输出讯号「饱和」（saturation），导致非线性的失真出现。
因此运算放大器很少以开环回路出现在电路系统中，少数的例外是用运算放大器做比较器（comparator），比较器的输出通常为逻辑准位元的「0」与「1」。
闭环负反馈将运算放大器的反向输入端与输出端连接起来，放大器电路就处在负反馈组态的状况，此时通常可以将电路简单地称为闭环放大器。
withanemphasison
MSU NSCL DAQ School—Notre Dame 2006
More to Read
• MSU NSCL DAQ:
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– Tree parameter GUI for powerful manipulation of the definition of parameters, spectra, variables, and gates
– Xamine for easy display and operations of histograms – Tcl/Tk for user-tailorable control GUI and easy extension of
SpectroDaq Data Server
SpecTcl Xamine
Scalers
Scaler Configuration
offline analysis
MSU NSCL DAQ School—Notre Dame 2006
Disk
Hardware Setup
¾ Caen v785, 32-ch ADC ¾ Caen v775, 32-ch TDC ¾ Caen v830, 32-ch Scaler ¾ Trigger to be upgraded
• SpecTcl
– Home: /daq/spectcl/ – Project: /projects/nsclspectcl – Tree Parameters:
/daq/spectcl/treeparam/TreeParameter.html – Tcl/Tk: /
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OPAMP Design
I. Opamp Overview
Outline ▪What’s Opamp?
▪Figures of Merit
▪Application of Opamp
▪MOSFET Circuit Review
▪One-Stage Opamp
▪Homework
What’s Opamp?
Opamp(operational amplifier)
Vip
A Vo
Vim
Vo = A* (Vip-Vim)
Figures of Merit A“Good”Opamp
rge voltage gain
2.High speed(large bandwidth)
3.Input current=0(infinite input impedance)
4.Low noise
5.Low power
6.……
Amplifier
Offer steady closed-loop gain
Voltage Follower(buffer) Reduce output impedance
LDO(Voltage Regulator)
Vref
A
Vout
R1
R2
Integrator
Differentiator
Low-Pass Filter
Current Mirror
）λ1（)()(k'211211
DS t GS D REF V V V L
W I I +-==R
V V I I GS DD REF
D 11-=
=The drain of Q1 is shorted to its gate, so it operates in the saturation region.
）λ1（)()(k 21222'2
DS t GS D o V V V L
W I I +-==）
λ1（*)/(）
λ1（*)/(1122DS DS REF O V L W V L W I I ++=
Common-Source Amplifier with Active Load
Common-Source Amplifier with Active Load
where,V GS−V TH=
2I D W
Lμn C ox
Source
Follower
R out=
v x
i x
|v
in=0
G m=
i out
v in
|v
out=0
Common-Gate Amplifier
CS-CG Amplifier
v i
v o
v b
M1
M2
A v=−
g m1
g ds1
∗
g m2
g ds2
DC gain around40dB
GBW:product of gain andωp
Common-mode Input Range To bias M1,M2,M5in saturation region.
Common-mode Input Range To bias M1,M2,M3in saturation region.
CMRR(Common-mode Rejection Ratio)
Definition:CMRR=|A dm|
|A cm|=|G dm|
|G cm|
CMRR(Common-mode Rejection Ratio)
CMRR(Common-mode Rejection Ratio)
CMRR(Common-mode Rejection Ratio)
i o is caused by mismatches between i1&i2,i3&i4.(Systematic error)
Calculate the output impedance of the circuit below. Assume g m1,g m2,g ds1and g ds2are known.
The gain of the error amplifier is A.
Calculate the transfer function of the circuit below. Assume g m1and g ds1are known.
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