K1S3216B1C中文资料

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C1608C0G1H331J资料

REMINDERSPlease read this before using the product.SAFETY REMINDERSREMINDERS1. If you intend to use a product listed in this catalog for a purpose that may cause loss of life or other damage, you must contact our company’s sales window.2. We may modify products or discontinue production of a product listed in this catalog without prior notification.3. We provide “Delivery Specification” that explain precautions for the specifications and safety of each product listed in this cata-log. We strongly recommend that you exchange these delivery specifications with customers that use one of these products.4. If you plan to export a product listed in this catalog, keep in mind that it may be a restricted item according to the “Foreign Exchange and Foreign Trade Control Law”. In such cases, it is necessary to acquire export permission in harmony with this law.5. Any reproduction or transferring of the contents of this catalog is prohibited without prior permission from our company.6. We are not responsible for problems that occur related to the intellectual property rights or other rights of our company or a third party when you use a product listed in this catalog. We do not grant license of these rights.7. This catalog only applies to products purchased through our company or one of our company’s official agencies. This catalog does not apply to products that are purchased through other third parties.8. The descriptions in this catalog apply as of April 2007.General Multilayer Ceramic Chip Capacitors C Series C1608 (EIA CC0603) TypeFEATURES•High capacitance has been achieved through precision technologies that enable the use of multiple thinner ceramic dielectric layers.• A monolithic structure ensures superior mechanical strength and reliability.•High-accuracy automatic mounting is facilitated through the maintenance of very precise dimensional tolerances.•Composed of only ceramics and metals, these capacitors provide extremely dependable performance, exhibiting virtually no degradation even when subjected to temperature extremes.•Low stray capacitance ensures high conformity with nominal values, thereby simplifying the circuit design process.•Low residual inductance assures superior frequency characteristics.•Because electrostatic capacity has been obtained up to the electrolytic capacitor range, these capacitors offer long service life and are optimally suited for power supply designs that require high levels of reliability.•Owing to their low ESR and excellent frequency characteristics, these products are optimally suited for high frequency and high-density type power supplies.SHAPES AND DIMENSIONS PRODUCT IDENTIFICATION(1) Series name(2) Dimensions L×W(3) Capacitance temperature characteristicsClass 1 (T emperature compensation)Class 2 (T emperature stable and general purpose)(4) Rated voltage Edc(5) Nominal capacitanceThe capacitance is expressed in three digit codes and in units of pico farads (pF).The first and second digits identify the first and second significant figures of the capacitance.The third digit identifies the multiplier.R designates a decimal point.(6) Capacitance tolerance(7) Packaging styleConformity to RoHS DirectiveC1608CH1H100D(1)(2)(3)(4)(5)(6)(7)1608 1.6×0.8mmT emperaturecharacteristicsCapacitance change Temperature rangeCH0±60ppm/°C–25 to +85°CSL+350 to –1000ppm/°C+20 to +85°CT emperaturecharacteristicsCapacitance change Temperature rangeJB±10%–25 to +85°CJF+30, –80%–25 to +85°CX7R±15%–55 to +125°CX5R±15%–55 to +85°CY5V+22, –82%–30 to +85°C1A10V1C16V1H50V0101pF10010pF1021,000pF0R50.5pFSymbol T oleranceApplicable capacitancerangeC±0.25pF10pF or lessJ±5%Over 10pFK±10%Z+80, –20%T T aping (reel)B Bulk•Conformity to RoHS Directive: This means that, in conformity with EU Directive 2002/95/EC, lead, cadmium, mercury, hexavalent chromium, and specific bromine-based flame retardants, PBB and PBDE, have not been used, except for exempted applications.CAPACITANCE RANGES: CLASS 1 (TEMPERATURE COMPENSATION)TEMPERATURE CHARACTERISTICS: CH(0±60ppm/°C), C0G(0±30ppm/°C)RATED VOLTAGE Edc: 50V TEMPERATURE CHARACTERISTICS: SL(+350 to –1000ppm/ )RATED VOLTAGE Edc: 10VCAPACITANCE RANGES: CLASS 2TEMPERATURE CHARACTERISTICS: JB(±10%), X5R/X7R(±15%)RATED VOLTAGE Edc: 50VCapacitance(pF)ToleranceThickness T (mm)Part No.T emperature characteristics: CH T emperature characteristics: C0G 0.5 ±0.25pF 0.8±0.10C1608CH1H0R5C C1608C0G1H0R5C 0.75 ±0.25pF 0.8±0.10C1608CH1HR75C C1608C0G1HR75C 1 ±0.25pF 0.8±0.10C1608CH1H010C C1608C0G1H010C 1.5 ±0.25pF 0.8±0.10C1608CH1H1R5C C1608C0G1H1R5C 2 ±0.25pF 0.8±0.10C1608CH1H020C C1608C0G1H020C 3 ±0.25pF 0.8±0.10C1608CH1H030C C1608C0G1H030C 4 ±0.25pF 0.8±0.10C1608CH1H040C C1608C0G1H040C 5 ±0.25pF 0.8±0.10C1608CH1H050C C1608C0G1H050C 6 ±0.5pF 0.8±0.10C1608CH1H060D C1608C0G1H060D 7 ±0.5pF 0.8±0.10C1608CH1H070D C1608C0G1H070D 8 ±0.5pF 0.8±0.10C1608CH1H080D C1608C0G1H080D 9 ±0.5pF 0.8±0.10C1608CH1H090D C1608C0G1H090D 10 ±0.5pF 0.8±0.10C1608CH1H100D C1608C0G1H100D 12 ±5%0.8±0.10C1608CH1H120J C1608C0G1H120J 15 ±5%0.8±0.10C1608CH1H150J C1608C0G1H150J 18 ±5%0.8±0.10C1608CH1H180J C1608C0G1H180J 22 ±5%0.8±0.10C1608CH1H220J C1608C0G1H220J 27 ±5%0.8±0.10C1608CH1H270J C1608C0G1H270J 33 ±5%0.8±0.10C1608CH1H330J C1608C0G1H330J 39 ±5%0.8±0.10C1608CH1H390J C1608C0G1H390J 47 ±5%0.8±0.10C1608CH1H470J C1608C0G1H470J 56 ±5%0.8±0.10C1608CH1H560J C1608C0G1H560J 68 ±5%0.8±0.10C1608CH1H680J C1608C0G1H680J 82 ±5%0.8±0.10C1608CH1H820J C1608C0G1H820J 100 ±5%0.8±0.10C1608CH1H101J C1608C0G1H101J 120±5%0.8±0.10C1608CH1H121J C1608C0G1H121J 150 ±5%0.8±0.10C1608CH1H151J C1608C0G1H151J 180±5%0.8±0.10C1608CH1H181J C1608C0G1H181J 220 ±5%0.8±0.10C1608CH1H221J C1608C0G1H221J 270±5%0.8±0.10C1608CH1H271J C1608C0G1H271J 330 ±5%0.8±0.10C1608CH1H331J C1608C0G1H331J 390±5%0.8±0.10C1608CH1H391J C1608C0G1H391J 470 ±5%0.8±0.10C1608CH1H471J C1608C0G1H471J 560±5%0.8±0.10C1608CH1H561J C1608C0G1H561J 680 ±5%0.8±0.10C1608CH1H681J C1608C0G1H681J 820±5%0.8±0.10C1608CH1H821J C1608C0G1H821J 1,000 ±5%0.8±0.10C1608CH1H102J C1608C0G1H102J 1,500 ±5%0.8±0.10C1608CH1H152J C1608C0G1H152J 2,200 ±5%0.8±0.10C1608CH1H222J C1608C0G1H222J 3,300 ±5%0.8±0.10C1608CH1H332JC1608C0G1H332JCapacitance (pF)Tolerance Thickness T (mm)Part No.T emperature characteristics: SL 15,000±5%0.80±0.10C1608SL1A153J 22,000±5%0.80±0.10C1608SL1A223JCapacitance(pF)ToleranceThickness T (mm)Part No.T emperature characteristics: JB T emperature characteristics: X5R Temperature characteristics: X7R 10,000 ±10%0.8±0.10C1608JB1H103KC1608X5R1H103K C1608X7R1H103K15,000 ±10%0.8±0.10C1608JB1H153KC1608X5R1H153K C1608X7R1H153K 22,000 ±10%0.8±0.10C1608JB1H223K C1608X5R1H223K C1608X7R1H223K 33,000 ±10%0.8±0.10C1608JB1H333KC1608X5R1H333K C1608X7R1H333K 47,000 ±10%0.8±0.10C1608JB1H473KC1608X5R1H473K C1608X7R1H473K 68,000 ±10%0.8±0.10C1608JB1H683KC1608X5R1H683K C1608X7R1H683K 100,000±10%0.8±0.10C1608JB1H104K C1608X5R1H104K C1608X7R1H104K ±20%0.8±0.10C1608JB1H104MC1608X5R1H104MC1608X7R1H104MRATED VOLTAGE Edc: 16VTEMPERATURE CHARACTERISTICS: JB(±10%), X5R(±15%)RATED VOLTAGE Edc: 25VRATED VOLTAGE Edc: 16VRATED VOLTAGE Edc: 10VRATED VOLTAGE Edc: 6.3VTEMPERATURE CHARACTERISTICS: JF(+30, –80%), Y5V(+22, –82%)RATED VOLTAGE Edc: 50VT emperature characteristics: JB T emperature characteristics: X5R Temperature characteristics: X7R 150,000 ±10%0.8±0.10C1608JB1E154K C1608X5R1E154K C1608X7R1E154K ±20%0.8±0.10C1608JB1E154M C1608X5R1E154M C1608X7R1E154M 220,000 ±10%0.8±0.10C1608JB1E224K C1608X5R1E224K C1608X7R1E224K ±20%0.8±0.10C1608JB1E224M C1608X5R1E224M C1608X7R1E224M 330,000±10%0.8±0.10C1608JB1E334K C1608X5R1E334K C1608X7R1E334K ±20%0.8±0.10C1608JB1E334MC1608X5R1E334MC1608X7R1E334MCapacitance (pF)Tolerance Thickness T (mm)Part No.T emperature characteristics: JB T emperature characteristics: X5R Temperature characteristics: X7R 470,000 ±10%0.8+0.15, –0.1C1608JB1C474K C1608X5R1C474K C1608X7R1C474K ±20%0.8+0.15, –0.1C1608JB1C474M C1608X5R1C474M C1608X7R1C474M 680,000 ±10%0.8+0.15, –0.1C1608JB1C684K C1608X5R1C684K C1608X7R1C684K ±20%0.8+0.15, –0.1C1608JB1C684M C1608X5R1C684M C1608X7R1C684M 1,000,000±10%0.8+0.2, –0.1C1608JB1C105K C1608X5R1C105K C1608X7R1C105K ±20%0.8+0.2, –0.1C1608JB1C105MC1608X5R1C105MC1608X7R1C105MCapacitance (pF)Tolerance Thickness T (mm)Part No.T emperature characteristics: JB T emperature characteristics: X5R 470,000±10%0.80±0.10C1608JB1E474K C1608X5R1E474K ±20%0.80±0.10C1608JB1E474M C1608X5R1E474M 680,000±10%0.80±0.10C1608JB1E684K C1608X5R1E684K ±20%0.80±0.10C1608JB1E684M C1608X5R1E684M 1,000,000±10%0.80±0.10C1608JB1E105K C1608X5R1E105K ±20%0.80±0.10C1608JB1E105MC1608X5R1E105MCapacitance (pF)Tolerance Thickness T (mm)Part No.T emperature characteristics: JB T emperature characteristics: X5R 1,500,000 ±10%0.8±0.10C1608JB1C155K C1608X5R1C155K ±20%0.8±0.10C1608JB1C155M C1608X5R1C155M 2,200,000±10%0.8±0.10C1608JB1C225K C1608X5R1C225K ±20%0.8±0.10C1608JB1C225MC1608X5R1C225MCapacitance (pF)Tolerance Thickness T (mm)Part No.T emperature characteristics: JB T emperature characteristics: X5R 3,300,000 ±10%0.8±0.10C1608JB1A335K C1608X5R1A335K ±20%0.8±0.10C1608JB1A335M C1608X5R1A335M 4,700,000±10%0.8±0.10C1608JB1A475K C1608X5R1A475K ±20%0.8±0.10C1608JB1A475MC1608X5R1A475MCapacitance (pF)Tolerance Thickness T (mm)Part No.T emperature characteristics: JB T emperature characteristics: X5R 6,800,000 ±10%0.80+0.15,–0.10C1608JB0J685K C1608X5R0J685K ±20%0.80+0.15,–0.10C1608JB0J685M C1608X5R0J685M 10,000,000±10%0.80+0.15,–0.10C1608JB0J106K C1608X5R0J106K ±20%0.80+0.20,–0.10C1608JB0J106MC1608X5R0J106MCapacitance(pF)ToleranceThickness T (mm)Part No.T emperature characteristics: JF T emperature characteristics: Y5V 100,000 +80,–20%0.8±0.10C1608JF1H104Z C1608Y5V1H104Z 220,000 +80,–20%0.8±0.10C1608JF1H224Z C1608Y5V1H224Z 470,000 +80,–20%0.8±0.10C1608JF1H474ZC1608Y5V1H474ZRATED VOLTAGE Edc: 16V RATED VOLTAGE Edc: 6.3V T emperature characteristics: JF T emperature characteristics: Y5V1,000,000 +80,–20%0.8±0.10C1608JF1E105Z C1608Y5V1E105ZCapacitance (pF)ToleranceThickness T(mm)Part No.T emperature characteristics: JF T emperature characteristics: Y5V2,200,000 +80,–20%0.8±0.10C1608JF1C225Z C1608Y5V1C225ZCapacitance (pF)ToleranceThickness T(mm)Part No.T emperature characteristics: JF T emperature characteristics: Y5V4,700,000 +80,–20%0.8±0.10C1608JF0J475Z C1608Y5V0J475Z 10,000,000 +80,–20%0.8+0.15,–0.10C1608JF0J106Z C1608Y5V0J106Z • For more information about the products of other capacitance or data, please contact us.。

101C133T200DE2B中文资料

5,000 hour load lifeRipple Current to > 100 amps @ 55 °C ESRs to 2.5 m Ω> 90% capacitance at –40 ºCThermal-Pak™ extended cathode construction•••••SpeciﬁcationsOperating Temperature:Rated Voltage:Capacitance:Capacitance Tolerance: DCLeakage Current:Cold Impedence:Ripple Current Multipliers:–55 °C to +105 °C 7.5 to 250 Vdc 290 µF to 1.5 F7.5 to 150 Vdc: –10% +75%, 200 & 250 Vdc: 10 +50% ≤1.5√CV µA (4mA max. 5 minutes)–55 °C multiple of 25 °C Z ≤ 3EIA Ripple Life:Life Test:Shelf Life:Vibration:5,000 h at full load @ 85 °C per EIA IS-749 ∆Capacitance ±20% ESR 200% of limit DCL 100% of limit2,000 h at 105 °C and rated voltage ∆Capacitance ±20%ESR 200% of limit DCL 100% of limit500 h @ 105 °C, Capacitance, ESR and DCL, initial requirements.10 to 55 Hz, 0.06” and 10 g max, 1.5 h ea. of 2 axis45 °C 55 °C 65 °C 75 °C 85 °C 95 ºC 105 ºC 1.661.521.371.201.000.750.36Ambient TemperatureThe Ultimate in Cold Performance and ESRThe Type 101C is the wide-temperature, low voltage version of the Type 550C. It is ideal for high-ripple current military and industrial applications that need full performance to –40 ºC and solid perfor-mance to –55 ºC. It also excels as apower-supply output capacitor because of its exceptionally low ESR. The extended cathode foil of the 101C assures heat ﬂow from the capacitor element to the can in all mounting orientations.Highlights10 kHz50 Hz 60 Hz 120 Hz 360 Hz 1 kHz 5 kHz & up1 3/8” & 1 3/4” Diameters7.5 to 150 V 0.910.93 1.00 1.06 1.08 1.09 1.09200 & 250 V 0.820.861.001.141.201.231.232” & 2 1/2” Diameters7.5 to 150 V 0.920.94 1.00 1.05 1.07 1.08 1.08200 & 250 V 0.820.861.001.141.201.231.273” Diameters 7.5 to 150 V 0.950.96 1.00 1.03 1.04 1.05 1.05200 & 250 V0.850.881.001.111.151.181.18FrequencyComplies with the EU Directive 2002/95/E C r e q u i r e m e n t restricting the use of Lead (Pb), Mercury (Hg), Cadmium (Cd), Hexavalent chromium (Cr(VI)), PolyBrominated Biphenyls (PBB) and PolyBrominated Diphenyl Ethers (PBDE).Outline DrawingCase DimensionsUninsulated Case DimensionsFor insulated case, add 0.024”(0.610 mm) to “D”and 0.030”(0.762 mm) to height.NOTE:With the stud-mount feature, a ther-mally-conductive disk can be inserted in the bottom ﬂush with the outer insulating sleeve.This reduces the thermal resistance through the can bottom by 0.3 °C/W. Can Style P.Stud DimensionsTerminal DimensionsCase Diam.Stud ThreadP±0.039”(±1.0 mm) 1.38M8 0.470” (12.0)1.75M8 0.470” (12.0) 2.00M12 0.630” (16.0) 2.50M12 0.630” (16.0)3.00M120.630” (16.0)Diam. (D)Length (L) Terminals (S) Case ±.031 ±.78 ±.062 ±1.57 ±0.015 ±.38 Typical WeightCode Inchesmm Inches mm Inches mm oz g AK 1.37534.93 1.62541.280.5012.70 1.954AA 1.37534.93 2.12553.980.5012.70 2.057AH 1.37534.93 2.62566.680.5012.70 2.777AB 1.37534.93 3.12579.380.5012.70 3.394AJ 1.37534.93 3.62592.080.5012.70 3.8108AC 1.37534.93 4.125104.780.5012.70 4.4125AD 1.37534.93 4.625117.480.5012.70 5.1145AE 1.37534.93 5.125130.180.5012.70 6.8193AF 1.37534.93 5.625142.880.5012.708.1230EA 1.75044.45 2.12553.980.7519.05 2.776EH 1.75044.45 2.62566.680.7519.05 3.8108EB 1.75044.45 3.12579.380.7519.05 5.1145EJ 1.75044.45 3.62592.080.7519.05 6.8193EC 1.75044.45 4.125104.780.7519.058.1230ED 1.75044.45 4.625117.480.7519.059.0255EE 1.75044.45 5.125130.180.7519.059.5269EF 1.75044.45 5.625142.880.7519.0510.5298BA 2.00050.80 2.12553.980.7522.23 5.4153BH 2.00050.80 2.62566.680.7522.23 6.1173BB 2.00050.80 3.12579.380.7522.23 6.8193BJ 2.00050.80 3.62592.080.7522.238.2232BC 2.00050.80 4.125104.780.7522.239.5269BD 2.00050.80 4.625117.480.7522.2310.3292BE 2.00050.80 5.125130.180.7522.2310.7303BF2.00050.80 5.625142.880.7522.2313.0369CH 2.50063.50 2.62566.68 1.2528.589.2261CB 2.50063.50 3.12579.38 1.2528.5810.4295CJ 2.50063.50 3.62592.08 1.2528.5812.7361CC 2.50063.504.125104.78 1.2528.5815.0425CD 2.50063.50 4.625117.48 1.2528.5817.2488CE 2.50063.50 5.125130.18 1.2528.5819.3547CF 2.50063.50 5.625142.88 1.2528.5821.4607DB 3.00076.20 3.12579.38 1.2531.7516.7473DJ 3.00076.20 3.62592.08 1.2531.7520.0567DC 3.00076.20 4.125104.78 1.2531.7522.2629DD 3.00076.20 4.625117.48 1.2531.7525.5723DE 3.00076.20 5.125130.18 1.2531.7530.0850DF 3.00076.20 5.625142.88 1.2531.7531.9904DP 3.00076.20 5.875149.23 1.2531.7532.8931DN 3.00076.207.625193.68 1.2531.7539.51119DG3.00076.208.625219.081.2531.7543.31227For CasePost Diameter H max min Full Thread Torque Terminal Style Diameters Code inmminmm Threadin mm in·lb N·m Low Post 1⅜ to 3A 0.3148.00.094 2.410–320.218 5.525 2.82High Post 1⅜ to 3B 0.3148.00.2817.110–320.3759.525 2.82High Current, Med2½ & 3D0.43411.00.190 4.8¼–280.3127.9505.65Click here to see Hardware & Mounting OptionsPart Numbering System Standard insulation is 0.008-in PVC sleeve with 0.01-in polypropylene end disk.Typical Performance CurvesType Capacitance Tolerance Voltage Case Code Insulation Terminal Can Style101C 183T 250 DG2D S100 = 10 µF 101 = 100 µF 183 = 18,000 µFBlank = Standard CanS = Stud Bottom P = Stud with Thermal PadM = ±20%U = –10%+75%T = –10%+50%7R5 = 7.5 Vdc 063 = 63 Vdc 100 = 100 Vdc0= None1= Polyester 2= PVC A = Low Post B = High PostD = High CurrentRatingsCatalog Part Number ESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)CatalogPart NumberESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)Cap. (µF)Cap.(µF)7.5 Vdc (10 Vdc Surge)74000101C743U010AB2B 14.614.2 1 3/8 x 3 1/828000101C283U7R5AK2B 38.2 6.1 1 3/8 x 1 5/8 89000101C893U010AJ2B 12.516.4 1 3/8 x 3 5/8 47000101C473U7R5AA2B 25.08.7 1 3/8 x 2 1/8 99000101C993U010EH2B 16.614.6 1 3/4 x 2 5/8 66000101C663U7R5AH2B 19.011.4 1 3/8 x 2 5/8 110000101C114U010BH2B 12.118.6 2 x 2 5/8 79000101C793U7R5BA2B 18.314.0 2 x 2 1/8 110000101C114U010AC2B 11.318.1 1 3/8 x 4 1/8 84000101C843U7R5EA2B 22.611.6 1 3/4 x 2 1/8 120000101C124U010AD2B 10.319.7 1 3/8 x 4 5/8 84000101C843U7R5AB2B 15.413.8 1 3/8 x 3 1/8 130000101C134U010EB2B 13.217.4 1 3/4 x 3 1/8 100000101C104U7R5AJ2B 13.215.9 1 3/8 x 3 5/8 140000101C144U010AE2B 9.421.4 1 3/8 x 5 1/8 120000101C124U7R5EH2B 16.514.7 1 3/4 x 2 5/8 150000101C154U010BB2B 8.124.2 2 x 3 1/8 120000101C124U7R5BH2B 12.418.3 2 x 2 5/8 160000101C164U010EJ2B 11.120.0 1 3/4 x 3 5/8 120000101C124U7R5AC2B 12.117.4 1 3/8 x 4 1/8 160000101C164U010AF2B 8.723.1 1 3/8 x 5 5/8 140000101C144U7R5AD2B 10.819.2 1 3/8 x 4 5/8 180000101C184U010CH2B 9.224.5 2 1/2 x 2 5/8 160000101C164U7R5EB2B 13.217.5 1 3/4 x 3 1/8 180000101C184U010BJ2B 7.426.5 2 x 3 5/8 160000101C164U7R5AE2B 9.920.9 1 3/8 x 5 1/8 190000101C194U010EC2B 8.224.4 1 3/4 x 4 1/8 170000101C174U7R5BB2B 8.523.6 2 x 3 1/8 220000101C224U010ED2B 8.724.7 1 3/4 x 4 5/8 180000101C184U7R5AF2B 9.122.6 1 3/8 x 5 5/8 230000101C234U010BC2B 5.731.7 2 x 4 1/8 200000101C204U7R5EJ2B 11.120.1 1 3/4 x 3 5/8 240000101C244U010CB2B 7.029.7 2 1/2 x 3 1/8 210000101C214U7R5CH2B 9.424.2 2 1/2 x 2 5/8 250000101C254U010EE2B 8.026.7 1 3/4 x 5 1/8 220000101C224U7R5EC2B 8.224.4 1 3/4 x 4 1/8 260000101C264U010BD2B 5.533.5 2 x 4 5/8 220000101C224U7R5BJ2B 7.626.2 2 x 3 5/8 280000101C284U010EF2B 7.428.7 1 3/4 x 5 5/8 260000101C264U7R5BC2B 6.031.0 2 x 4 1/8 300000101C304U010CJ2D 5.734.6 2 1/2 x 3 5/8 270000101C274U7R5ED2B 8.724.7 1 3/4 x 4 5/8 300000101C304U010BE2B 5.036.5 2 x 5 1/8 280000101C284U7R5CB2B 7.229.4 2 1/2 x 3 1/8 340000101C344U010BF2B 4.738.9 2 x 5 5/8 300000101C304U7R5BD2B 5.732.9 2 x 4 5/8 360000101C364U010DB2D 7.033.4 3 x 3 1/8 310000101C314U7R5EE2B 7.926.8 1 3/4 x 5 1/8 370000101C374U010CC2D 4.043.0 2 1/2 x 4 1/8 350000101C354U7R5EF2B 7.428.8 1 3/4 x 5 5/8 430000101C434U010CD2D 4.343.5 2 1/2 x 4 5/8 350000101C354U7R5BE2B 5.235.9 2 x 5 1/8 450000101C454U010DJ2D 5.738.8 3 x 3 5/8 360000101C364U7R5CJ2D 5.934.2 2 1/2 x 3 5/8 500000101C504U010CE2D 3.847.5 2 1/2 x 5 1/8 390000101C394U7R5DB2D 7.133.1 3 x 3 1/8 550000101C554U010DC2D 4.545.5 3 x 4 1/8 390000101C394U7R5BF2B 4.938.2 2 x 5 5/8 560000101C564U010CF2D 3.353.0 2 1/2 x 5 5/8 430000101C434U7R5CC2D 4.242.4 2 1/2 x 4 1/8 640000101C644U010DD2D 4.050.4 3 x 4 5/8 490000101C494U7R5DJ2D 5.838.5 3 x 3 5/8 740000101C744U010DE2D 3.754.0 3 x 5 1/8 490000101C494U7R5CD2D 4.442.8 2 1/2 x 4 5/8 840000101C844U010DF2D 3.358.2 3 x 5 5/8 570000101C574U7R5CE2D 4.046.7 2 1/2 x 5 1/8 880000101C884U010DP2D 3.359.2 3 x 5 7/8 610000101C614U7R5DC2D 4.645.2 3 x 4 1/8 1200000101C125U010DN2D 2.870.7 3 x 7 5/8 640000101C644U7R5CF2D 3.452.1 2 1/2 x 5 5/8 1400000101C145U010DG2D 2.576.9 3 x 8 5/8 700000101C704U7R5DD2D 4.050.0 3 x 4 5/8 16 Vdc (25 Vdc Surge)810000101C814U7R5DE2D 3.753.6 3 x 5 1/8 16000101C163U016AK2B 39.2 6.0 1 3/8 x 1 5/8 910000101C914U7R5DF2D 3.457.8 3 x 5 5/8 27000101C273U016AA2B 26.08.5 1 3/8 x 2 1/8 960000101C964U7R5DP2D 3.458.8 3 x 5 7/8 38000101C383U016AH2B 20.011.1 1 3/8 x 2 5/8 1300000101C135U7R5DN2D 2.870.2 3 x 7 5/8 45000101C453U016BA2B 19.113.7 2 x 2 1/8 1500000101C155U7R5DG2D 2.576.4 3 x 8 5/8 46000101C463U016EA2B 24.311.2 1 3/4 x 2 1/810 Vdc (15 Vdc Surge) 49000101C493U016AB2B 15.913.6 1 3/8 x 3 1/8 25000101C253U010AK2B 36.0 6.2 1 3/8 x 1 5/8 59000101C593U016AJ2B 13.515.7 1 3/8 x 3 5/8 41000101C413U010AA2B 23.98.9 1 3/8 x 2 1/8 66000101C663U016EH2B 17.714.2 1 3/4 x 2 5/8 58000101C583U010AH2B 18.111.7 1 3/8 x 2 5/8 71000101C713U016BH2B 13.018.0 2 x 2 5/8 68000101C683U010BA2B 17.814.2 2 x 2 1/8 73000101C733U016AC2B 12.217.4 1 3/8 x 4 1/8 69000101C693U010EA2B 22.811.6 1 3/4 x 2 1/8 82000101C823U016AD2B 11.119.0 1 3/8 x 4 5/8Catalog Part Number ESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)CatalogPart NumberESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)Cap. (µF)Cap. (µF)86000101C863U016EB2B 14.116.9 1 3/4 x 3 1/8 94000101C943U020BJ2B 8.025.7 2 x 3 5/8 93000101C933U016AE2B 10.120.6 1 3/8 x 5 1/8 98000101C983U020EC2B 8.623.8 1 3/4 x 4 1/8 100000101C104U016BB2B 8.623.4 2 x 3 1/8 110000101C114U020ED2B 9.224.0 1 3/4 x 4 5/8 110000101C114U016EJ2B 11.819.4 1 3/4 x 3 5/8 120000101C124U020CB2B 7.528.9 2 1/2 x 3 1/8 110000101C114U016AF2B 9.322.3 1 3/8 x 5 5/8 120000101C124U020BC2B 6.030.9 2 x 4 1/8 120000101C124U016CH2B 9.823.7 2 1/2 x 2 5/8 130000101C134U020EE2B 8.426.0 1 3/4 x 5 1/8 120000101C124U016BJ2B 8.025.7 2 x 3 5/8 130000101C134U020BD2B 5.932.5 2 x 4 5/8 130000101C134U016EC2B 8.623.8 1 3/4 x 4 1/8 140000101C144U020EF2B 7.828.0 1 3/4 x 5 5/8 150000101C154U016ED2B 9.224.0 1 3/4 x 4 5/8 150000101C154U020CJ2D 6.133.6 2 1/2 x 3 5/8 160000101C164U016CB2B 7.528.9 2 1/2 x 3 1/8 150000101C154U020BE2B 5.335.4 2 x 5 1/8 160000101C164U016BC2B 6.030.9 2 x 4 1/8 180000101C184U020DB2D 7.332.7 3 x 3 1/8 170000101C174U016EE2B 8.426.0 1 3/4 x 5 1/8 180000101C184U020BF2B 4.938.0 2 x 5 5/8 170000101C174U016BD2B 5.932.5 2 x 4 5/8 190000101C194U020CC2D 4.341.9 2 1/2 x 4 1/8 190000101C194U016EF2B 7.828.0 1 3/4 x 5 5/8 220000101C224U020CD2D 4.542.3 2 1/2 x 4 5/8 200000101C204U016CJ2D 6.133.6 2 1/2 x 3 5/8 230000101C234U020DJ2D 5.938.1 3 x 3 5/8 200000101C204U016BE2B 5.335.4 2 x 5 1/8 250000101C254U020CE2D 4.046.2 2 1/2 x 5 1/8 230000101C234U016BF2B 4.938.0 2 x 5 5/8 280000101C284U020DC2D 4.744.6 3 x 4 1/8 240000101C244U016DB2D 7.332.7 3 x 3 1/8 280000101C284U020CF2D 3.451.6 2 1/2 x 5 5/8 250000101C254U016CC2D 4.341.9 2 1/2 x 4 1/8 330000101C334U020DD2D 4.149.5 3 x 4 5/8 290000101C294U016CD2D 4.542.3 2 1/2 x 4 5/8 380000101C384U020DE2D 3.853.0 3 x 5 1/8 300000101C304U016DJ2D 5.938.1 3 x 3 5/8 420000101C424U020DF2D 3.557.2 3 x 5 5/8 330000101C334U016CE2D 4.046.2 2 1/2 x 5 1/8 450000101C454U020DP2D 3.458.2 3 x 5 7/8 360000101C364U016DC2D 4.744.6 3 x 4 1/8 610000101C614U020DN2D 2.969.4 3 x 7 5/8 370000101C374U016CF2D 3.451.6 2 1/2 x 5 5/8 710000101C714U020DG2D 2.675.5 3 x 8 5/8 430000101C434U016DD2D 4.149.5 3 x 4 5/8 25 Vdc (40 Vdc Surge)490000101C494U016DE2D 3.853.0 3 x 5 1/8 9900101C992U025AK2B 42.6 5.7 1 3/8 x 1 5/8 560000101C564U016DF2D 3.557.2 3 x 5 5/8 16000101C163U025AA2B 28.28.2 1 3/8 x 2 1/8 590000101C594U016DP2D 3.458.2 3 x 5 7/8 23000101C233U025AH2B 20.910.8 1 3/8 x 2 5/8 800000101C804U016DN2D 2.969.6 3 x 7 5/8 27000101C273U025EA2B 25.111.0 1 3/4 x 2 1/8 920000101C924U016DG2D 2.675.8 3 x 8 5/8 27000101C273U025BA2B 19.913.5 2 x 2 1/820 Vdc (30 Vdc Surge)30000101C303U025AB2B 16.613.3 1 3/8 x 3 1/8 13000101C133U020AK2B 39.2 6.0 1 3/8 x 1 5/8 35000101C353U025AJ2B 14.215.4 1 3/8 x 3 5/8 21000101C213U020AA2B 26.08.5 1 3/8 x 2 1/8 39000101C393U025EH2B 18.313.9 1 3/4 x 2 5/8 29000101C293U020AH2B 20.011.1 1 3/8 x 2 5/8 42000101C423U025BH2B 13.517.6 2 x 2 5/8 34000101C343U020BA2B 19.113.7 2 x 2 1/8 43000101C433U025AC2B 12.717.0 1 3/8 x 4 1/8 35000101C353U020EA2B 24.311.2 1 3/4 x 2 1/8 49000101C493U025AD2B 11.618.6 1 3/8 x 4 5/8 38000101C383U020AB2B 15.913.6 1 3/8 x 3 1/8 52000101C523U025EB2B 14.516.6 1 3/4 x 3 1/8 45000101C453U020AJ2B 13.515.7 1 3/8 x 3 5/8 56000101C563U025AE2B 10.620.2 1 3/8 x 5 1/8 50000101C503U020EH2B 17.714.2 1 3/4 x 2 5/8 60000101C603U025BB2B 9.022.9 2 x 3 1/8 54000101C543U020BH2B 13.018.0 2 x 2 5/8 63000101C633U025AF2B 9.721.9 1 3/8 x 5 5/8 55000101C553U020AC2B 12.217.4 1 3/8 x 4 1/8 64000101C643U025EJ2B 12.219.1 1 3/4 x 3 5/8 62000101C623U020AD2B 11.119.0 1 3/8 x 4 5/8 70000101C703U025CH2B 10.123.3 2 1/2 x 2 5/8 66000101C663U020EB2B 14.116.9 1 3/4 x 3 1/8 73000101C733U025BJ2B 8.325.2 2 x 3 5/8 71000101C713U020AE2B 10.120.6 1 3/8 x 5 1/8 77000101C773U025EC2B 9.922.2 1 3/4 x 4 1/8 77000101C773U020BB2B 8.623.4 2 x 3 1/8 88000101C883U025ED2B 9.523.6 1 3/4 x 4 5/8 80000101C803U020AF2B 9.322.3 1 3/8 x 5 5/8 90000101C903U025BC2B 6.430.0 2 x 4 1/8 81000101C813U020EJ2B 11.819.4 1 3/4 x 3 5/8 95000101C953U025CB2B 7.728.4 2 1/2 x 3 1/8 89000101C893U020CH2B 9.823.7 2 1/2 x 2 5/8 100000101C104U025EE2B 8.625.7 1 3/4 x 5 1/8(mΩ) (A) (inches) (mΩ) (A) (inches) 100000101C104U025BD2B 6.131.9 2 x 4 5/8 120000101C124U030CC2D 4.740.0 2 1/2 x 4 1/8 110000101C114U025EF2B 8.027.6 1 3/4 x 5 5/8 150000101C154U030DJ2D 5.738.7 3 x 3 5/8 120000101C124U025CJ2D 6.333.1 2 1/2 x 3 5/8 150000101C154U030CD2D 4.343.4 2 1/2 x 4 5/8 120000101C124U025BE2B 5.534.8 2 x 5 1/8 170000101C174U030CE2D 3.847.4 2 1/2 x 5 1/8 140000101C144U025DB2D 7.432.4 3 x 3 1/8 180000101C184U030DC2D 4.843.9 3 x 4 1/8 140000101C144U025BF2B 5.137.4 2 x 5 5/8 190000101C194U030CF2D 3.551.2 2 1/2 x 5 5/8 150000101C154U025CC2D 4.540.6 2 1/2 x 4 1/8 220000101C224U030DD2D 4.348.5 3 x 4 5/8 170000101C174U025CD2D 4.741.6 2 1/2 x 4 5/8 250000101C254U030DE2D 3.852.8 3 x 5 1/8 180000101C184U025DJ2D 6.037.7 3 x 3 5/8 280000101C284U030DF2D 3.556.9 3 x 5 5/8 200000101C204U025CE2D 4.245.5 2 1/2 x 5 1/8 300000101C304U030DP2D 3.458.8 3 x 5 7/8 220000101C224U025DC2D 4.844.1 3 x 4 1/8 410000101C414U030DN2D 2.969.5 3 x 7 5/8 220000101C224U025CF2D 3.650.3 2 1/2 x 5 5/8 470000101C474U030DG2D 2.675.8 3 x 8 5/8 260000101C264U025DD2D 4.547.3 3 x 4 5/8 40 Vdc (55 Vdc Surge)290000101C294U025DE2D 4.051.6 3 x 5 1/8 5400101C542U040AK2B 47.6 5.4 1 3/8 x 1 5/8 330000101C334U025DF2D 3.556.7 3 x 5 5/8 9000101C902U040AA2B 32.37.6 1 3/8 x 2 1/8 350000101C354U025DP2D 3.557.7 3 x 5 7/8 13000101C133U040AH2B 23.110.3 1 3/8 x 2 5/8 480000101C484U025DN2D 2.969.0 3 x 7 5/8 16000101C163U040EA2B 26.610.7 1 3/4 x 2 1/8 550000101C554U025DG2D 2.675.2 3 x 8 5/8 16000101C163U040BA2B 21.213.0 2 x 2 1/830 Vdc (45 Vdc Surge) 17000101C173U040AB2B 17.313.1 1 3/8 x 3 1/8 5400101C542U030AK2B 43.9 5.6 1 3/8 x 1 5/8 21000101C213U040AJ2B 15.214.8 1 3/8 x 3 5/8 13000101C133U030AA2B 29.88.0 1 3/8 x 2 1/8 23000101C233U040EH2B 19.313.5 1 3/4 x 2 5/8 19000101C193U030AH2B 21.410.7 1 3/8 x 2 5/8 25000101C253U040BH2B 14.317.1 2 x 2 5/8 23000101C233U030EA2B 23.111.5 1 3/4 x 2 1/8 25000101C253U040AC2B 14.016.2 1 3/8 x 4 1/8 23000101C233U030BA2B 18.813.8 2 x 2 1/8 29000101C293U040AD2B 12.417.9 1 3/8 x 4 5/8 24000101C243U030AB2B 16.013.6 1 3/8 x 3 1/8 30000101C303U040EB2B 15.416.2 1 3/4 x 3 1/8 30000101C303U030AJ2B 14.115.4 1 3/8 x 3 5/8 33000101C333U040AE2B 11.319.6 1 3/8 x 5 1/8 33000101C333U030EH2B 16.914.5 1 3/4 x 2 5/8 34000101C343U040BB2B 9.822.0 2 x 3 1/8 36000101C363U030AC2B 13.016.8 1 3/8 x 4 1/8 37000101C373U040EJ2B 12.918.6 1 3/4 x 3 5/8 36000101C363U030BH2B 12.818.1 2 x 2 5/8 37000101C373U040AF2B 10.421.1 1 3/8 x 5 5/8 41000101C413U030AD2B 11.618.6 1 3/8 x 4 5/8 41000101C413U040CH2B 10.722.7 2 1/2 x 2 5/8 44000101C443U030EB2B 13.417.3 1 3/4 x 3 1/8 43000101C433U040BJ2B 8.824.4 2 x 3 5/8 47000101C473U030AE2B 10.620.2 1 3/8 x 5 1/8 45000101C453U040EC2B 10.521.6 1 3/4 x 4 1/8 49000101C493U030BB2B 8.723.3 2 x 3 1/8 52000101C523U040ED2B 9.523.6 1 3/4 x 4 5/8 53000101C533U030AF2B 9.821.8 1 3/8 x 5 5/8 52000101C523U040BC2B 7.128.5 2 x 4 1/8 54000101C543U030EJ2B 11.319.9 1 3/4 x 3 5/8 56000101C563U040CB2B 8.127.6 2 1/2 x 3 1/8 59000101C593U030CH2B 9.324.4 2 1/2 x 2 5/8 59000101C593U040EE2B 8.925.4 1 3/4 x 5 1/8 62000101C623U030BJ2B 7.825.8 2 x 3 5/8 61000101C613U040BD2B 6.531.0 2 x 4 5/8 64000101C643U030EC2B 9.223.0 1 3/4 x 4 1/8 66000101C663U040EF2B 8.426.9 1 3/4 x 5 5/8 75000101C753U030ED2B 8.425.1 1 3/4 x 4 5/8 70000101C703U040BE2B 5.833.8 2 x 5 1/8 75000101C753U030BC2B 6.330.1 2 x 4 1/8 71000101C713U040CJ2D 6.632.2 2 1/2 x 3 5/8 81000101C813U030CB2B 7.129.7 2 1/2 x 3 1/8 79000101C793U040BF2B 5.336.5 2 x 5 5/8 85000101C853U030EE2B 7.926.9 1 3/4 x 5 1/8 83000101C833U040DB2D 8.630.1 3 x 3 1/8 88000101C883U030BD2B 5.832.7 2 x 4 5/8 86000101C863U040CC2D 5.437.3 2 1/2 x 4 1/8 95000101C953U030EF2B 7.528.5 1 3/4 x 5 5/8 100000101C104U040CD2D 4.940.6 2 1/2 x 4 5/8 100000101C104U030CJ2D 5.734.6 2 1/2 x 3 5/8 110000101C114U040DJ2D 7.035.1 3 x 3 5/8 100000101C104U030BE2B 5.235.6 2 x 5 1/8 120000101C124U040CE2D 4.444.4 2 1/2 x 5 1/8 110000101C114U030BF2B 4.838.4 2 x 5 5/8 130000101C134U040DC2D 5.341.9 3 x 4 1/8 120000101C124U030DB2D 7.033.3 3 x 3 1/8 130000101C134U040CF2D 4.048.0 2 1/2 x 5 5/8(mΩ) (A) (inches) (mΩ) (A) (inches) 150000101C154U040DD2D 5.244.0 3 x 4 5/8 63 Vdc (85 Vdc Surge)170000101C174U040DE2D 4.648.1 3 x 5 1/8 2800101C282U063AK2B 57.9 4.9 1 3/8 x 1 5/8 190000101C194U040DF2D 4.251.9 3 x 5 5/8 5000101C502U063AA2B 35.57.3 1 3/8 x 2 1/8 210000101C214U040DP2D 4.053.8 3 x 5 7/8 7200101C722U063AH2B 25.89.8 1 3/8 x 2 5/8 280000101C284U040DN2D 3.463.9 3 x 7 5/8 8800101C882U063BA2B 22.812.6 2 x 2 1/8 330000101C334U040DG2D 3.069.9 3 x 8 5/8 8900101C892U063EA2B 28.010.4 1 3/4 x 2 1/850 Vdc (75 Vdc Surge) 9400101C942U063AB2B 20.412.0 1 3/8 x 3 1/8 3800101C382U050AK2B 48.4 5.4 1 3/8 x 1 5/8 12000101C123U063AJ2B 17.114.0 1 3/8 x 3 5/8 7000101C702U050AA2B 30.87.8 1 3/8 x 2 1/8 13000101C133U063EH2B 20.413.2 1 3/4 x 2 5/8 10000101C103U050AH2B 22.010.5 1 3/8 x 2 5/8 14000101C143U063BH2B 15.416.5 2 x 2 5/8 12000101C123U050EA2B 26.510.7 1 3/4 x 2 1/8 14000101C143U063AC2B 14.815.8 1 3/8 x 4 1/8 12000101C123U050BA2B 20.813.2 2 x 2 1/8 16000101C163U063AD2B 13.217.4 1 3/8 x 4 5/8 13000101C133U050AB2B 17.513.0 1 3/8 x 3 1/8 17000101C173U063EB2B 16.115.8 1 3/4 x 3 1/8 16000101C163U050AJ2B 14.615.2 1 3/8 x 3 5/8 18000101C183U063AE2B 12.019.0 1 3/8 x 5 1/8 18000101C183U050EH2B 19.313.6 1 3/4 x 2 5/8 19000101C193U063BB2B 10.221.5 2 x 3 1/8 19000101C193U050BH2B 14.117.2 2 x 2 5/8 20000101C203U063AF2B 11.020.5 1 3/8 x 5 5/8 19000101C193U050AC2B 13.416.6 1 3/8 x 4 1/8 21000101C213U063EJ2B 13.518.2 1 3/4 x 3 5/8 22000101C223U050AD2B 11.918.3 1 3/8 x 4 5/8 23000101C233U063CH2B 11.322.1 2 1/2 x 2 5/8 24000101C243U050EB2B 15.316.2 1 3/4 x 3 1/8 24000101C243U063BJ2B 9.623.4 2 x 3 5/8 25000101C253U050AE2B 10.820.0 1 3/8 x 5 1/8 25000101C253U063EC2B 11.021.1 1 3/4 x 4 1/8 27000101C273U050BB2B 9.622.2 2 x 3 1/8 29000101C293U063ED2B 10.023.0 1 3/4 x 4 5/8 29000101C293U050EJ2B 12.818.6 1 3/4 x 3 5/8 29000101C293U063BC2B 8.226.4 2 x 4 1/8 29000101C293U050AF2B 10.021.5 1 3/8 x 5 5/8 31000101C313U063CB2B 8.626.9 2 1/2 x 3 1/8 32000101C323U050CH2B 9.624.0 2 1/2 x 2 5/8 33000101C333U063EE2B 9.324.8 1 3/4 x 5 1/8 34000101C343U050BJ2B 8.624.6 2 x 3 5/8 34000101C343U063BD2B 7.229.3 2 x 4 5/8 35000101C353U050EC2B 10.521.6 1 3/4 x 4 1/8 37000101C373U063EF2B 8.826.3 1 3/4 x 5 5/8 40000101C403U050ED2B 9.523.6 1 3/4 x 4 5/8 39000101C393U063BE2B 6.532.0 2 x 5 1/8 41000101C413U050BC2B 7.228.2 2 x 4 1/8 40000101C403U063CJ2D 7.031.4 2 1/2 x 3 5/8 44000101C443U050CB2B 8.227.6 2 1/2 x 3 1/8 44000101C443U063BF2B 5.934.6 2 x 5 5/8 46000101C463U050EE2B 8.825.4 1 3/4 x 5 1/8 47000101C473U063DB2B 9.329.0 3 x 3 1/8 48000101C483U050BD2B 6.331.2 2 x 4 5/8 48000101C483U063CC2D 5.636.4 2 1/2 x 4 1/8 52000101C523U050EF2B 8.427.0 1 3/4 x 5 5/8 56000101C563U063CD2D 5.239.5 2 1/2 x 4 5/8 55000101C553U050CJ2D 6.632.2 2 1/2 x 3 5/8 59000101C593U063DJ2D 7.533.8 3 x 3 5/8 55000101C553U050BE2B 5.734.1 2 x 5 1/8 65000101C653U063CE2D 4.643.3 2 1/2 x 5 1/8 62000101C623U050BF2B 5.236.8 2 x 5 5/8 72000101C723U063DC2D 6.039.5 3 x 4 1/8 65000101C653U050DB2B 8.929.5 3 x 3 1/8 73000101C733U063CF2D 4.246.8 2 1/2 x 5 5/8 67000101C673U050CC2D 5.437.3 2 1/2 x 4 1/8 84000101C843U063DD2D 5.642.5 3 x 4 5/8 79000101C793U050CD2D 4.940.5 2 1/2 x 4 5/8 97000101C973U063DE2D 5.046.5 3 x 5 1/8 83000101C833U050DJ2D 7.334.4 3 x 3 5/8 110000101C114U063DF2D 4.550.2 3 x 5 5/8 90000101C903U050CE2D 4.444.3 2 1/2 x 5 1/8 120000101C124U063DP2D 4.352.0 3 x 5 7/8 100000101C104U050DC2D 5.541.1 3 x 4 1/8 160000101C164U063DN2D 3.662.2 3 x 7 5/8 100000101C104U050CF2D 4.047.9 2 1/2 x 5 5/8 180000101C184U063DG2D 3.268.2 3 x 8 5/8 120000101C124U050DD2D 5.443.2 3 x 4 5/8 75 Vdc (100 Vdc Surge)130000101C134U050DE2D 4.847.2 3 x 5 1/8 2100101C212U075AK2B 97.3 3.8 1 3/8 x 1 5/8 150000101C154U050DF2D 4.451.0 3 x 5 5/8 3600101C362U075AA2B 67.2 5.3 1 3/8 x 2 1/8 160000101C164U050DP2D 4.252.9 3 x 5 7/8 5200101C522U075AH2B 50.07.0 1 3/8 x 2 5/8 220000101C224U050DN2D 3.563.0 3 x 7 5/8 6400101C642U075BA2B 40.79.4 2 x 2 1/8 260000101C264U050DG2D 3.169.0 3 x 8 5/8 6500101C652U075EA2B 47.58.0 1 3/4 x 2 1/8Catalog Part Number ESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)CatalogPart NumberESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)Cap. (µF)Cap.(µF)75 Vdc (100 Vdc Surge) 8900101C892U100BB2B 21.015.0 2 x 3 1/86800101C682U075AB2B 39.38.7 1 3/8 x 3 1/8 9600101C962U100AF2B 23.414.1 1 3/8 x 5 5/8 8400101C842U075AJ2B 32.510.1 1 3/8 x 3 5/8 9800101C982U100EJ2B 25.813.2 1 3/4 x 3 5/8 9400101C942U075EH2B 34.210.2 1 3/4 x 2 5/8 11000101C113U100CH2B 20.716.3 2 1/2 x 2 5/8 10000101C103U075AC2B 27.911.5 1 3/8 x 4 1/8 11000101C113U100BJ2B 19.516.4 2 x 3 5/8 10000101C103U075BH2B 27.412.4 2 x 2 5/8 12000101C123U100EC2B 20.715.4 1 3/4 x 4 1/8 12000101C123U075EB2B 27.012.2 1 3/4 x 3 1/8 14000101C143U100ED2B 18.616.9 1 3/4 x 4 5/8 12000101C123U075AD2B 24.512.8 1 3/8 x 4 5/8 14000101C143U100BC2B 14.819.7 2 x 4 1/8 13000101C133U075AE2B 22.014.0 1 3/8 x 5 1/8 15000101C153U100EE2B 17.018.3 1 3/4 x 5 1/8 14000101C143U075BB2B 18.016.2 2 x 3 1/8 15000101C153U100CB2B 16.519.4 2 1/2 x 3 1/8 15000101C153U075EJ2B 22.414.1 1 3/4 x 3 5/8 16000101C163U100BD2B 14.320.8 2 x 4 5/8 15000101C153U075AF2B 20.015.2 1 3/8 x 5 5/8 17000101C173U100EF2B 15.919.6 1 3/4 x 5 5/8 17000101C173U075CH2B 18.917.1 2 1/2 x 2 5/8 18000101C183U100BE2B 12.722.9 2 x 5 1/8 17000101C173U075BJ2B 16.817.7 2 x 3 5/8 19000101C193U100CJ2B 13.322.7 2 1/2 x 3 5/8 18000101C183U075EC2B 18.016.5 1 3/4 x 4 1/8 21000101C213U100BF2B 11.424.9 2 x 5 5/8 21000101C213U075ED2B 16.218.1 1 3/4 x 4 5/8 22000101C223U100DB2B 13.823.8 3 x 3 1/8 21000101C213U075BC2B 12.721.2 2 x 4 1/8 22000101C223U100CC2B 10.027.4 2 1/2 x 4 1/8 23000101C233U075CB2B 14.320.8 2 1/2 x 3 1/8 26000101C263U100CD2B 9.728.9 2 1/2 x 4 5/8 24000101C243U075EE2B 14.819.6 1 3/4 x 5 1/8 28000101C283U100DJ2B 11.227.7 3 x 3 5/8 25000101C253U075BD2B 12.322.4 2 x 4 5/8 30000101C303U100CE2D 8.631.7 2 1/2 x 5 1/8 27000101C273U075EF2B 13.920.9 1 3/4 x 5 5/8 34000101C343U100DC2D 8.533.2 3 x 4 1/8 28000101C283U075BE2B 11.024.6 2 x 5 1/8 34000101C343U100CF2D 7.734.5 2 1/2 x 5 5/8 29000101C293U075CJ2B 11.524.4 2 1/2 x 3 5/8 39000101C393U100DD2D 7.935.7 3 x 4 5/8 32000101C323U075BF2B 9.926.7 2 x 5 5/8 45000101C453U100DE2D 6.540.5 3 x 5 1/8 34000101C343U075DB2B 13.324.2 3 x 3 1/8 51000101C513U100DF2D 6.043.5 3 x 5 5/8 35000101C353U075CC2B 8.729.4 2 1/2 x 4 1/8 54000101C543U100DP2D 6.044.1 3 x 5 7/8 41000101C413U075CD2D 8.430.9 2 1/2 x 4 5/8 74000101C743U100DN2D 4.854.0 3 x 7 5/8 43000101C433U075DJ2B 10.828.2 3 x 3 5/8 85000101C853U100DG2D 4.259.2 3 x 8 5/8 47000101C473U075CE2D 7.534.0 2 1/2 x 5 1/8 150 Vdc (200 Vdc Surge)52000101C523U075DC2D 7.635.0 3 x 4 1/8 490101C491U150AK2B 433.0 2.1 1 3/8 x 1 5/8 53000101C533U075CF2D 6.736.9 2 1/2 x 5 5/8 880101C881U150AA2B 241.0 3.1 1 3/8 x 2 1/8 61000101C613U075DD2D 7.935.7 3 x 4 5/8 1200101C122U150EA2B 199.0 3.9 1 3/4 x 2 1/8 70000101C703U075DE2D 6.142.0 3 x 5 1/8 1300101C132U150AH2B 163.0 4.0 1 3/8 x 2 5/8 79000101C793U075DF2D 6.043.5 3 x 5 5/8 1500101C152U150BA2B 159.0 4.8 2 x 2 1/8 83000101C833U075DP2D 5.745.1 3 x 5 7/8 1700101C172U150AB2B 125.0 4.9 1 3/8 x 3 1/8 110000101C114U075DN2D 4.754.7 3 x 7 5/8 1800101C182U150EH2B 133.0 5.2 1 3/4 x 2 5/8 130000101C134U075DG2D 4.160.3 3 x 8 5/8 1900101C192U150AJ2B 112.0 5.5 1 3/8 x 3 5/8 100 Vdc (150 Vdc Surge) 2300101C232U150BH2B 104.0 6.3 2 x 2 5/8 1300101C132U100AK2B 116.0 3.5 1 3/8 x 1 5/8 2500101C252U150EB2B 95.5 6.5 1 3/4 x 3 1/8 2300101C232U100AA2B 79.9 4.9 1 3/8 x 2 1/8 2500101C252U150AC2B 84.9 6.6 1 3/8 x 4 1/8 3400101C342U100AH2B 59.4 6.4 1 3/8 x 2 5/8 2700101C272U150AD2B 80.17.1 1 3/8 x 4 5/8 4100101C412U100BA2B 47.68.7 2 x 2 1/8 3100101C312U150AE2B 74.07.6 1 3/8 x 5 1/8 4200101C422U100EA2B 55.07.4 1 3/4 x 2 1/8 3200101C322U150EJ2B 74.67.7 1 3/4 x 3 5/8 4400101C442U100AB2B 46.68.0 1 3/8 x 3 1/8 3400101C342U150BB2B 54.69.3 2 x 3 1/8 5400101C542U100AJ2B 38.59.3 1 3/8 x 3 5/8 3600101C362U150AF2B 66.38.4 1 3/8 x 5 5/8 6100101C612U100EH2B 39.69.5 1 3/4 x 2 5/8 3800101C382U150CH2B 62.89.4 2 1/2 x 2 5/8 6500101C652U100AC2B 32.910.6 1 3/8 x 4 1/8 4000101C402U150BJ2B 59.79.4 2 x 3 5/8 6500101C652U100BH2B 32.011.4 2 x 2 5/8 4400101C442U150EC2B 54.39.5 1 3/4 x 4 1/8 7500101C752U100AD2B 28.911.8 1 3/8 x 4 5/8 4500101C452U150ED2B 53.110.0 1 3/4 x 4 5/8 7900101C792U100EB2B 31.111.4 1 3/4 x 3 1/8 5200101C522U150EE2B 45.911.1 1 3/4 x 5 1/8 8500101C852U100AE2B 25.812.9 1 3/8 x 5 1/8Catalog Part Number ESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)CatalogPart NumberESR Max.@ 25 °C120 Hz(mΩ)Ripple Max.@ 85°C120 Hz(A)Nominal SizeD x L(inches)Cap. (µF)Cap. (µF)5200101C522U150CB2B 45.911.6 2 1/2 x 3 1/8 8300101C832T200CE2B 24.019.0 2 1/2 x 5 1/8 5200101C522U150BC2B 45.011.3 2 x 4 1/8 9300101C932T200DC2B 21.420.9 3 x 4 1/8 5700101C572U150BD2B 41.912.2 2 x 4 5/8 10000101C103T200CF2B 21.220.8 2 1/2 x 5 5/8 5800101C582U150EF2B 41.212.2 1 3/4 x 5 5/8 11000101C113T200DD2B 20.522.1 3 x 4 5/8 6600101C662U150BE2B 36.213.6 2 x 5 1/8 13000101C133T200DB2B 17.820.9 3 x 3 1/8 6600101C662U150CJ2B 36.213.8 2 1/2 x 3 5/8 13000101C133T200DE2B 17.824.5 3 x 5 1/8 7800101C782U150DB2B 35.714.8 3 x 3 1/8 14000101C143T200DF2B 16.925.9 3 x 5 5/8 7900101C792U150BF2B 30.215.3 2 x 5 5/8 15000101C153T200DP2B 15.927.1 3 x 5 7/8 8500101C852U150CC2B 28.116.3 2 1/2 x 4 1/8 20000101C203T200DN2D 12.533.9 3 x 7 5/8 9400101C942U150CD2B 25.417.8 2 1/2 x 4 5/8 23000101C233T200DG2D 10.437.8 3 x 8 5/8 9900101C992U150DJ2B 28.117.5 3 x 3 5/8 250 Vdc (350 Vdc Surge)11000101C113U150CE2B 21.719.9 2 1/2 x 5 1/8 290101C291T250AK2B 549.0 1.8 1 3/8 x 1 5/8 12000101C123U150DC2B 23.220.1 3 x 4 1/8 530101C531T250AA2B 300.0 2.7 1 3/8 x 2 1/8 13000101C133U150CF2B 18.422.3 2 1/2 x 5 5/8 700101C701T250EA2B 227.0 3.7 1 3/4 x 2 1/8 14000101C143U150DD2B 19.922.5 3 x 4 5/8 760101C761T250AH2B 209.0 3.5 1 3/8 x 2 5/8 16000101C163U150DE2B 17.424.8 3 x 5 1/8 890101C891T250BA2B 164.0 4.7 2 x 2 1/8 18000101C183U150DF2B 15.527.1 3 x 5 5/8 990101C991T250AB2B 161.0 4.3 1 3/8 x 3 1/8 19000101C193U150DP2B 14.728.2 3 x 5 7/8 1100101C112T250EH2B 145.0 5.0 1 3/4 x 2 5/8 26000101C263U150DN2D 11.335.7 3 x 7 5/8 1200101C122T250AJ2B 133.0 5.0 1 3/8 x 3 5/8 30000101C303U150DG2D 9.340.0 3 x 8 5/8 1400101C142T250BH2B 104.0 6.3 2 x 2 5/8 200 Vdc (275 Vdc Surge) 1500101C152T250AC2B 106.0 5.9 1 3/8 x 4 1/8 380101C381T200AK2B 454.0 2.0 1 3/8 x 1 5/8 1500101C152T250EB2B 106.0 6.2 1 3/4 x 3 1/8 680101C681T200AA2B 254.0 3.0 1 3/8 x 2 1/8 1700101C172T250AD2B 101.0 6.3 1 3/8 x 4 5/8 890101C891T200EA2B 224.0 3.7 1 3/4 x 2 1/8 1900101C192T250AE2B 90.7 6.9 1 3/8 x 5 1/8 980101C981T200AH2B 176.0 3.9 1 3/8 x 2 5/8 1900101C192T250EJ2B 83.87.3 1 3/4 x 3 5/8 1100101C112T200BA2B 181.0 4.5 2 x 2 1/8 1900101C192T250BB2B 69.88.2 2 x 3 1/8 1300101C132T200AB2B 133.0 4.8 1 3/8 x 3 1/8 2200101C222T250AF2B 84.47.4 1 3/8 x 5 5/8 1400101C142T200EH2B 142.0 5.0 1 3/4 x 2 5/8 2300101C232T250CH2B 75.08.6 2 1/2 x 2 5/8 1600101C162T200AJ2B 108.0 5.6 1 3/8 x 3 5/8 2300101C232T250EC2B 69.28.4 1 3/4 x 4 1/8 1800101C182T200BH2B 111.0 6.1 2 x 2 5/8 2400101C242T250BJ2B 58.09.5 2 x 3 5/8 1900101C192T200EB2B 105.0 6.2 1 3/4 x 3 1/8 2700101C272T250ED2B 58.99.5 1 3/4 x 4 5/8 1900101C192T200AC2B 88.9 6.4 1 3/8 x 4 1/8 2900101C292T250BC2B 50.310.7 2 x 4 1/8 2200101C222T200AD2B 90.4 6.7 1 3/8 x 4 5/8 3100101C312T250CB2B 55.610.6 2 1/2 x 3 1/8 2400101C242T200EJ2B 82.97.3 1 3/4 x 3 5/8 3100101C312T250EE2B 51.310.5 1 3/4 x 5 1/8 2400101C242T200BB2B 82.97.5 2 x 3 1/8 3400101C342T250BD2B 45.611.7 2 x 4 5/8 2500101C252T200AE2B 79.67.4 1 3/8 x 5 1/8 3500101C352T250EF2B 45.511.6 1 3/4 x 5 5/8 2800101C282T200AF2B 71.08.1 1 3/8 x 5 5/8 3900101C392T250BE2B 42.012.6 2 x 5 1/8 3100101C312T200BJ2B 64.29.0 2 x 3 5/8 4000101C402T250CJ2B 43.112.6 2 1/2 x 3 5/8 3400101C342T200EC2B 58.59.1 1 3/4 x 4 1/8 4500101C452T250BF2B 38.313.6 2 x 5 5/8 3500101C352T200ED2B 56.89.7 1 3/4 x 4 5/8 4700101C472T250DB2B 42.313.6 3 x 3 1/8 4000101C402T200EE2B 49.710.7 1 3/4 x 5 1/8 5100101C512T250CC2B 30.615.6 2 1/2 x 4 1/8 4000101C402T200CB2B 49.711.2 2 1/2 x 3 1/8 5700101C572T250CD2B 28.916.7 2 1/2 x 4 5/8 4000101C402T200BC2B 43.111.5 2 x 4 1/8 5900101C592T250DJ2B 33.716.0 3 x 3 5/8 4400101C442T200BD2B 45.211.7 2 x 4 5/8 6500101C652T250CE2B 26.618.0 2 1/2 x 5 1/8 4500101C452T200EF2B 44.211.7 1 3/4 x 5 5/8 7200101C722T250DC2B 27.618.4 3 x 4 1/8 5000101C502T200BE2B 39.812.9 2 x 5 1/8 7700101C772T250CF2B 24.119.5 2 1/2 x 5 5/8 5100101C512T200CJ2B 39.013.3 2 1/2 x 3 5/8 8500101C852T250DD2B 23.420.7 3 x 4 5/8 6100101C612T200BF2B 32.614.7 2 x 5 5/8 9700101C972T250DE2B 20.522.8 3 x 5 1/8 6500101C652T200CC2B 26.316.9 2 1/2 x 4 1/8 11000101C113T250DF2B 18.125.0 3 x 5 5/8 7200101C722T200CD2B 27.617.1 2 1/2 x 4 5/8 12000101C123T250DP2B 16.626.5 3 x 5 7/8 7600101C762T200DJ2B 29.717.0 3 x 3 5/8 16000101C163T250DN2D 13.432.8 3 x 7 5/818000101C183T250DG2D 11.136.7 3 x 8 5/8。

ADGS1612 数据手册说明书

Rev. 0Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective owners.One Technology Way, P .O. Box 9106, Norwood, M A 02062-9106, U.S.A.Tel: 781.329.4700 ©2012-2017 Analog Devices, Inc. All rights reserved. Technical Support /cnSPI 接口、1 Ω R ON 、±5 V/12 V/5 V/3.3 V 、支持多路复用器配置、四通道SPST 开关数据手册ADGS1612特性SPI 接口具备错误检测功能包括CRC 、无效读取/写入地址和SCLK 计数错误检测支持突发模式和菊花链模式兼容业界标准SPI 模式0和SPI 模式3接口保证先开后合式开关动作，允许开关外部接线以实现多路复用器配置导通电阻(25°C)：1 Ω（典型值）导通电阻平坦度(25°C)：0.23 Ω（典型值）模拟信号范围：V SS 至V DD额定电源电压：±5 V 、12 V 、5 V 和3.3 V ±3.3 V 至±8 V 双电源供电3.3 V 至16 V 单电源供电1.8 V 逻辑兼容性，2.7 V ≤ VL ≤3.3 V 4 mm x 4 mm 、24引脚LFCSP 封装应用通信系统医疗系统音频和视频信号路由自动测试设备数据采集系统电池供电系统采样保持系统继电器替代方案功能框图图1.概述ADGS1612内置四个独立的单刀单掷(SPST)开关。

S331C中文说明书

Site MasterS113C,S114C,S331C,S332C,天线、电缆和频谱分析仪用户指南专门用于传输线和其它射频器件的手持式测试仪目录第一章—概述简介………………………………………………………………..1-1说明………………………………………………………………..1-1标准附件……………………………………………………………1-1选件…………………………………………………………………1-2可选附件……………………………………………………………1-2性能指标…………………………………………………………..1-3维护事项……………………………………………………………1-6校准…………………………………………………………………1-6自动校准InstaCal 模块…………… ………………………………1-7年检………………………………………………………………….1-7第二章—功能和操作简介…………………………………………………………….…….2-1测试连接器面板…………………………………………………….2-1前面板概述………………………………………………………….2-2功能区硬键……………………………………………………………2-3 键盘区硬键…………………………………………………………2-4软键…. ………………………………………………………………2-6功率监测菜单……………………………………………………….2-15符号………………………………………………………………….2-19自检………………………………………………………………….2-19错误代码…………………………………………………………….2-19 自检错误…………..…………………………………………….2-19范围错误……..………………………………………………….2-21自动校准InstaCal错误消息………….…………………………2-22 电池信息…………………………………………….………………2-24新电池充电…………………………………………………………2-24 在Site Master上给电池充电…………………………………….2-24用充电器给电池充电………………………………………………2-24电池充电指示……………………………………………………2-25电池寿命…………………………………………………………..2-25关于电池的重要信息……………………………………………..2-26第三章—操作入门简介…………………………………………………………3-1开机过程……………………………………………………3-1选择频率/距离………………………………………………3-2校准…………………………………………………………..3-2校准确认……………………………………………….3-3手动校准过程………………………………………….3-4自动校准InstaCal 模块确认…………………………3-5自动校准InstaCal模块校准过程……………………. 3-6有测试端口延长电缆的校准………………………3-6 设臵刻度…………………………………………………3-7 自动刻度……………………………………………….3-7幅度刻度………………………………………………3-7 保存和调用设臵………………………………………….3-7 保存设臵……………………………………………...3-7调用设臵……………………………………………..3-8 保存和调用显示…………………………………………3-8 保存显示…………………………………………….3-8调用显示……………………………………………3-8设臵距离和电缆类型……………………………..3-9 改变单位…………………………………………………..3-9改变显示语言……………………………………………..3-9打印………………………………………………………..3-10 打印屏幕……………………………………………..3-10打印机开关设臵……………………………………..3-11 使用软背包……………………………………………….3-12第四章—电缆测量和天线测量简介……………………………………………………….4-1传输线扫描的基本原理………………………………….4-1进行传输线扫描所需的信息…………………………….4-2典型传输线扫描的测试过程…………………………….4-3 系统回波损耗测量………………………………….4-3插入损耗测量………………………………………4-4故障点定位（DTF）传输线测试…………………4-8天线子系统回波损耗测试………………………..4-10第五章—频谱分析仪测量简介……………………………………………………….5-1占用带宽………………………………………………….5-1通道功率测量…………………………………………….5-2 Site Master的通道功率测量…………………………5-2 邻道功率测量…………………………………………….5-4带外杂波散射测量……………………………………….5-6带内/通道外测量…………………………………………5-7场强测量…………………………………………………5-8天线校准………………………………………………….5-9 第六章—功率测量简介………………………………………………………..6-1功率测量…………………………………………………..6-1 第七章—Site Master软件工具简介………………………………………………………… 7-1特点…………………………………………………………7-1系统需求……………………………………………………7-1安装…………………………………………………………7-2 通讯口设臵……………………………………………7-2接口电缆安装………………………………………….7-3 使用软件工具……………………………………………….7-3从Site Master下载图形曲线………………………………..7-3图形获取……………………………………………………..7-3图形属性…………………………………………………….7-4 曲线叠加或图形叠加…………………………………..7-4保存曲线………………………………………………7-5常规电缆列表…………………………………………7-6输入天线因子…………………………………………7-7上载天线因子………………………………………...7-8创建数据库…………………………………………..7-8打印格式……………………………………………..7-8附录 A—参考数据同轴电缆技术数据…………………………………………………A-1附录B—视窗简介…………………………………………………………………B-1 样例…………………………………………………………………B-1第一章概述简介本章对Site Master S113C、S114C、S331C和S332C型号及其性能指标、选用附件、日常维护和校准要求进行了说明。

K4S161622D-LE10中文资料

K4S161622D-TI/E CMOS SDRAM1M x 16 SDRAM512K x 16bit x 2 BanksSynchronous DRAMLVTTLIndustrial/ExtendedTemperatureRevision 1.2Jan 2003Samsung Electronics reserves the right to change products or specification without notice.Rev 1.2 Jan '03K4S161622D-TI/E CMOS SDRAM Revision HistoryRevision 1.0 (June 1999)• Define Industrial Temperature spec of K4S161622DRevision 1.1 (June 2001)• Add Industrial Temperature Specification.Revision 1.2 (Jan 2003)• Changed VDD condition of High speed (over 166MHz) from 3.135V~ 3.6V to 3.0V ~ 3.0V.Rev 1.2 Jan '03K4S161622D-TI/E CMOS SDRAMRev 1.2 Jan '03K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03V DD DQ0DQ1V SSQ DQ2DQ3V DDQ DQ4DQ5V SSQ DQ6DQ7V DDQ LDQM WE CAS RAS CS BA A10/APA0A1A2A3V DD1234567891011121314151617181920212223242550494847464544434241403938373635343332313029282726PIN CONFIGURATION (TOP VIEW)V SS DQ15DQ14V SSQ DQ13DQ12V DDQ DQ11DQ10V SSQ DQ9DQ8V DDQN.C/RFU UDQM CLK CKE N.C A9A8A7A6A5A4V SS50PIN TSOP (II)(400mil x 825mil)(0.8 mm PIN PITCH)PIN FUNCTION DESCRIPTIONPin NameInput FunctionCLK System Clock Active on the positive going edge to sample all inputs.CSChip SelectDisables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQMCKE Clock EnableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.A 0 ~ A 10/AP AddressRow / column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 10, column address : CA 0 ~ CA 7BA Bank Select Address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write EnableEnables write operation and row tches data in starting from CAS, WE active.L(U)DQM Data Input/Output Mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when L(U)DQM active.DQ 0 ~ 15Data Input/Output Data inputs/outputs are multiplexed on the same pins.V DD /V SS Power Supply/Ground Power and ground for the input buffers and the core logic.V DDQ /V SSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFUNo Connection/Reserved for Future UseThis pin is recommended to be left No Connection on the device.K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to Vss V DD , V DDQ-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150°C Power dissipation P D 1W Short circuit currentI OS50mAPermanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Note :DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, Extended T A = -25 to +85°C , Industrial T A = -40 to +85°C) Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ3.0 3.3 3.6V Input logic high votlage V IH 2.0 3.0V DDQ +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mAInput leakage currentI LI-10-10uA3Note :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)Pin Symbol Min Max Unit ClockC CLK 24pF RAS, CAS, WE, CS, CKE, L(U)DQMC IN 24pF Address C ADD 24pF DQ 0 ~ DQ 15C OUT35pF1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN ≤ V DDQ .Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.:DECOUPLING CAPACITANCE GUIDE LINERecommended decoupling capacitance added to power line at board. ParameterSymbol Value Unit Decoupling Capacitance between V DD and V SS C DC10.1 + 0.01uF Decoupling Capacitance between V DDQ and V SSQC DC20.1 + 0.01uF1. V DD and V DDQ pins are separated each other.All V DD pins are connected in chip. All V DDQ pins are connected in chip.2. V SS and V SSQ pins are separated each otherAll V SS pins are connected in chip. All V SSQ pins are connected in chip.Note :K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '031. Unless otherwise notes, Input level is CMOS(V IH /V IL =V DDQ /V SSQ ) in LVTTL.2. Measured with outputs open. Addresses are changed only one time during tcc(min).3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).Note :DC CHARACTERISTICS(Recommended operating condition unless otherwise noted, Extended T A = -25 to +85°C , Industrial T A = -40 to +85°C)ParameterSymbolTest ConditionCASLatency Version Unit Note-50-55-60-70-80-10Operating Current (One Bank Active)I CC1Burst Length =1t RC ≥t RC (min)I o = 0 mA31251201151059585mA22---959580Precharge Standby Current in power-down mode I CC2P CKE ≤V IL (max), t CC = 15ns 2mAI CC2PSCKE & CLK ≤V IL (max), t CC = ∞2Precharge Standby Current in non power-down modeI CC2NCKE ≥V IH (min), CS ≥V IH (min), t CC = 15ns Input signals are changed one time during 30ns15mAI CC2NSCKE ≥V IH (min), CLK ≤V IL (max), t CC = ∞Input signals are stable 5Active Standby Current in power-down modeI CC3P CKE ≤V IL (max), t CC = 15ns 3mAI CC3PS CKE & CLK ≤V IL (max), t CC = ∞3Active Standby Current in non power-down mode (One Bank Active)I CC3NCKE ≥V IH (min), CS ≥V IH (min), t CC = 15ns Input signals are changed one time during 30ns25mAI CC3NS CKE ≥V IH (min), CLK ≤V IL (max), t CC = ∞Input signals are stable 15mAOperating Current (Burst Mode)I CC4I o = 0 mAPage Burst 2Banks Activated t CCD = 2CLKs3160155150140130115mA22---115115100Refresh Current I CC5t RC ≥t RC (min)3110105100909080mA 32---909080Self Refresh CurrentI CC6CKE ≤0.2V1mAK4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03AC OPERATING TEST CONDITIONS (V DD = 3.3V ±0.3V *2, Extended T A = -25 to +85°C , Industrial T A = -40 to +85°C)Parameter Value Unit Input levels (Vih/Vil)2.4 / 0.4V Input timing measurement reference level 1.4V Input rise and fall timetr / tf = 1 / 1ns Output timing measurement reference level 1.4VOutput load condition See Fig. 23.3V1200Ω870ΩOutputV OH (DC) = 2.4V, I OH = -2mAV OL (DC) = 0.4V, I OL = 2mAVtt=1.4V50ΩOutputZ0=50Ω(Fig. 2) AC Output Load Circuit(Fig. 1) DC Output Load Circuit1. The DC/AC Test Output Load of K4S161622D-50/55/60/70 is 30pF.Note :50pF *250pF *11. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and thenrounding off to the next higher integer. Refer to the following clock unit based AC conversion tableNotes :OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)ParameterSymbol VersionUnit Note-50-55-60-70-80-10CASLatency CL 323232323232CLK CLK cycle timet CC(min)5105.5106107108101012ns Row active to row active delay t RRD(min)2CLK 1RAS to CAS delay t RCD(min)333332323222CLK 1Row precharge time t RP(min)333332323222CLK 1Row active time t RAS(min)877775756554CLK 1t RAS(max)100us Row cycle timet RC (min )111010101071079776CLK 1Last data in to row precharge t RDL(min)1CLK 2, 5Last data in to new col.address delay t CDL(min)1CLK 2Last data in to burst stopt BDL(min)1CLK 2Col. address to col. address delay t CCD(min)1CLK Mode Register Set cycle time t MRS(min)2CLK Number of valid output dataCAS Latency=32ea4CAS Latency=21K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '031. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf)=1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Note :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)ParameterSymbol-50-55-60-70-80-10Unit NoteMin Max Min Max Min Max Min Max Min Max Min Max CLK cycle time CAS Latency=3t CC 51000 5.51000610007100081000101000ns 1CAS Latency=210--101012CLK to validoutput delay CAS Latency=3t SAC - 4.5-5- 5.5- 5.5-6-6ns 1, 2CASLatency=2-6-6-6-6-6-8Output datat OH 2-2- 2.5- 2.5- 2.5 - 2.5- ns 2CLK high pulse width CAS Latency=3t CH2-2- 2.5-3-3- 3.5-ns3CAS Latency=2333CLK low pulse widthCAS Latency=3t CL 2-2- 2.5-3-3- 3.5-ns 3CAS Latency=2333Input setup time CAS Latency=3t SS 1.5- 1.5- 1.5- 1.75-2- 2.5-ns 3CAS Latency=22222Input hold time t SH 1-1-1-1-1-1-ns 3CLK to output in Low-Z t SLZ 1-1-1-1-1-1-ns 2CLK to output in Hi-ZCAS Latency=3t SHZ- 4.5-5- 5.5- 5.5 -6-6nsCAS Latency=2-6-6-6-6-6-82. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J".From the next generation, tRDL will be only 2CLK for every clock frequency.ParameterSymbolVersionUnit -50-55-60-70-80-10CLK cycle timet CC(min)5 5.567810ns Row active to row active delay t RRD(min)101112141620ns RAS to CAS delay t RCD(min)1516.518202020ns Row precharge time t RP(min)1516.518202020ns Row active time t RAS(min)4038.542494848ns t RAS(max)100us Row cycle timet RC (min )555560697070nsK4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03SIMPLIFIED TRUTH TABLE(V=Valid, X=Don ′t Care, H=Logic High, L=Logic Low)COMMANDCKEn-1CKEnCSRASCASWEDQMBAA 10/APA 9~ A 0NoteRegisterMode Register Set H X L L L L X OP CODE1, 2RefreshAuto RefreshHH L L L H XX3Self RefreshEntryL 3ExitL H L H H H X X3H X X X 3Bank Active & Row Addr.H X L L H H X V Row Address Read &Column Address Auto Precharge Disable HXLHLHXVL Column Address (A 0~A 7)4Auto Precharge Enable H 4, 5Write &Column Address Auto Precharge Disable H X L H L L X VL Column Address (A 0~A 7)4Auto Precharge EnableH 4, 5Burst Stop H X L H H L X X6PrechargeBank Selection HXL L H L XV L XBoth BanksXHClock Suspend or Active Power DownEntry H L H X X X X XL V V V Exit L H X X X X X Precharge Power Down ModeEntryHLH X X X XXL H H H ExitL HH X X X X LV VVDQMH VX 7No Operation CommandHXH X X X XXLHHH1. OP Code : Operand CodeA 0 ~ A 10/AP , BA : Program keys. (@MRS)2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state.4. BA : Bank select address.If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected.If A 10/AP is "High" at row precharge, BA is ignored and both banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the assoiated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)Note :XK4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03MODE REGISTER FIELD TABLE TO PROGRAM MODESRegister Programmed with MRS Address FunctionA 10/AP RFUA 9W.B.LA 8A 7TMA 6A 5A 4A 3A 2A 1A 0CAS LatencyBTBurst LengthA 8A 7A 6A 5A 4A 3A 2A 1A 0BT = 0Test ModeTypeMode Register SetReserved Reserved Reserved 00110101Write Burst Length A 901Length Burst Single BitLatency Reserved-23Reserved Reserved Reserved ReservedCAS Latency 000011110011001101010101Burst Type 01BT = 1Burst Length Type Sequential Interleave0000111100110011010101011248Reserved Reserved Reserved Full Page 1248Reserved Reserved Reserved ReservedPOWER UP SEQUENCESDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.3. Issue precharge commands for all banks of the devices.4. Issue 2 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode register.cf.) Sequence of 4 & 5 is regardless of the order.The device is now ready for normal operation.Note : 1. If A 9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle.Full Page Length : x4 (1024), x8 (512), x16 (256)BA RFUK4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03BURST SEQUENCE (BURST LENGTH = 4)Initial Address SequentialInterleaveA 1A 00011010101231230230130120123103223013210BURST SEQUENCE (BURST LENGTH = 8)Initial Address Sequential Interleave 000011110101010101234567234567014567012367012345A 1A 0A 200110011123456703456701256701234701234560123456723016745456701236745230110325476321076545476103276543210K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03DEVICE OPERATIONSADDRESS INPUTS (A0 ~ A10/AP): In case x 4The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 11 address input pins (A 0 ~ A 10/AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA during read or write command.: In case x 8The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 11 address input pins (A 0 ~ A 10/AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA during read or write command.: In case x 16The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A 0 ~ A 10/AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA during read or write command.NOP and DEVICE DESELECTWhen RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than sin-gle clock cycle like bank activate, burst read, auto refresh, etc.The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS,CAS, WE and all the address inputs are ignored.POWER-UPSDRAMs must be powered up and initialized in a pre-defined manner to prevent undefined operations.1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.3. Issue precharge commands for both banks of the devices.4. Issue 2 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode reg- ister.cf.) Sequence of 4 & 5 is regardless of the order.The device is now ready for normal operation.CLOCK (CLK)The clock input is used as the reference for all SDRAM opera-tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH . During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and I CC specifications.CLOCK ENABLE (CKE)The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro-zen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock,the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + t SS " before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.BANK ADDRESS (BA): In case x 4This SDRAM is organized as two independent banks of 2,097,152 words x 4 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations.: In case x 8This SDRAM is organized as two independent banks of 1,048,576 words x 8 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations.: In case x 16This SDRAM is organized as two independent banks of 524,288words x 16 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active,read, write, mode register set and precharge operations.K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03MODE REGISTER SET (MRS)The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A 0 ~ A 10/AP and BA in the same cycle as CS,RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A 0 ~ A 2, burst type uses A 3, CAS latency (read latency from column address) uses A 4 ~A 6, vendor specific options or test mode use A 7 ~ A 8, A 10/AP and BA. The write burst length is programmed using A 9. A 7 ~ A 8,A 10/AP , BA must be set to low for normal SDRAM operation.Refer to the table for specific codes for various burst length,burst type and CAS latencies.BANK ACTIVATEThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of t RCD (min) from the time of bank activation. t RCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency.The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD (min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of two banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before the other bank can be sensed reliably. t RRD (min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to beactive to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS (min). Every SDRAM bank activate command must satisfy t RAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS (max). The number of cycles for both t RAS (min) and t RAS (max) can be calculated similar to t RCD specification.BURST READThe burst read command is used to access burst of data on con-secutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD (min) before the burst read com-mand is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read com-mand is determined by the mode register which is already pro-grammed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of out-puts from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank.The burst stop command is valid at every page burst length.BURST WRITEThe burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be com-pleted yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank t RDL after the last data input to be written into the active row. See DQM OPERATION also.DEVICE OPERATIONS (Continued)K4S161622D-TI/ECMOS SDRAMRev 1.2 Jan '03DQM OPERATIONThe DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also.PRECHARGEThe precharge operation is performed on an active bank by asserting low on CS, RAS, WE and A 10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after t RAS (min) is satisfied from the bank active command in the desired bank. t RP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t RP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS (max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when both banks are in idle state.AUTO PRECHARGEThe precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy t RAS (min) and "t RP " for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A 10/AP . If burst read or burst write by asserting high on A 10/AP , the bank is left active until a new command is asserted. Once auto precahrge command is given, no new commands are possible to that particular bank until the bank achieves idle state.BOTH BANKS PRECHARGEBoth banks can be precharged at the same time by using pre-charge all command. Asserting low on CS, RAS, and WE with high on A 10/AP after both banks have satisfied t RAS (min)requirement, performs precharge on both banks. At the end of t RP after performing precharge to all the banks, both banks are in idle state.DEVICE OPERATIONS (Continued)AUTO REFRESHThe storage cells of SDRAM need to be refreshed every 32ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows.An auto refresh command is issued by asserting low on CS,RAS and CAS with high on CKE and WE. The auto refresh com-mand can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by t RFC (min). The minimum number of clock cycles required can be calculated by driving t RFC with clock cycle time and them rounding up to the next higher integer.The auto refresh command must be followed by NOP's until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be per-formed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms.SELF REFRESHThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption.The self refresh mode is entered from both banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE.Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of t RFC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 2048auto refresh cycles immediately after exiting in self refresh mode.。

Luckylight KW3-801A B C 0.80英寸三位数绿色黄色LED数字显示器说明书

Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Features:●0.80″(inch)digit height ●Low power consumption ●High reliability●Excellent characters appearance●Available in common cathode or common anode ●RoHS CompliantDescriptions:●The KW3-801AGB/KW3-801CGB is a 0.80inch (20.32mm)height Triple digit display.●The display provides excellent reliability in bright ambient light.●The deviceis made with white segments and black surface.Applications:●Home appliances ●Instrument panels ●Digital readout displays ●Game console systemsDevice Selection Guide:Part No.Emitting ColorPolarityKW3-801AGB Yellow Green Common Anode KW3-801CGBYellow GreenCommon CathodeTechnical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************PackageDimension:2.54*5=12.7 [0.500]DIG.2DIG.3AENotes:1.All dimensions are in millimeters (inches).2.Tolerance is ±0.25mm (.010″)unless otherwise noted.Triple Digit7-segment LED DisplayTechnical Data SheetInternal Circuit Diagram:Internal Circuit Diagram(Common Anode)KW3-801AGB1298Internal Circuit Diagram(Common Cathode)KW3-801CGB1298Spec No.:W8031A/B Date:16-Mar-2017 Issue No.:G-001-Rev-3E-mail:*******************Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Absolute Maximum Ratings at Ta=25℃ParametersSymbolMaxUnitPower Dissipation Per Segment P d 48mW Peak Forward Current Per Segment (1/10Duty Cycle,0.1ms Pulse Width)I FP 100mA Forward Current Per Segment I F 20mA Reverse Voltage Per Segment V R 5VOperating Temperature Range T opr -40℃to +80℃Storage Temperature Range T stg -40℃to +85℃Soldering TemperatureT sld260℃for 5SecondsElectrical Optical Characteristics at Ta=25℃ParametersSymbolMin.Typ.Max.UnitTest ConditionAverage Luminous Intensity Iv 5.010.0---mcd IF=10mA (Note a)10.020.0---mcdIF=20mA (Note a)Luminous Intensity Matching Ratio I v-m ------2:1IF=10mAPeak Emission Wavelength λp ---575---nm IF=20mA Dominant Wavelength λd ---572---nm IF=20mA (Note b)Spectral Line Half-Width △λ---20---nm IF=20mA Forward Voltage Per Segment V F --- 2.0 2.4V IF=20mA Reverse Current Per SegmentI R------50µAVR=5VNotes:a.Luminous intensity is measured with a light sensor and filter combination that approximates the CIE eye-response curve.b.The dominant wavelength (λd)is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device.Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Typical Electrical /Optical Characteristics Curves (25℃Ambient Temperature Unless Otherwise Noted)Spect r um D i st r i but i onR e la t i v e L u m i n o u s I n t e n s i t y (%)T a=25℃0400100For w ar d C ur r ent & For w ar d V ol t ageF o r w a r d C u r r e n t I F (m A )T a=25℃10203040501.61.82.0 2.2 2.4For w ar d V ol t age V F (V )300500600700800W avel engt h λp (nm )755025Lum i nous I nt ensi t y &A m bi ent T em per at ur eR e l a t i v e L u m i n o u s I n t e n s i t y (%)11000-60A m bi ent T em per at ur e T a (℃)10010-40-20020406080100L um i nous I nt ensi t y & For w ar d C ur r entR e l a t i v e L u m i n o u s I n t e n s i t y (%)1100010For w ar d C ur r ent I F (m A )10010101102103For w ar d C ur r ent D er at i ng C ur veF o r w a r d C u r r e n t I F (m A )010********A m bi ent T em per at ur e T a (℃)f =1K H zD ut y=1/10T a=25℃204060801002.61.4Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Packing &LabelSpecifications:LabelOutside BoxDateSidePearl WoolInner BoxTriple Digit7-segment LED DisplayTechnical Data SheetTerms and conditions for the usage of this document:a.The information included in this document reflects representative usage scenarios and is intended for technicalreference only.b.The part number,type,and specifications mentioned in this document are subject to future change andimprovement without notice.Before production usage customer should refer to the latest datasheet for theupdated specifications.c.When using the products referenced in this document,please make sure the product is being operated within theenvironmental and electrical limits specified in the datasheet.If customer usage exceeds the specified limits, Luckylight will not be responsible for any subsequent issues.d.The information in this document applies to typical usage in consumer electronics applications.If customer'sapplication has special reliability requirements or have life-threatening liabilities,such as automotive or medical usage,please consult with Luckylight representative for further assistance.e.The contents and information of this document may not be reproduced or re-transmitted without permission byLuckylight.f.Over-current-proofCustomer must apply resistors for protection,otherwise slight voltage shift will cause big current change(Burn out will happen).g.Storage1.Before opening the package,the LEDs should be kept at30℃or less and80%RH or less.2.The LEDs should be used within a year.3.After opening the package,the LEDs should be kept at30℃or less and60%RH or less.Spec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Through Hole Display Mounting MethodLead Forming:1.Do not bend the component leads by hand without proper tools.2.The leads should be bent by clinching the upper part of the lead firmly such that the bending force Is not exerted on the plasticbody.Installation:1.The installation process should not apply stress to the lead terminals.2.When inserting for assembly,ensure the terminal pitch matches the substrate board’s hole pitch to prevent spreading or pinching the leadterminals.Not Recommended Recommended3.The component shall be placed at least 5mm from edge of PCB to avoid damage caused excessive heat during wavesoldering.Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************R e c o m m e n d e d W a v e S o ld e rin g P ro file sT e m p e r a t u r e(℃)T im e (s e c)50100150200250300Notes:1.Recommend pre-heat temperature of 105℃or less (as measured with a thermocouple attached to the LED pins)prior to immersion in the solder wave with a maximum solder bath temperature of 260℃.2.Peak wave soldering temperature between 245℃～255℃for 3sec (5sec max).3.Do not apply stress to the epoxy resin while the temperature is above 85℃.4.Fixtures should not incur stress on the component when mounting and during soldering process.5.SAC 305solder alloy is recommended.6.No more than one wave soldering pass.7.During wave soldering,the PCB top-surface temperature should be kept below 105℃.Soldering General Notes:1.Through-hole displays are incompatible with reflow soldering.2.If components will undergo multiple soldering processes,or other processes where the omponents may be subjected to intense heat,please check with luckylight for compatibility.Technical Data SheetTriple Digit 7-segment LED DisplaySpec No.:W8031A/B Date:16-Mar-2017Issue No.:G-001-Rev-3E-mail:*******************Cleaning:d “no-clean”fluxes are recommended for use in soldering.2.If cleaning is required,luckylight recommends to wash components with water only.Do not use harsh organic solvents for cleaning because they may damage the plastic parts.3.The cleaning process should take place at room temperature and the devices should not be washed for more than one minute.4.When water is used in the cleaning process,immediately remove excess moisture from the component with forced-air drying afterwards.Circuit Design Notes:1.Protective current-limiting resistors may be necessary to operate the LEDs within the specified range.2.LEDs mounted in parallel should each be placed in series with its own current-limitingresistor.Recommended Set-up Invalid Set-upGND VSVSGND3.The driving circuit should be designed to protect the LED against reverse voltages and transient voltage spikes when the circuit is powered up or shut down.4.The safe operating current should be chosen after considering the maximum ambient temperature of the operating environment.5.Prolonged reverse bias should be avoided,as it could cause metal migration,leading to an increase in leakage current or causing a short circuit.。

K4S561632E-UC60中文资料

CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)256Mb E-die SDRAM SpecificationRevision 1.3August 2004* Samsung Electronics reserves the right to change products or specification without notice.54 TSOP-II with Pb-Free(RoHS compliant)CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)Revision HistoryRevision 1.0 (May. 2003)- First generation for Pb_free products Revision 1.1 (August. 2003)- Corrected typo in Page #8, 9Revision 1.2 (May. 2004)- Added Note 5. sentense of tRDL parameter Revision 1.3 (August. 2004) - Corrected typo.CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)Part No.Orgainization Max Freq.Interface Package K4S560432E-UC(L)7564M x 4 133MHz LVTTL 54pin TSOP(II)K4S560832E-UC(L)7532M x 8 133MHz LVTTL 54pin TSOP(II)K4S561632E-UC(L)60/7516M x 16133MHzLVTTL54pin TSOP(II)The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro-nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper-ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.• JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3)-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation• DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh• 64ms refresh period (8K Cycle)• 54 TSOP(II) Pb-free Package• RoHS compliantGENERAL DESCRIPTIONFEATURES16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAMOrdering InformationRow & Column address configurationOrganizationRow Address Column Address 64Mx4A0~A12A0-A9, A1132Mx8A0~A12A0-A916Mx16A0~A12A0-A8CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)54Pin TSOP(II) Package DimensionPackage Physical DimensionCMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)FUNCTIONAL BLOCK DIAGRAMLWE LDQMDQi* Samsung Electronics reserves the right to change products or specification without notice.CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)PIN CONFIGURATION (Top view)V DD N.C V DDQ N.C DQ0V SSQ N.C N.C V DDQ N.C DQ1V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/APA0A1A2A3V DD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928V SS N.C V SSQ N.C DQ3V DDQ N.C N.C V SSQ N.C DQ2V DDQ N.C V SSN.C/RFU DQM CLK CKE A12A11A9A8A7A6A5A4V SS54Pin TSOP(400mil x 875mil)(0.8 mm Pin pitch)PIN FUNCTION DESCRIPTIONPin NameInput FunctionCLK System clock Active on the positive going edge to sample all inputs.CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMCKEClock enableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.A 0 ~ A 12AddressRow/column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 12,Column address : (x4 : CA 0 ~ CA 9,CA 11), (x8 : CA 0 ~ CA 9), (x16 : CA 0 ~ CA 8)BA 0 ~ BA 1Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write enableEnables write operation and row tches data in starting from CAS, WE active.DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.DQ 0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins.(x4 : DQ 0 ~ 3), (x8 : DQ 0 ~ 7), (x16 : DQ 0 ~ 15)V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFUNo connection/reserved for future useThis pin is recommended to be left No Connection on the device.V DD DQ0V DDQ N.C DQ1V SSQ N.C DQ2V DDQ N.C DQ3V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ7V SSQ N.C DQ6V DDQ N.C DQ5V SSQ N.C DQ4V DDQ N.C V SSN.C/RFU DQM CLK CKE A12A11A9A8A7A6A5A4V SSV DD DQ0V DDQ DQ1DQ2V SSQ DQ3DQ4V DDQ DQ5DQ6V SSQ DQ7V DD LDQM WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ15V SSQ DQ14DQ13V DDQ DQ12DQ11V SSQ DQ10DQ9V DDQ DQ8V SSN.C/RFU UDQM CLK CKE A12A11A9A8A7A6A5A4V SSx16x8x4x16x8x4CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to Vss V DD , V DDQ-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150°C Power dissipation P D 1W Short circuit currentI OS50mAPermanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Note :DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C) Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mAInput leakage currentI LI-10-10uA31. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN ≤ V DDQ .Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.Notes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)PinSymbol Min Max Unit NoteClockC CLK 2.5 3.5pF RAS, CAS, WE, CS, CKE, DQM C IN 2.5 3.8pF AddressC ADD2.53.8pF (x4 : DQ 0 ~ DQ 3), (x8 : DQ 0 ~ DQ 7), (x16 : DQ 0 ~ DQ 15) C OUT4.06.0pFCMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)ParameterSymbolTest ConditionVersion Unit Note75Operating current (One bank active)I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA80mA 1Precharge standby current in power-down mode I CC2P CKE ≤ V IL (max), t CC = 10ns 2mAI CC2PS CKE & CLK ≤ V IL (max), t CC = ∞2Precharge standby current in non power-down mode I CC2NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns20mAI CC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 10Active standby current in power-down mode I CC3PCKE ≤ V IL (max), t CC = 10ns6mA I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞6Active standby current in non power-down mode (One bank active)I CC3N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns 25mA I CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25mAOperating current (Burst mode)I CC4 I O = 0 mA Page burst4banks Activated.t CCD = 2CLKs 100mA 1Refresh current I CC5t RC ≥ t RC (min)180mA 2Self refresh currentI CC6CKE ≤ 0.2VC 3mA 3L1.5mA41. Measured with outputs open.2. Refresh period is 64ms.3. K4S5604(08)32E-UC4. K4S5604(08)32E-UL5. Unless otherwise noticed, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ).Notes :DC CHARACTERISTICS (x4, x8)CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)ParameterSymbolTest ConditionVersion Unit Note6075Operating current (One bank active)I CC1Burst length = 1t RC ≥ t RC (min)I O = 0 mA14090mA 1Precharge standby current in power-down modeI CC2P CKE ≤ V IL (max), t CC = 10ns 2mA I CC2PS CKE & CLK ≤ V IL (max), t CC = ∞2Precharge standby current in non power-down mode I CC2N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns 20mAI CC2NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 10Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 6mA I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞6Active standby current in non power-down mode (One bank active)I CC3N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns 25mA I CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25mAOperating current (Burst mode)I CC4I O = 0 mA Page burst4banks Activated.t CCD = 2CLKs 170130mA 1Refresh current I CC5t RC ≥ t RC (min)200180mA 2Self refresh currentI CC6CKE ≤ 0.2VC 3mA 3 L1.5mA41. Measured with outputs open.2. Refresh period is 64ms.3. K4S561632E-UC4. K4S561632E-UL5. Unless otherwise noticed, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ).Notes :DC CHARACTERISTICS (x16)CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)Parameter Value Unit AC input levels (Vih/Vil)2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall timetr/tf = 1/1ns Output timing measurement reference level 1.4VOutput load conditionSee Fig. 23.3V1200Ω870ΩOutput50pFV OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mAVtt = 1.4V50ΩOutput50pFZ0 = 50Ω(Fig. 2) AC output load circuit(Fig. 1) DC output load circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)ParameterSymbol VersionUnit Note 6075Row active to row active delay t RRD (min)1215ns 1RAS to CAS delay t RCD (min)1820ns 1Row precharge time t RP (min)1820ns 1Row active time t RAS (min)4245ns 1t RAS (max)100us Row cycle timet RC (min)6065ns 1Last data in to row precharge t RDL (min)2CLK 2, 5Last data in to Active delayt DAL (min) 2 CLK + tRP-5Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stopt BDL (min)1CLK 2Col. address to col. address delay t CCD (min)1CLK 3Number of valid output dataCAS latency=32ea4CAS latency=2-11. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle timeand then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .Notes :CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)DQ BUFFER OUTPUT DRIVE CHARACTERISTICSParameterSymbol ConditionMin TypMax Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall timetfhMeasure in linear region : 1.2V ~ 1.8V2.02.9 5.0Volts/ns1,21. Rise time specification based on 0pF + 50 Ω to V SS , use these values to design to.2. Fall time specification based on 0pF + 50 Ω to V DD , use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to V SS .Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)ParameterSymbol 6075Unit Note Min Max Min Max CLK cycle time CAS latency=3t CC 610007.51000ns 1CAS latency=2-10CLK to valid output delay CAS latency=3t SAC 5 5.4ns 1,2CAS latency=2-6Output data hold timeCAS latency=3t OH 2.53ns 2CAS latency=2-3CLK high pulse width t CH 2.5 2.5ns 3CLK low pulse width t CL 2.5 2.5ns 3Input setup time t SS 1.5 1.5ns 3Input hold time t SH 10.8ns 3CLK to output in Low-Z t SLZ 11ns2CLK to output in Hi-ZCAS latency=3t SHZ5 5.4nsCAS latency=2-61. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Notes :CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)I OH Characteristics (Pull-up)Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min (V)I (mA)I (mA)I (mA)3.45 -2.43.3 -27.33.0 0.0 -74.1 -0.72.6-21.1-129.2 -7.52.4-34.1-153.3-13.32.0-58.7-197.0-27.51.8-67.3-226.2-35.5 1.65-73.0-248.0-41.11.5-77.9-269.7-47.91.4-80.8-284.3-52.41.0-88.6-344.5-72.50.0-93.0-502.4-93.0IBIS SPECIFICATIONI OL Characteristics (Pull-down)Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min (V)I (mA)I (mA)I (mA)0.0 0.0 0.0 0.00.427.5 70.217.7 0.6541.8107.526.9 0.8551.6133.833.31.058.0151.237.61.470.7187.746.61.572.9194.448.0 1.6575.4202.549.51.877.0208.650.7 1.9577.6212.051.53.080.3219.654.2 3.4581.4222.654.90-100-200-300-400-500-600030.511.522.53.5Voltagem A250200150100500030.511.522.53.5Voltagem A66MHz and 100MHz/133MHz Pull-up66MHz and 100MHz/133MHz Pull-downI OH Min (100MHz)I OH Max (66 and 100MHz)I OH Min (66MHz)I OL Min (100MHz)I OL Max (100MHz)I OL Min (66MHz)CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)V DD Clamp @ CLK, CKE, CS, DQM & DQV DD (V)I (mA)0.00.00.20.00.40.00.60.00.70.00.80.00.90.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.618.31V SS Clamp @ CLK, CKE, CS, DQM & DQV SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.0 0.00.0201510500312Voltagem AI (mA)Voltagem AI (mA)Minimum V DD clamp current(Referenced to V DD )Minimum V SS clamp current0-10-20-30-40-30-2-1-50-60CMOS SDRAMRev. 1.3 August 2004SDRAM 256Mb E-die (x4, x8, x16)SIMPLIFIED TRUTH TABLE (V=Valid, X=Don't care, H=Logic high, L=Logic low)CommandCKEn-1CKEnCSRASCASWEDQMBA 0,1A 10/APA 0 ~ A 9 A 11, A 12NoteRegisterMode register set H X L L L L X OP code1,2RefreshAuto refreshH H L L L H X X 3Self refreshEntry L 3ExitL H L H H H X X3H X X X 3Bank active & row addr.H X L L H H X V Row address Read &column address Auto precharge disable H X L H L H X V L Column address 4Auto precharge enable H 4,5Write &column address Auto precharge disable H X L H L L X VL Column address4Auto precharge enableH 4,5Burst stop HX L H H L X X 6Precharge Bank selection H X L L H L X V L XAll banksX H Clock suspend or active power downEntry H L H X X X X XL V V V Exit L H X X X X X Precharge power down modeEntryH L H X X X XXL H H H ExitL HH X X X X L V V V DQMH X V X 7No operation commandHXH X X X XXLHHHNotes :1. OP Code : Operand codeA 0 ~ A 12 & BA 0 ~ BA 1 : Program keys. (@ MRS)2. MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)。

AP3216CGCK中文资料

5 DRAWN: W.J.ZHU
PAGE: 3 OF 4 ERP:1203000333
元器件交易网
AP3216CGCK
Recommended Soldering Pattern (Units : mm)
Tape Specifications (Units : mm)
Absolute Maximum Ratings at TA=25°C
Parameter Power dissipation DC Forward Current Peak Forward Current [1] Reverse Voltage Operating/Storage Temperature
Note: 1. 1/10 Duty Cycle, 0.1ms Pulse Width.
Green 105 30 150 5 -40°C To +85°C
Units mW mA mA V
SPEC NO: DSAA6052 APPROVED: J. Lu
REV NO: V.5 CHECKED: Allen Liu
Electrical / Optical Characteristics at TA=25°C
Symbol λpeak λD ∆λ1/2 C VF IR Parameter Peak Wavelength Dominant Wavelength Spectral Line Half-width Capacitance Forward Voltage Reverse Current Green Green Green Green Green Green Device Typ. 574 570 20 15 2.1 2.5 10 Max. Units nm nm nm pF V uA Test Conditions IF=20mA IF=20mA IF=20mA VF=0V;f=1MHz IF=20mA VR = 5V

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Document Title2Mx16 bit Uni-Transistor Random Access MemoryThe attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.Revision HistoryRevision No.0.00.1RemarkAdvanced PreliminaryHistoryInitial DraftRevised- Changed Package Type from 48 TBGA into 48 FBGA 6.0 x 8.0- Changed Standby Current(CMOS) from 80uA to 100uADraft DateJanuary 16, 2003June 9, 2003PRODUCT FAMILYProduct FamilyOperating Temp.Vcc RangeSpeedPower DissipationPKG TypeStandby (I SB1, Max.)Operating (I CC2, Max.)K1S3216B1C-I Industrial(-40~85°C) 1.7V~2.1V 70/85ns 100µA30mA48-FBGA-6.0x8.02M x 16 bit Uni-Transistor CMOS RAMGENERAL DESCRIPTIONThe K1S3216B1C is fabricated by SAMSUNG ′s advanced CMOS technology using one transistor memory cell. The device supports Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports dual chip selection for user interface.FEATURES• Process Technology: CMOS • Organization: 2M x16 bit• Power Supply Voltage: 1.7V~2.1V • Three State Outputs• Compatible with Low Power SRAM • Dual Chip selection support• Package Type: 48-FBGA-6.0x8.0SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice .1) Reserved for future use.Name Function Name Function CS 1,CS 2Chip Select Inputs Vcc Power OE Output Enable Input Vss GroundWE Write Enable Input UB Upper Byte(I/O 9~16)A 0~A 20Address InputsLB Lower Byte(I/O 1~8)I/O 1~I/O 16Data Inputs/OutputsNCNo Connection 1)FUNCTIONAL BLOCK DIAGRAMClk gen.Row selectI/O 1~I/O 8Data cont Data cont Data contI/O 9~I/O 16Vcc VssPrecharge circuit.Memory arrayI/O Circuit Column selectWE OE UB CS 1LBControl LogicCS 2RowAddressesColumn AddressesPIN DESCRIPTION48-FBGA: Top View(Ball Down)LB OE A0A1A2CS 2I/O9UB A3A4CS 1I/O1I/O10I/O11A5A6I/O2I/O3Vss I/O12A17A7I/O4VccVcc I/O13NC A16I/O5VssI/O15I/O14A14A15I/O6I/O7I/O16A19A12A13WE I/O8A18A8A9A10A11A20123456A B C D E F G HPOWER UP SEQUENCE1. Apply power.2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS1=high.or CS2=low.TIMING WAVEFORM OF POWER UP(1) (CS 1 controlled)TIMING WAVEFORM OF POWER UP(2) (CS 2 controlled)POWER UP(2)1. After V CC reaches V CC (Min.), wait 200µs with CS 2 low. Then the device gets into the normal operation.V CCCS 1CS 2V POWER UP(1)1. After V CC reaches V CC (Min.), wait 200µs with CS 1 high. Then the device gets into the normal operation.V CCCS 1CS 2V Normal OperationPower Up ModeFUNCTIONAL DESCRIPTIONCS1CS2OE WE LB UB I/O1~8I/O9~16Mode PowerH X1)X1)X1)X1)X1)High-Z High-Z Deselected StandbyX1)L X1)X1)X1)X1)High-Z High-Z Deselected Standby X1)X1)X1)X1)H H High-Z High-Z Deselected Standby L H H H L X1)High-Z High-Z Output Disabled Active L H H H X1)L High-Z High-Z Output Disabled Active L H L H L H Dout High-Z Lower Byte Read Active L H L H H L High-Z Dout Upper Byte Read Active L H L H L L Dout Dout Word Read Active L H X1)L L H Din High-Z Lower Byte Write Active L H X1)L H L High-Z Din Upper Byte Write Active L H X1)L L L Din Din Word Write Active1. X means don′t care.(Must be low or high state)ABSOLUTE MAXIMUM RATINGS1)Item Symbol Ratings Unit Voltage on any pin relative to Vss V IN, V OUT-0.2 to V CC+0.3V V Voltage on Vcc supply relative to Vss V CC-0.2 to 2.5V V Power Dissipation P D 1.0W Storage temperature T STG-65 to 150°C Operating Temperature T A-40 to 85°C1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-ability.RECOMMENDED DC OPERATING CONDITIONS 1)1. T A =-40 to 85°C, otherwise specified.2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.3. Undershoot: -1.0V in case of pulse width ≤20ns.4. Overshoot and undershoot are sampled, not 100% tested.ItemSymbol Min Typ Max Unit Supply voltage Vcc 1.7 1.8/2.0 2.1V GroundVss 000V Input high voltage V IH 1.4-V CC +0.22)V Input low voltageV IL-0.23)-0.4VCAPACITANCE 1)(f=1MHz, T A =25°C)1. Capacitance is sampled, not 100% tested.ItemSymbol Test ConditionMin Max Unit Input capacitance C IN V IN =0V -8pF Input/Output capacitanceC IOV IO =0V-10pFDC AND OPERATING CHARACTERISTICSItemSymbolTest ConditionsMin Typ Max Unit Input leakage current I LI V IN =Vss to Vcc-1-1µA Output leakage currentI LO CS 1=V IH or CS 2=V IL or OE=V IH or WE=V IL or LB=UB=V IH , V IO =Vss to Vcc-1-1µA Average operating currentI CC1Cycle time=1µs, 100% duty, I IO =0mA, CS 1≤0.2V, LB ≤0.2V or/and UB ≤0.2V, CS 2≥V CC -0.2V, V IN ≤0.2V or V IN ≥V CC -0.2V --5mA I CC2Cycle time=Min, I IO =0mA , 100% duty, CS 1=V IL, CS 2=V IH LB=V IL or/and UB=V IL , V IN =V IH or V IL --30mA Output low voltage V OL I OL = 0.1mA --0.2V Output high voltage V OH I OH = -0.1mA1.4--V Standby Current(CMOS)I SB1Other inputs=0~Vcc1) CS 1≥V CC -0.2V , CS 2≥V CC -0.2V(CS 1 controlled) or 2) 0V ≤ CS 2 ≤ 0.2V(CS 2 controlled)--100µAPRODUCT LISTIndustrial Temperature Products(-40~85°C)Part Name FunctionK1S3216B1C-FI70K1S3216B1C-FI8548-FBGA, 70ns, 1.8V/2.0V 48-FBGA, 85ns, 1.8V/2.0VAC OPERATING CONDITIONSTEST CONDITIONS (Test Load and Test Input/Output Reference)Input pulse level: 0.2 to Vcc-0.2V Input rising and falling time: 5nsInput and output reference voltage: 0.5 x V CC Output load (See right): C L =50pFC L1. Including scope and jig capacitanceDoutAC CHARACTERISTICS (Vcc=1.7~2.1V, T A =-40 to 85°C)1. t WP (min)=70ns for continuous write operation over 50 times.Parameter ListSymbolSpeed BinsUnits70ns85nsMinMax Min Max ReadRead Cycle Time t RC 70-85-ns Address Access Time t AA -70-85ns Chip Select to Output t CO -70-85ns Output Enable to Valid Output t OE -35-40ns UB, LB Access Timet BA -70-85ns Chip Select to Low-Z Output t LZ 10-10-ns UB, LB Enable to Low-Z Output t BLZ 10-10-ns Output Enable to Low-Z Output t OLZ 5-5-ns Chip Disable to High-Z Output t HZ 025025ns UB, LB Disable to High-Z Output t BHZ 025025ns Output Disable to High-Z Output t OHZ 025025ns Output Hold from Address Change t OH 5-5-ns WriteWrite Cycle Timet WC 70-85-ns Chip Select to End of Write t CW 60-70-ns Address Set-up Time t AS 0-0-ns Address Valid to End of Write t AW 60-70-ns UB, LB Valid to End of Writet BW 60-70-ns Write Pulse Width t WP 551)-601)-ns Write Recovery Time t WR 0-0-ns Write to Output High-Z t WHZ 025025ns Data to Write Time Overlap t DW 30-35-ns Data Hold from Write Time t DH 0-0-ns End Write to Output Low-Zt OW5-5-nsAddressData OutTIMING DIAGRAMSTIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS 1=OE=V IL , CS 2=WE=V IH , UB or/and LB=V IL )TIMING WAVEFORM OF READ CYCLE(2) (WE=V IH )Data ValidHigh-Zt RCCS 1AddressUB, LBOEData outt OHt AA t COt BAt OEt OLZ t BLZt LZ t OHZt BHZt HZNOTES (READ CYCLE)1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection.3. t OE (max) is met only when OE becomes enabled after t AA (max).4. If invalid address signals shorter than min. t RC are continuously repeated for over 4us, the device needs a normal read timing(t RC ) or needs to sustain standby state for min. t RC at least once in every 4us.CS 2TIMING WAVEFORM OF WRITE CYCLE(2) (CS 1 Controlled)AddressUB, LBWEData inData out High-Z High-ZCS 1CS 2TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)AddressCS 1UB, LBWEData inData outCS 2AddressData ValidUB, LBWEData inData outHigh-Z High-ZTIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)NOTES (WRITE CYCLE)1. A wri t e occurs during the overlap(t WP ) of low CS 1 and low WE. A write begins when CS 1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-sition when CS 1 goes high and WE goes high. The t WP is measured from the beginning of write to the end of write.2. t CW is measured from the CS 1 going low to the end of write.3. t AS is measured from the address valid to the beginning of write.4. t WR is measured from the end of write to the address change. t WR is applied in case a write ends with CS 1 or WE going high.t WCt CW(2)t BWt WP(1)t DH t DWt WR(4)t AWt AS(3)CS1CS2TIMING WAVEFORM OF WRITE CYCLE(3) (CS 2 Controlled)AddressData ValidUB, LBWEData inData out High-Z High-Zt WCt CW(2)t AWt BW t WP(1)t DHt DWt WR(4)t AS(3)CS 1CS 2PACKAGE DIMENSIONBottom ViewTop ViewSide ViewDetail AMinTyp Max A -0.75-B 5.90 6.00 6.10B1- 3.75-C 7.908.008.10C1- 5.25-D 0.400.450.50E -0.90 1.00E1-0.55-E20.300.350.40Y--0.08Notes.1. Bump counts: 48(8 row x 6 column)2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)3. All tolerence are ±0.050 unless specified beside figures.4. Typ : Typical5. Y is coplanarity: 0.08(Max)Unit: millimeters48 FINE PITCH BALL GRID ARRAY(0.75mm ball pitch)。