CXL1517中文资料

CMOS-CCD Signal ProcessorDescriptionThe CXL1517M/1518M are CMOS-CCD signal processors developed for CCD camera complementary color filter array processing system.CXL1517M452.5-bit ×2, 453.5-bit 1H CCD delay line CXL1518M300.5-bit ×2, 301.5-bit 1H CCD delay line Features•Single 5V power supply•Low power consumption (Typ.)CXL1517M 120mW CXL1518M 75mW•Built-in peripheral circuits•Built-in CDS (Correlated Double Sampling) circuit Functions •Clock driver•Autobias circuit (Center and black) •Pedestal clamp circuit •CDS circuit•Overflow prevention circuitAbsolute Maximum Ratings (Ta = 25°C)•Supply voltage V DD 6V •Operating temperature Topr –10 to +65°C •Storage temperature Tstg –55 to +150°C •Allowable power dissipation P D 500mWRecommended Operating Voltage Range (Ta = 25°C)Supply voltage V DD 4.6 to 5.25V– 1–E91777A78-PSSony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.CXL1517M/1518M20 pin SOP (Plastic)StructureCMOS-CCDItemSymbol V L V H f CL f CLMin.V SS 0.7 ×V DDTyp.7.164.77Max.0.3 ×V DDV DDUnit V V MHz MHzRemarksNTSC: 455f H CCIR: 454f H NTSC: 910f H /3CCIR: 908f H /3Clock voltage Low Clock voltage High Clock frequencyCXL1517M CXL1518M– 2–Block Diagram and Pin Configuration (Top View)V D DV D DA B O V FV D DV G GIN-B IN-A V S SD L 1X D L 2V S SV S SC D SC LPOUT-COUT-AOUT-B IN-C V SS IN-B ABBL V DD IN-C CLP V DD OUT-C V GG IN-A ABCN V DD XDL1XDL2V SS V SS OUT-ACDS ABOVF OUT-BPin DescriptionPin No.Symbol I/O Description CommentV SSIN-B ABBL V DDIN-C CLPV DD OUT-C V GG OUT-B OUT-A CDSV SSV SS XDL2 XDL1 V DD ABCN ABOVF IN-A —IO—II—OOOOO——II—OOIGNDSignal input B channel (Y)Autobias DC output for Y signalPower supplySignal input C channel (Y)Clamp pulse inputPower supplySignal output C channelOutput circuit bias DC outputSignal output B channelSignal output A channelDC output for CDSGNDGNDClock pulse input 2Clock pulse input 1Power supplyAutobias DC output for C signalAutobias DC output for overflow prevention circuitSignal input A channel (C)AnalogBlack level biasAnalogBlack level biasat no clamp >100k>100kOutput circuitOutput circuitTiming>100k>100kTimingCenter level biasCenter level biasat no clamp >100k1234567891011121314151617181920– 3––CXL1517M/1518ME l e c t r i c a l C h a r a c t e r i s t i c sf C L = 7.16M H z (C X L 1517M )T a = 25°C , V D D = 5.0V , V S S = 0Vf C L = 4.77M H z (C X L 1518M )I t e m A u t o b i a s c e n t e r l e v e l A u t o b i a s b l a c k l e v e l O v e r f l o w p r e v e n t i o n c i r c u i t A u t o b i a s l e v e lC D S s o u r c e l e v e l O u t p u t c i r c u i t b i a s l e v e l C u r r e n t ∗s u p p l yI n s e r t i o n g a i n F r e q u e n c y ∗r e s p o n s eL i n e a r i t y T h e i n s e r t i o n g a i n d i f f e r e n c e b e t w e e n c h a n n e l sL i n e a r i t y d i f f e r e n c e b e t w e e n c h a n n e l s C r o s s -t a l k b e t w e e n c h a n n e l s A B C N A B B LA B O V FC D SV G GI D DI G f GL i n .∆G ∆L B C C R T V 1V 2V 3V 4V 5A 1V 6V 6V 6V 6S y m b o lT e s t p o i n tS W c o n d i t i o n s B i a s c o n d i t i o n sS W 1aaaaab b bc b b b b b a a a b b b b a a a a a a a t o c a t o c a t o ca t o c aa a a a a a aa ab S W 2S W 3S W 4t o 6E 1M i n .4.23.92.61.20.3——–4.5–1.5–1.8004.64.33.02.30.82415–3.5–0.4–0.855114.84.53.33.53.03525———121253VVVVVm Ad Bd B%%%%T y p .M a x .C o n d i t i o n s 20 l o g 20 l o gN o t e 1)N o t e 2)N o t e 3)N o t e 4)R a t i n g s U n i tC X L 1517MC X L 1518MC X L 1517MC X L 1518MB c h →C c hO u t p u t a m p l i t u d e (m V p -p )I n p u t a m p l i t u d e (S I N 100k H z , 100m V p -p )↑↓↑↓V 1A →V 1B ,C →V 2+ 0.25V↓A →V 1B ,C →V 2+ 0.25V O u t p u t a m p l i t u d e (S I N 1M H z , 100m V p -p )O u t p u t a m p l i t u d e (S I N 100k H z , 100m V p -p )∗S t a n d a r d v a l u e s a r e d i f f e r e n t b e t w e e n C X L 1517M a n d C X L 1518M .元器件交易网– 5–Notes)1)Linearity testingFor A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as: Lin. = ×200 [%]2)Calculation of insertion gain differenceAs the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin,the insertion gain difference between channels ∆G as: ∆G = |1 – 10()|×100 [%] 3)Calculation of linearity differenceDefine B channel linearity as L B and C channel linearily as L C we obtain the difference ∆L BC as: ∆L BC = |L B – L C |[%]4)Cross-talk calculation CRTa :The cross-talk value of A channel when B and C channels are inputOUT A -a:The output value of A channel when A channel is input SW3-a, SW4-a, SW5, 6-bOUT A -bc :The output value of A channel when B and C channels are input(Cross-talk component) SW3-a, SW4-b, SW5, 6-a CRTa = ×100 [%]Clock Waveform TimingSout max – Sout min Sout max + Sout minGmax – Gmin 20OUT A -bcOUT A -a(140) ∗∗ The value in brackets is for CXL1517M.– 6–XDL XDL Output AOutput BOutput C Electrical Characteristics Test CircuitApplication CircuitApplication circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.Package Outline Unit: mmSONY CODE EIAJ CODE JEDEC CODE SOP-20P-L01SOP020-P-0300PACKAGE STRUCTUREPACKAGE MATERIALLEAD TREATMENTLEAD MATERIALPACKAGE MASSCOPPER ALLOYSOLDER PLATINGEPOXY RESIN0.3g20PIN SOP (PLASTIC)12.45 – 0.1+ 0.420110.45 ± 0.1 1.271015.3–.1+.37.9±.46.9+ 0.4– 7–。