Common-mode currents and EMI in non-isolated power supplies
共模电感 英语

共模电感英语Common mode inductors, also known as common mode chokes, are essential components used in a wide range of electronic devices like power supplies, filters, and amplifiers. These inductors help to suppress electromagnetic interference (EMI) and noise by filtering the common mode signals.Step 1: Understanding the Basics of Common Mode InductorsA common mode inductor consists of two coils wound on a core that has a high magnetic permeability. These two coils are positioned next to each other and are connected in parallel. The input currents flow through both coils in the same direction, providing a high impedance to any common mode noise. While the differential mode currents pass through only one of the coils, providing a low impedance path.Step 2: Advantages of Using Common Mode InductorsCommon mode inductors offer several advantages, including:- EMI Suppression: One of the primary benefits of using common mode inductors is that they help to suppress electromagnetic interference (EMI). This is especially important in applications involving sensitive electronic equipment.- Noise Reduction: Common mode inductors also filter out noise, providing a much cleaner power supply to sensitive applications.- High Reliability: Common mode inductors are highly reliable and can operate even in harsh and demandingenvironments.Step 3: Applications of Common Mode InductorsCommon mode inductors are commonly used in a variety of electronic applications, including:- Power Supplies: Common mode inductors are used in power supplies to suppress EMI and provide a clean and reliable power supply.- Filters: They are also used in RF bandpass filters, band-reject filters, and other types of filters.- Audio Amplifiers: Common mode inductors can help to reduce noise in audio amplifiers.Step 4: ConclusionOverall, common mode inductors are an essential component in electronics design, helping to suppress EMI, reduce noise, and provide clean and reliable power. With their high reliability and versatility, they are a must-have electronic component for a variety of applications.。
压敏电阻的应用实例

压敏电阻的应用实例English Answer.1. Overvoltage Protection.In electronic circuits, overvoltage protection is critical to prevent damage to sensitive components. A surge suppressor is commonly used for this purpose, and it shunts excess voltage to ground.Transient voltage suppression (TVS) diodes and metal oxide varistors (MOVs) are two types of surge suppressors. However, they have different characteristics.TVS diodes are semiconductor devices that conduct in the reverse direction when the voltage exceeds a certain threshold. They offer fast response times and low capacitance, making them suitable for protecting against high-energy transients.MOVs, on the other hand, are ceramic-based devicesthat exhibit non-linear resistance. They have a higher voltage threshold than TVS diodes but offer better surge current handling capability.2. EMI/RFI Suppression.Electromagnetic interference (EMI) and radio frequency interference (RFI) can cause signal distortion, noise, and performance degradation in electronic systems.Ferrites and common-mode chokes are commonly used to suppress EMI and RFI.Ferrites are magnetic materials that exhibit high permeability at high frequencies. They can be used to create inductors that suppress unwanted high-frequency signals.Common-mode chokes are transformers with a specific winding configuration that blocks common-mode noise while allowing differential signals to pass through.3. Voltage Regulation.Voltage regulators are used to maintain a stable voltage level in electronic circuits. Varistors can be used as voltage regulators due to their non-linear resistance特性.When the voltage rises above a certain threshold, the varistor's resistance decreases, allowing more current to flow and thus regulating the output voltage.Varistors offer a simple and cost-effective solution for voltage regulation in applications where precise voltage control is not required.4. Load Protection.Inrush current can damage sensitive electronic components during startup. NTC thermistors can be used to limit the inrush current.NTC thermistors have a high resistance when cold, which limits the current flow during startup. As the thermistor heats up, its resistance decreases, allowing more current to pass through.This characteristic makes NTC thermistors ideal for protecting loads from excessive inrush current.5. Signal Conditioning.Voltage-dependent resistors (VDRs) can be used in signal conditioning circuits to vary the resistance based on the applied voltage.VDRs are typically used as voltage dividers or attenuators. By varying the applied voltage, the output voltage can be adjusted to the desired level.Chinese Answer.1. 过压保护。
反激式开关电源外文翻译

Measurement of the Source Impedance of Conducted Emission Using Mode Separable LISN: Conducted Emission of a Switching Power SupplyJUNICHI MIY ASHITA,1 MASAYUKI MITSUZAW A,1 TOSHIYUKI KARUBE,1KIYOHITO Y AMASAW A,2 and TOSHIRO SA TO21Precision Technology Research Institute of Nagano Prefecture, Japan2Shinshu University, JapanSUMMARYIn the procedure for reducing conducted emissions, it is helpful to know the noise source impedance. This paper presents a method of measuring noise source complex impedances of common and differential mode separately. We propose a line impedance stabilization network (LISN) to measure common and differential mode noise separately without changing LISN impedances of each mode. With this LISN, conducted emissions of each mode are measured inserting appropriate impedances at the equipment under test (EUT) terminal of the LISN. Noise source complex impedances of switching power supply are well calculated from measured results. © 2002 Scripta Technica, Electr Eng Jpn, 139(2): 72 78, 2002; DOI 10.1002/eej.1154Key words:Conducted emission; noise terminal voltage; noise source impedance; line impedance stabiliza-tion network (LISN); EMI.1. IntroductionSwitching power supplies are employed widely in various devices. High-speed on/off operation is accompa-nied by harmonic noise that may cause electromagnetic interference (EMI) with communication devices and other equipment. To prevent the interference, methods of meas-urement and limit values have been set for conducted noise (~30 MHz) and radiated noise (30 to 1000 MHz). Much time and effort are required to contain the noise within the limit values; hence, the efficiency of noise removal tech-niques is an urgent social problem. Understanding of the mechanism behind noise generation and propagation is necessary in order to develop efficient measures. In particu-lar, the propagation of conducted noise must be investi-gated.Modeling and analysis of equivalent circuits have been carried out in order to investigate conducted noise caused by switching [1, 2]. However, the stray capacitance and other circuit parameters of each device must be known in order to develop an equivalent circuit, which is not practicable in the field of noise removal. On the other hand, noise filters and other noise-removal devices do not actually provide the expected effect [3, 4], which is explained by the difference between the static characteristics measured at an impedance of 50 Ω, and the actual impedance. Thus, it is necessary to know the noise source impedance in order to analyze the conducted noise.Regulations on the measurement of noise terminal voltage [5] suggest using LISN; in particular, the vector sum (absolute voltage) of two propagation modes, namely, common mode and differential mode, is measured in terms of the frequency spectrum. Such a measurement, however, does not provide phase data, and propagation modes cannot be separated; therefore, the noise source impedance cannot be derived easily. There are publications dealing with the calculation of the noise source impedance; for example, common mode is only considered as the principal mode, and the absolute value of the noise source impedance for the common mode is found from the ground wire current and ungrounded voltage [6], or mode-separated measure-ment is performed by discrimination between grounded and ungrounded devices [7]. However, measurement of the ground wire current is impossible in the case of domestic single-phase two-line devices. The complex impedance can be found using an impedance analyzer in the nonoperating state, but its value may be different for the operating state. Thus, there is no simple and accurate method of measuring source noise impedance as a complex impedance.© 2002 Scripta TechnicaElectrical Engineering in Japan, V ol. 139, No. 2, 2002Translated from Denki Gakkai Ronbunshi, V ol. 120-D, No. 11, November 2000, pp. 1376 1381The authors assumed that the noise source impedance could be found easily using only a spectrum analyzer, provided that the noise could be measured separately for each mode, and the LISN impedance could be varied. For this purpose, a LISN with a balun transformer was devel-oped to ensure noise measurement, with the common mode and differential mode strictly separated. An appropriate known impedance is inserted at the EUT (equipment under test) terminals, and the noise source impedance is found from the variation of the noise level. This method was used to measure the conducted noise of a switching power sup-ply, and it was confirmed that the noise source impedance could be measured as a complex impedance independently for each mode. Thus, significant information for noiseremoval and propagation mode analysis was acquired.This paper presents a new method of measuring the noise source impedance of conducted emission using mode-separable LISN.2. Separate Measurement for Common Mode andDifferential ModeThe conventional single-phase LISN circuit for measurement of the noise terminal voltage is shown in Fig.1. The power supply is provided with high impedance by a 50-µH reactor, and a meter with an input impedance of 50Ω is connected between one line and the ground via a high-pass capacitor, and another line is terminated by 50 Ω. Thus, the LISN impedance as seen at the EUT is 100 Ω in the differential mode, and 25 Ω in the common mode. The measured value is the vector sum of both modes, and the noise must be found separately in order to find the noise source impedance for each mode. There is LISN with Y-to-delta switching to provide mode separation [8], but its impedance is 150 Ω, giving rise to a problem of data compatibility with 50-Ω LISN. Thus, a new mode-separa-ble LISN was developed as shown in Fig.2. The circuit is identical to that in Fig. 1 from the power supply through the high-pass capacitor. Switching of the connection pattern ensures measurement with one line of the balun transformer terminated by 50 Ω, and another line connected to the meter.In Fig. 2, the secondary side of the 2:1 balun trans-former is terminated by 50 Ω, while the primary side has 200 Ω; in the differential mode, the impedance (line-to-line) is 100 Ω since 200 Ω at the high-pass capacitor is connected in parallel. With the switch set at D, the meter is connected to the secondary side of the balun transformer. The voltage is one-half that of the line-to-line voltage, and measurement is performed in the standard way.The common mode current flows from both sides of the balun transformer via the middle tap to the 50-Ω termi-nal. The currents in the windings are antiphase, and no voltage is generated at the secondary side. Therefore, the impedance of the primary side is the terminal resistance of the tap. Since this impedance is connected in parallel to 50Ω (two 100 Ω in parallel) at the high-pass capacitor, the impedance between the common line and ground is 25 Ω. With the switch set at C, the meter is connected to the middle tap of the balun transformer, and the common-mode voltage is the line-to-ground voltage.3. Measurement of Noise Source Impedance3.1 Measurement circuit and calculationThough the propagation routes are different in the two modes, propagation from the noise source to the LISN can be represented in a simplified way as shown in Fig. 3. In the initial measurement, the load impedance Z L is the LISN impedance. Z L can be varied by inserting a knownimpedance at the EUT terminals. Consider three load im-Fig. 1. Standard 50-Ω/50-µH LISN.Fig. 2.Mode-separable LISN.Fig. 3. Schematic circuit of noise propagation.pedances, namely, LISN only and LISN with two different impedances inserted, Z L 1(R 1 + jX 1), Z L 2(R 2 + jX 2), andZ L 3(R 3+ jX 3). Using the values I 1, I 2, I 3 (scalars) measured in the three cases, Z 0(R 0 + jX 0) is found. Since V 0 = |Z L | × I ,the following expressions can be derived:From the above,Here a , b , and c are as follows:Substituting Eq. (2) into Eq. (1), the following quadratic equation for R 0 is obtained:Thus, R 0 and X 0 have two solutions each. The series of frequency points with positive R 0 is taken as the noise source impedance.3.2 Method of measurementAn impedance is inserted at the EUT terminals in order to measure the noise source impedance in the LISN as seen at the EUT. As shown in Fig. 4, the impedance is inserted so as to vary only the impedance in the mode under consideration, thus preventing an influence on the imped-ance in the other mode. In the diagram, V m is the voltage at the meter connected to the LISN, while the input impedance of the meter (50 Ω) is represented by the parallel resistance.Since parameters of both the LISN and the inserted imped-ance are known, the noise current I can be calculated from V m . Now Z 0 is calculated for each mode from the measured data obtained while varying Z L , by using Eqs. (2) and (3).With the differential mode shown in Fig. 4(a), CR is inserted between the two lines, thus varying the load im-pedance Z L . In the differential mode, Z 0 is assumed to be a low impedance, and hence the inserted impedance exerts a significant effect on the measured value. For this reason, 1Ω/0.47 µF and 0 Ω/0.1 µF were inserted, which are rather small compared to the LISN impedance.The measurement of the common mode shown in Fig.4(b) employs common-mode chokes that basically have no impedance in the differential mode. The common-mode chokes are provided with a secondary winding (ratio 1:1),so that the impedance at the secondary side can be varied.In the common mode, Z 0 is assumed to have a particularly high impedance in the low-frequency band. For this reason,5.1 k Ω and 100 pF were used as the secondary load for the common-mode choke to obtain a high inserted impedance.The measured data for the inserted impedance in the case of resistive and capacitive loads are presented in Fig. 5. The impedance of the common-mode choke includes its own inductance and the secondary load. In the case of a capaci-tive load, the resonance point is around 200 kHz; at higher frequencies, the impedance becomes capacitive.A single-phase two-line switching power supply (an ac adapter for a PC with an input of ac 100 V , a rated power of 45 W, and PWM switching at 73 kHz) was used as the EUT, and the rated load resistance was connected at the dcside. Filters were used for both the common and differential(1)modes, except for the case in which one common-mode choke was removed, in order to obtain the high noise level required for analysis. Both the EUT and the loads had conventional commercial ratings, and were placed 40 cm above a metal ground plate; the power cord was fixed.4. Measurement Results and Discussion The results of conventional measurement as well as common-mode and differential-mode measurement for the LISN without inserted impedance are shown in Fig. 6. The measurements were performed in the range of 150 kHz through 30 MHz, divided into three bands, using a spectrum analyzer with frequency linear sweep. Time-variable data were measured at their highest levels using the Max Hold function of the spectrum analyzer, and only the peak values were employed for calculation of Z 0. For this purpose, the values measured in every frequency band were subjected to the FFT, and all harmonics higher than the fundamental frequency were removed. The data were smoothed, and about 10 peak points were detected in every frequency band. In addition, only those peaks that were stronger than the meter s background noise by at least 6 dB were consid-ered.The results in Figs. 6(b) and 6(c) pertain to the LISN only; the level would vary with inserted impedance. The noise source impedance for both modes calculated from the measured data (using triple measurement) is given in Figs.7 and 9, respectively. The bold and dashed lines pertain to data acquired with the impedance analyzer at the EUT power plug, with the EUT not in operation. With the differ-ential mode, there were no high-frequency components, as shown in Fig. 6(b), and hence the impedance is calculated only for significant low-frequency peaks.The noise source impedance in differential mode can be represented schematically as in Fig. 8. The noise sourceimpedance is equal to the impedance between the LISNFig. 5.Inserted impedance in common mode.Fig. 6. Measured results of standard, differential-mode,and common-mode.Fig. 7. Noise source impedance for differential mode.terminals when the noise source is short-circuited. With switching power supplies, filtering is usually performed by a capacitor of 0.1 to 1 µF inserted between the lines. Since the impedance of the power cord is small in the measured frequency range, one may assume that the impedance as seen at the LISN is low, and that the phase changes from capacitive toward inductive as with the measured static characteristics. However, in the case of the given EUT, a nonlinear resistor was inserted between the power cord and the filter as shown in Fig. 8, and hence the impedance is rather high in the nonoperating state. In addition, there are rectifying diodes on the propagation route, but they do not conduct at the measurement voltage of the impedance ana-lyzer. The noise levels show considerable variation at 120Hz, which corresponds to the on/off frequency of the recti-fying diodes; however, only the peak values are measured and then used for calculation, and hence the impedance obtained by the proposed method is considered to pertain to the conductive state. For this reason, the results do not agree well with static characteristics. Thus, the impedance in the operating state cannot be measured in the differential mode.On the other hand, the measured data for |Z 0| in common mode agree well with the static characteristics, as shown in Fig. 9. The phase, too, exhibits a similar variation,although the scatter is rather large. The resistive part of three load impedances and Z 0 may be presented in a simplified way as in Fig. 10. From Eq. (1), the following is true for R 2,R 3, and Z 0:The distance ratio from Z 0 to R 3 and R 2 on the R X plane that satisfies this equation is I 2:I 3, which corresponds to a circle with radius r as in Eq. (4), with the center lying on the line R 3R 2:Similar circles for R 1 and R 2 are also shown in the diagram.When Z 0 and the load impedances lie on one line, the twocircles have a common point. Equation (4) indicates that if I 3 increases slightly, the outer circle becomes bigger, and the two circles do not adjoin. On the other hand, when the outer circle becomes smaller, the two circles intersect at two points, and X 0 varies more strongly than R 0. In practice, the difference in noise level due to the inserted impedance may drop below 1 dB at some frequencies, so that the solution for Z 0 becomes unavailable because of the scatter, or the phase scatters too much. The measurement accuracy is governed by the difference in noise level, and thus the inserted impedance should have a large enough variation compared to the measurement scatter; in addition, there should be a phase difference so that the two circles are not aligned, as in Fig. 10.Figures 7 and 9 pertain to one of the solutions of Eq.(3) with larger R 0. Here R 0 is not necessarily positive and the other solution is not necessarily negative. The two solutions may be basically discriminated from the fre-quency response and other characteristics, but other inser-tion data are employed for the sake of accuracy.Fig. 8. Equivalent circuit of differential-mode noisesource impedance.(4)Fig. 9.Noise source impedance for common mode.Fig. 10. Load impedances and Z 0 on R X plane.Figure 11 compares the measured data and calculated data for the variation of noise level due to insertion of a commercially available common-mode choke, with the cal-culation based on the results of Fig. 9 and the impedance of the common-mode choke. As is evident, the calculation agrees well with the measured values. On the other hand, a considerable discrepancy was confirmed for the other solu-tion. The noise source impedance found as explained above is accurate enough to predict the filtering effect.The noise source resistance in the common mode can be represented as in Fig. 12. Here Z 1 is the stray capacitance between the internal circuit and the case, and Z 2 is the stray capacitance between the case and the ground plate (or in the case of the ground wire, the impedance of the wire). The common-mode noise source impedance for a single-phase two-line EUT is primarily Z 2, becoming capacitive at low frequencies. Since the EUT is equipped with a filter, the influence of the primary rectifying diodes is not related to common-mode, and hence the data measured by the pro-posed method are very close to the static characteristics.However, this is not necessarily true in the case of a grounded line (Z 2 short-circuited) with no filter installed.In addition, here the full impedance as seen at the LISN is found; in practice, however, a filter or Z 1 is employed to suppress noise. Therefore, the impedance of the power cord is required as well as Z 1 and Z 2 in order to analyze the filtering effect. The impedance of the power cord or grounded wire can be easily determined by measurement or calculation. In our experiments without ground, the impedance is very close to Z 2; on the other hand, Z 1 might be measured by grounding the case and removing the filter (Fig. 12), and then used to analyze the filtering effect between the case and the lines. However, noise propagation in the inner circuit must be further investigated in order to estimate the noise-suppressing efficiency of Z 1.5. ConclusionsA new mode-separable LISN is proposed that sup-ports noise measurement without changing the impedance depending on the mode. The proposed LISN ensures accu-rate measurement for each mode, thus supporting imped-ance analysis.With the proposed LISN, an appropriate impedance is inserted at the EUT terminals, and the noise impedance can be found as a complex impedance, just as simply as with conventional measurement of the noise terminal voltage.The value of the inserted impedance must be chosen prop-erly in order to determine the phase accurately. The pro-posed method ensures sufficient accuracy not only to investigate noise propagation and design efficient counter-measures, but also to predict the filtering effect. The pro-posed technique can supply important data for future analysis of noise generation and propagation in switching power supplies.REFERENCES1.Matsuda H et al. Analysis of common-mode noise in switching power supplies. NEC Tech Rep 1998;51:60 65.2.Ogasawara S et al. Modeling and analysis of high-frequency leak currents generated by voltage-fed PWM inverter. Trans IEE Japan 1995;115-D:77 83.3.Iwasaki M, Ikeda T. Evaluation of noise filters for power supply. Tech Rep IEICE EMCJ 1999;90:1 6.4.Kamita M, Toyama K. A study on attenuation char-acteristics of power filters. Tech Rep IEICE EMCJ 1996;96:45 50.rmation technology equipment Radio distur-bance characteristics Limits and method of meas-urement. CISPR 22, 1997.Fig. 11. V ariation of noise level due to insertion ofanother impedance (measured and calculated data).Fig. 12. Equivalent circuit of common-mode noisesource impedance.6.K amita M, Oka N. Calculation of common-mode noise output impedance during operation. Tech Rep IEICE EMCJ 1998;98:59 65.7.Ran L, Clare C, Bradley K J, Chriistoopoulos C.Measurement of conducted electromagnetic emis-sions in PWM motor drive without the need for an LISN. IEEE Trans EMC 1999;41:50 55.8.Specification for radio disturbance and immunity measuring apparatus and method Part 1: Radio dis-turbance and immunity measuring apparatus. CISPR 16-1, 1993.AUTHORS (from left to right)Junichi Miyashita (member) graduated from Tohoku University in 1981 and joined the Precision Technology Research Institute of Nagano Prefecture. His research interests are EMC measurement and prevention. He is a member of IEICE.Masayuki Mitsuzawa (nonmember) graduated from Nagoya University in 1984 and joined the Precision Technology Research Institute of Nagano Prefecture. His research interests are EMC measurement and prevention. He is a member of JIEP .Toshiyuki Karube (nonmember) graduated from Waseda University in 1991 and joined the Precision Technology Research Institute of Nagano Prefecture. His research interests are EMC measurement and prevention. He is a member of IEICE and JIEP .Kiyohito Yamasawa (member) completed the M.E. program at Tohoku University in 1970. He has been a professor at Shinshu University since 1993. His research interests are magnetic device integration, microswitching power units, and microwave sensors. He holds a D.Eng. degree and is a member of IEICE, SICE, the Magnetics Society of Japan, the Japan AEM Society, and IEEE.Toshiro Sato (member) completed his doctorate at Chiba University in 1989 and joined Toshiba Research Institute. He has been an associate professor at Shinshu University since 1996. His research interests are magnetic thin-film devices. He received a 1994 IEE Japan Paper Award and a 1999 Japan Society of Applied Magnetism Paper Award. He holds a D.Sc. degree,and is a member of IEE Japan, IEICE, and the Magnetics Society of Japan.。
MicroPHYTM MII Evaluation Board DEMO BOARD MANUAL

78Q2123-DB78Q2133-DB78Q21x3-DB MicroPHY TMMII Evaluation BoardDEMO BOARD MANUALFebruary 2006DESCRIPTIONThe 78Q21x3-DB is a design example for a 10/100BASE-TX Mbit/second Fast Ethernet MII Interface adaptor. A 78Q2123 or 78Q2133 MicroPHY transceiver from Teridian provides the network physical interface and MII (Medium Independent Interface) interface.Teridian Semiconductor’s MicroPHY is an auto-sensing, auto-switching 10/100BASE-TX Fast Ethernet transceiver with full duplex operation capability. The device interfaces directly to the IEEE-802.3u MII port. Full-featured MII management functions are included along with an extended register set. The MicroPHY five bit PHY address is defaulted to 0x001. The MicroPHY interfaces to CAT5 UTP cable via a 1:1 transformer. The transceiver’s transmitter includes on-chip the pulse shaper and low power line driver. The receiver incorporates a sophisticated combination of real-time adaptive equalization, an adaptive DC offset adjustment circuit and baseline wander correction. Smart squelch circuitry further improves the receiver’s noise rejection. Full featured auto-negotiation or parallel detect modes are supported. The demo board requires operation with a +3.3V power supply.Design Kit contains:√ MicroPHY MII Demo Board √ Demo Board Parts List √ P.C.B. Gerber Files √ Demo Board schematic √ MicroPHY Data Sheet 10/100Base-TX InterfaceRJ45 Pin Assignment Pin Signal Pin Signal 1 TX+ 5 N/C 2 TX- 6 RX- 3 RX+ 7 N/C 4 N/C 8 N/CMII: Medium Independent InterfacePin Assignment: (40 Pin Male Subminiature D, 0.050) Pin Signal Pin Signal 1 +3.3V 21 +3.3V 2 MDIO 22 COMMON 3 MDC 23 COMMON 4 RXD3 24 COMMON 5 RXD2 25 COMMON 6 RXD1 26 COMMON 7 RXD0 27 COMMON 8 RXDV 28 COMMON 9 RXCLK 29 COMMON 10 RXER 30 COMMON 11 TXER 31 COMMON 12 TXCLK 32 COMMON 13 TXEN 33 COMMON 14 TXD0 34 COMMON 15 TXD1 35 COMMON 16 TXD2 36 COMMON 17 TXD3 37 COMMON 18 COL 38 COMMON 19 CRS 39 COMMON 20 +3.3V 40 +3.3VOrdering Number Description78Q21x3-DBMicroPHY MII Demo BoardMII ADAPTOR WITH MICROPHYUse With the Netcom Smart-BitsThe Netcom expects to be the master and defaults to 100BASE-TX Half-Duplex operation. Fast-Ether Windows may require the reconfiguration of the MicroPHY’s control register MR0 bits for similar operation. The MicroPHY defaults to auto-negotiate with full capabilities.After initialization the MicroPHY defaults to 100BASE-TX Full-Duplex operation. When connected to another fully capable transceiver the transceivers will be in full-duplex mode. The default configuration of the Netcom is 100BASE-TX Half-Duplex operation. If data transfers were to commence, the Netcom would display Collision errors (because it does not automatically read the transceivers and reconfigure).The default MII PHY address for the MicroPHY is 0x001. Additionally, the MicroPHY will respond to the broadcast address 0x000.If a transceiver is used which defaults to 100BASE-TX Half-Duplex operation, the MicroPHY will adjust itself for half-duplex operation (assuming the MicroPHY is setup for the proper technologies).To establish proper operation between the MicroPHY and the Netcom, click on the “Options” button followed by selecting “Full Duplex MII”. Repeat selecting “Full Duplex MII” twice to ensure that everything is configured identically.The MicroPHY can be configured for half-duplex operation to minimize incompatibilities with other transceivers and the Netcom.10/100Mbps Transformer SelectionThe line interface for the MicroPHY requires a pair of 1:1 isolation transformers. Integrated common-mode chokes are recommended for satisfying FCC radiated EMI requirements. Additional filtering is not required with the MicroPHY due to internal waveform shaping circuitry. The line transformer characteristics are outlined below:ConditionName ValueTurns Ratio 1 CT : 1 CT@ 10 mV, 10 kHzOpen-Circuit Inductance 350 µH (min)See Note 1.Leakage Inductance 0.40 µH (max) @ 1 MHz (min)Inter-Winding Capacitance 25 pF (max)D.C. Resistance 0.9 ohm (max)Insertion Loss 1.1 dB (typ) 0 - 100 MHzVrmsHIPOT 1500Note 1: The receive line transformer’s Open-Circuit Inductance can be as low as 100 µH for the MicroPHY. The MicroPHY incorporates baseline wander correction circuitry, which allows the receiver to track the incoming data signal when there is excessive transformer droop.For Commercial Temperature (0°C ~ 70°C)Teridian Semiconductor has performed line testing with the following transformers and found their performance acceptable with the MicroPHY:Manufacturer Part NumberTDKTLA-6T103Bel-Fuse S558-5999-46TG22-3506NDHaloPE-68515PulseST6118Valor20PMT04YCLThe following transformers are low profile packages (0.100 in/2.5 mm or less).TLA-6T118TDKTG110-S050HaloEPF8023GPCAThe following devices integrate the transformers with the RJ45 connector.TDKTLA-6T704RJS-1A08T089ADeltaThe following devices integrate the transformers, RJ45 connector, LEDs and termination resistors.J0011D21B/EPulseThe above evaluations were performed using Netcom’s Smart-Bits Fast Ethernet Analyzer. The Teridian Semiconductor MicroPHY MII Adapter and Lancast Fast Ethernet Adapter were attached to the Netcom’s Ports A & B respectively. Twisted pair Category 5 General Cable P/N 459360 was used to connect the two transceivers. 100 Mbps performance was measured using cable lengths of both 12 inches and 115 meters. 10 Mbps performance was evaluated using 100 meters of Category 3 cable.The Netcom was configured to use the Baseline Wander Packet file. Packet length was 1500 bytes.All transformers listed above met or exceeded IEEE’s 802.3 Bit Error Rate requirements of 10-8.For Industrial Temperature (-40°C ~ +85°C)Now most of the transformer vendors also offer industrial temp transformer, which will work with the 78Q2133. Here is the recommended industrial temp transformer list:Manufacturer Part NumberBelfuse S558-5999-U5HX1148PulseTG110-E050N5HaloPCB Layout ConsiderationsThe following recommendations enhance the MicroPHY’s performance while minimizing EMC emissions:1. The transformer to transceiver signal traces must be 100Ω differential transmission lines.2. Place the termination network components near the input data pins of the transceiver or transformer.3. Make all differential signal pairs short and of the same length.4. Decouple the transceiver thoroughly with 0.01µF and 0.1µF capacitors.5. Locate these decoupling capacitors as close as possible to the respective transceiver VCC and GNDpins.6. All decoupling capacitor and transceiver VCC and GND connections should tie immediately to a VCC orGND plane via with minimum trace inductance.7. Total decoupling capacitance should be greater than the load capacitance that the digital output driversmust drive.8. Use low inductance, ceramic surface mount decoupling capacitors.9. Use a multi-layer PCB with the inner layers dedicated to GND and VCC.10. A single VCC and GND plane is recommended for optimum performance. The lowest possible seriesimpedance is required between the analog and digital VCC and GND pins respectively of the transceiver.11. The outer layers of a 4 layer PCB are to be used for signal routing.12. Place the highest speed signals on the layer adjacent to the GND plane.13. Physically separate the analog signals from the digital signals by placing them on opposite layers orrouting them away from each other.14. Additional component and solder side ground layers may be added for maximum EMC containment.15. The GND plane should extend out to the transceiver side of the transformer. Remove the VCC and GNDplanes from the line side of the transformer to the RJ-45 connector.16. Do not allow the chassis ground plane to cross over the transceiver GND plane. Minimum separationmust accommodate over 1.5kV.17. Provide onboard termination of the unused signal pairs in the CAT-5 cable.18. Use a shielded RJ-45 connector with its case stakes soldered to the chassis ground.19. Locate the transformer adjacent to the RJ-45 to minimize the shunt capacitance to the line.20. Minimize RF current fringing by making the VCC plane 0.10 inch smaller than the GND plane. If multipletransceivers are used, provide partitions in the VCC and GND planes between the analog sections.Maintain the partition from the transformer up to the transceiver’s analog interface. Do not cross thesepartitions with signal traces, in particular any digital signals from adjacent transceivers.21. Add series resistors on all transceiver MII outputs to minimize digital output driver peak currents.22. Minimize the use of vias when routing the analog signal traces.23. Isolate the crystal and its capacitors from the analog signals with a guard ring.24. The crystal compensation capacitor value (C2 & C3) must be selected to trim the oscillator’s frequency to25.0000 MHz ±50ppm. The optimum value will be layout dependent. A mere ±4pF can shift the 25MHz±100Hz. The 25.0000 MHz ±50ppm is specified by the IEEE.Note: System vendors need to select the proper crystal according to their applications, such as operating environment, product lifetime, and etc since crystal aging, operating temperature, and other factors can affect the crystal frequency tolerance.MicroPHY MII Demo Board Parts ListQ T Y R EF ER E N C E N U M B E R D E S C R I P T I O N PA R T N U M B E R PA C KA G E MA N U FA C T U R E R1 U1 IC, 10/100Mbps LANTransceiverTSC 78Q2123 QFN32 TSC1 J2 RJ45, XFRM, LED,10BaseT/100BaseTX J0011D21Bwith LEDsPULSETLA-6T704without LEDsTDK1 Q1 CRYSTAL, 25.000MHZ ECCM1-25.000MHZ ECCM1 ECLIPTEK2 D1,D2 LED, Optional LU20125 R/A LUMEX7 R5,R6,R7,R8,R11,R12,R13,R14,R23,R25RES, 100 CC06032 R1,R2 RES, 680, Optional CC06033 R3,R4,R26 RES, 5.1K CC06031 R27 RES, 10K CC06034 R9,R10,R21,R22 RES, 49.9, 1% CC06034 C14,C15,C16,C17 CAP, CER, 10PF, Optional CC06032 C2,C3 CAP, CER, 27PF CC06033 C4,C12,C13 CAP, CER, 0.01UF CC060310 C6,C7,C8,C10,C11 CAP, CER, 0.1UF C1608Y51H104Z CC0603 TDK1 C9 CAP, CER, 10UF CC08051 P1 CONN, MALE, 40 PIN FCN-238P040-G/F FUJITSU1 P.C.B.Top SilkscreenTop LayerVCC LayerGround LayerBottom LayerNo responsibility is assumed by Teridian Semiconductor Corporation for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Teridian Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders.Teridian Semiconductor Corporation, 6440 Oak Canyon, Irvine, CA 92618-5201TEL: (714) 508-8800, FAX: (714) 508-887778Q2123-DB78Q2133-DB。
信号完整性和电源完整性分析

An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element andFinite-Difference Time-Domain TechniquesWei-Da Guo,Guang-Hwa Shiue,Chien-Min Lin,Member,IEEE,and Ruey-Beei Wu,Senior Member,IEEEAbstract—This paper presents a numerical approach that com-bines thefinite-element time-domain(FETD)method and thefi-nite-difference time-domain(FDTD)method to model and ana-lyze the two-dimensional electromagnetic problem concerned in the simultaneous switching noise(SSN)induced by adjacent signal traces through the coupled-via parallel-plate structures.Applying FETD for the region having the source excitation inside and FDTD for the remaining regions preserves the advantages of both FETD flexibility and FDTD efficiency.By further including the transmis-sion-line simulation,the signal integrity and power integrity is-sues can be resolved at the same time.Furthermore,the numer-ical results demonstrate which kind of signal allocation between the planes can achieve the best noise cancellation.Finally,a com-parison with the measurement data validates the proposed hybrid techniques.Index Terms—Differential signaling,finite-element andfinite-difference time-domain(FETD/FDTD)methods,power integrity (PI),signal integrity(SI),simultaneous switching noise(SSN), transient analysis.I.I NTRODUCTIONI N RECENT years,considerable attention has been devotedto time-domain numerical techniques to analyze the tran-sient responses of electromagnetic problems.Thefinite-differ-ence time-domain(FDTD)method proposed by Yee in1966 [1]has become the most well-known technique because it pro-vides a lot of attractive advantages:direct and explicit time-marching scheme,high numerical accuracy with a second-order discretization error,stability condition,easy programming,and minimum computational complexity[2].However,it is often in-efficient and/or inaccurate to use only the FDTD method to dealManuscript received March3,2006;revised November6,2006.This work was supported in part by the National Science Council,Republic of China,under Grant NSC91-2213-E-002-109,by the Ministry of Education under Grant93B-40053,and by Taiwan Semiconductor Manufacturing Company under Grant 93-FS-B072.W.-D.Guo,G.-H.Shiue,and R.-B.Wu are with the Department of Electrical Engineering and Graduate Institute of Communication Engi-neering,National Taiwan University,10617Taipei,Taiwan,R.O.C.(e-mail: f92942062@.tw;d9*******@.tw;rbwu@.tw).C.-M.Lin is with the Packaging Core Competence Department,Advanced Assembly Division,Taiwan Semiconductor Manufacturing Company,Ltd., 30077Taiwan,R.O.C.(e-mail:chienmin_lin@).Color versions of one or more of thefigures in this paper are available online at .Digital Object Identifier10.1109/TADVP.2007.901595with some specific structures.Hybrid techniques,which com-bine the desirable features of the FDTD and other numerical schemes,are therefore being developed to improve the simula-tion capability in solving many realistic problems.First,the FDTD(2,4)method with a second-order accuracy in time and a fourth-order accuracy in space was incorporated to tackle the subgridding scheme[3]and a modified form was employed to characterize the electrically large structures with extremely low-phase error[4].Second,the integration with the time-domain method of moments was performed to analyze the complex geometries comprising the arbitrary thin-wire and inhomogeneous dielectric structures[5],[6].Third,theflexible finite-element time-domain(FETD)method was introduced locally for the simulation of structures with curved surfaces [6]–[8].With the advent of high-speed digital era,the simultaneous switching noise(SSN)on the dc power bus in the multilayer printed circuit boards(PCBs)causes paramount concern in the signal integrity and power integrity(SI/PI)along with the electromagnetic interference(EMI).One potential excitation mechanism of this high-frequency noise is from the signal traces which change layers through the via transition[9]–[11]. In the past,the transmission-line theory and the two-dimen-sional(2-D)FDTD method were combined successfully to deal with the parallel-plate structures having single-ended via transition[12],[13].Recently,the differential signaling has become a common wiring approach for high-speed digital system designs in benefit of the higher noise immunity and EMI reduction.Nevertheless,for the real layout constraints,the common-mode currents may be generated from various imbal-ances in the circuits,such as the driver-phase skew,termination diversity,signal-path asymmetries,etc.Both the differential-and common-mode currents can influence the dc power bus, resulting in the SSN propagating within the planes.While applying the traditional method to manage this case,it will need a muchfiner FDTD mesh to accurately distinguish the close signals transitioning through the planes.Such action not only causes the unnecessary waste of computer memory but also takes more simulation time.In order to improve the computa-tional efficiency,this paper incorporates the FETD method to the small region with two or more signal transitions inside,while the other regions still remain with the coarser FDTD grids.While the telegrapher’s equations of coupled transmission lines are further introduced to the hybrid FETD/FDTD techniques,the1521-3323/$25.00©2007IEEEFig.1.A typical four-layer differential-via structure.SI/PI co-analysis for differential traces through the planes can be accomplished as demonstrated in Section II and the numerical results are shown in Section III.For a group of signal vias,the proposed techniques can also tell which kind of signal alloca-tion to achieve the best performance as presented in Section III. Section IV thus correlates the measurement results and their comparisons,followed by brief conclusions in Section V.II.S IMULATION M ETHODOLOGYA typical differential-via structure in a four-layer board is il-lustrated in Fig.1.Along the signal-flow path,the whole struc-ture is divided into three parts:the coupled traces,the cou-pled-via discontinuities,and the parallel plates.This section will present how the hybrid techniques integrate the three parts to proceed with the SI/PI co-simulation.At last,the stability consideration and computational complexity of the hybrid tech-niques are discussed as well.A.Circuit SolverWith reference to Fig.2,if the even/odd mode propagation coefficients and characteristic impedances are given,it is recog-nized that the coupled traces can be modeled by theequivalentladder circuits,and the lossy effects can be well approxi-mated with the average values ofindividualand overthe frequency range of interest.The transient signal propagationis thus characterized by the telegrapher’s equations with the cen-tral-difference discretization both in time and space domains.The approach to predict the signal propagation through the cou-pled-via discontinuities is similar to that through the coupledtraces except for the difference of model-extracting method.To characterize the coupled-via discontinuities as depicted inFig.1,the structure can be separated into three segments:the viabetween the two solid planes,and the via above(and under)theupper(and lower)plane.Since the time delay of signals througheach segment is much less than the rising edge of signal,the cou-pled-via structure can be transformed into a SPICE passive net-work sketched in Fig.3by full-wave simulation[14],whererepresents the voltage of SSN induced by thecurrent on Ls2.By linking the extracted circuit models of coupled-via disconti-nuities,both the top-and bottom-layer traces together with suit-able driving sources and load terminations,the transient wave-forms throughout the interconnects are then characterized andcan be used for the SIanalyses.Fig.2.The k th element of equivalent circuit model of coupled transmissionlines.Fig.3.Equivalent circuit model of coupled-via structures.B.Plane SolverAs for the parallel-plate structure,because the separationbetween two solid planes is much smaller than the equiva-lent wavelength of signals,the electromagneticfield inside issupposed to be uniform along the vertical direction.Thence,the2-D numerical technique can be applied to characterizethe SSN effects while the FETD method is set for the smallregion covering the signal transitions and the FDTD scheme isconstructed in the most regular regions.The FETD algorithm[15]starts from Maxwell’s two curl-equations and the vector equation is obtainedbyin(1)whereand denote the electricfield and current density,re-spectively,in the losslessvolume.Applying the weak-formformulation or the Galerkin’s procedure to(1)gives(2)where is the weighting function that can be arbitrarily de-fined.In use of thefinite-element method,the variational for-mula is thus discretized to implement the later numerical com-putation.In the present case,the linear basis function is chosento express thefields inside each triangular element.After takingthe volume integration over each element and assembling theFig.4.FEM mesh in the source region and its interface with the FDTD grids. integrals from all the elements,(2)can be simplified into a ma-trix formof(3)whereand are the coefficient vectors of electricfield andcurrent density,respectively.In addition,the values of all matrixelements in(3)are formulatedasand(4)For the mesh profile as illustrated in Fig.4,the FETD re-gion is chosen to be a block replacing the prime FDTD regioninto which the via transition penetrates.This is an initial valueproblem in time with thepreviousand being theinitial conditions as well as the boundary value problem in spacewith being Dirichlet boundary condition.To solve theinitial value problem in(3),the time derivative of electricfieldis approximated by the central difference,thatis(5)As for the electricfield in the second term of(3),it can be for-mulated by the Newmark–Beta scheme[16]to be readas(6)Fig.5.Simulationflowchart of hybrid FETD and FDTD techniques to performthe SI/PI co-analysis for the coupled-via structure as illustrated in Fig.1.Moreover,in the triangular elements with the via transitioninside,the term in(3)as expressedbygridarea(7)is needed to serve as the excitation of the parallel-plate structurewith thecurrent shown in Fig.3through the via structurebetween Layers2and3.It is worth noting that the via transitionshould be placed on the bary-center of each triangular elementto achieve better accuracy.The hand-over scheme for thefield in the overlapped region ofFDTD and FETD can be depicted in Fig.5.Given the boundaryfield calculated by the FDTD algorithm at the timestep,all thefield in the FETD region can be acquiredthrough the matrix solution of(3).The SSNvoltage in Fig.3is then determinedby(8)where is the averaging value of nodal electric-fieldsenclosing the via transition,and is the separation between theplanes.Onceand at the FETD mesh nodes(node1,2,3,and4in Fig.4)become available,together with the ob-tained voltage/current values from the circuit solver and electric/magneticfields of the FDTD region,the hybrid time-marchingscheme for the next time step can be implemented and so on.As a result of using the integrated schemes,thecurrent,arisen from the input signal through the via structure,can havethe ability to induce the voltage noise propagating within theFig.6.Physical dimensions of coupled traces and via pair.(a)Top view (Unit =mil ).(b)Side view.parallel plates.After a period of time,owing to the plane reso-nance and return path,the induced noise will cause the unwanted voltage fluctuation on the coupled traces by the presence of the finite SSNvoltage .C.Stability Problem and Computational Complexity It is not dif ficult to manifest that the FETD algorithm is un-conditionally stable.Substituting (5),(6),and (7)into (3)yields the following differenceequation:(9)where(10)the superscript “1”denotes the matrix inverse and thefactorgridareaWithout loss of generality,the time-stepping scheme in (9)is restatedas(11)Applyingthe -transform technique to (11)and solvingfor,de fined asthe -transformof ,the resultreads(12)along with thedependent ,de fined asthe -transformof in (11).Regardless of the timestep ,it can be easily de-duced that the poles of (12)is just on the unit circleof plane.This proves that the time marching by (9)is absolutely stable.The stability condition of these hybrid techniques is thus gov-erned by the transmission-line theory and the FDTD algorithm in the regular region,which are already known.Concerning the computational complexity,because of the consistence of simulation engines used for the circuitsolver,parison of differential-mode S -parameters from HFSS simulation and the equivalent circuit as depicted in Fig.3.the only work is to compare the ef ficiency of the hybrid FETD/FDTD technique with that of the traditional FDTD method.In use of only the FDTD scheme for cell discretization,the grid size should be chosen at most the spacing between the adjacent via transitions.However,as depicted in Fig.4,the hybrid techniques adopting the FEM mesh for the source region exhibit the great talent to segment the whole plane with the coarser FDTD grids.Owing to the sparsity of the FETD matrices in (4)and the much smaller number of unknowns,the computational time needed for each FETD operation can be negligible.The complexity of the hybrid techniques is therefore dominated by the FDTD divisions in the regular region.It is ev-ident that the total simulation time of the 2-D FDTD algorithmis,where denotes the number of the division in the whole space [7].The coarser the FDTD grids,the smaller the number of the grids and unknowns.Hence,the present hybrid techniques can preserve high accuracy without sacri ficing the computational ef ficiency.III.N UMERICAL R ESULTSA.Coupled via TransitionConsider the geometry in Fig.1but with the coupled-via structure being 2cm away from the center of parallel plates,which is set as the origin ofthe–plane.The size of the plane is1010cm and the separation between the two metal planes is 20mils(0.05cm).The physical dimensions of the coupled traces and via pair are depicted in Fig.6.After extractingthe -parameters from the full-wave simulation,their equivalent circuit models of coupled-via structures as sketched in Fig.3can be thus constructed.In Fig.7,it is found that the differen-tial-mode -parameters of equivalent circuit models are in good agreement with those from the HFSS simulations [14]and the extracted parasitic values of inductive and capacitive lumped-el-ements are also listed in the attached table.The top-layer coupled traces are driven by differential Gaussian pulses with the rise time of 100ps and voltage ampli-tude of 2V while the traces are terminated with the matchedFig.8.Simulated TDR waveforms on the positive-signaling trace.(a)Late-time response for the signal skew of 10ps excluding the multire flection phe-nomenon of common-mode signal.(b)Late-time response while no signal skew.TABLE IC OMPARISON OF C OMPUTATIONAL C OMPLEXITY B ETWEEN THE T WO M ETHODS(T IME D URATION =2:5ns)(CPU:Intel P43.0GHz,RAM:2GHz)loads at their ends.For simplicity,the transmission-line losses are not considered in the following analyses for the transient responses.By using the same mesh discretization as illustrated in Fig.4,the resultant segmentation for the plane con fines the flexible FEM mesh in the vicinity of via transitions and the coarser FDTD division with the size of22mm elsewhere.Employing the perfect magnetic conductors for boundary conditions of the parallel-plate structure,the simulated TDR waveforms with and without the signal skew on the posi-tive-signaling trace are presented in Fig.8.In comparison of hybrid FETD/FDTD techniques and finer FDTD method with center-to-center via spacing(0.66mm)as the grid size,the simulation results are in good agreement.Note that the voltage fluctuation before 900ps is induced by the incident signal passing through the coupled-via structure while the occurrence of late-time response is accompanied by the parallel-plate resonances.As for the signal skew of 10ps,the voltage level of late-time response is found to be greater than that of no signal skew because of the existence of common-mode currents produced by the timing skew of differential signals.Moreover,the simulation time of both methods should be pro-portional to the number of grids multiplied by the total time steps.As the physical time duration is fixed,the decrease of the FDTD division size would correspond to the increase of thetotalFig.9.Parallel plane with three current sources inside.(a)3-D view.(b)Zoom-in view of three sources on the plane in (a).(c).FETD/FDTD meshdiscretization.Fig.10.Simulated noise waveforms at the preallocated probe in reference to Fig.9(a).time steps.Consequently,as shown in Table I,it is demonstrated that the computational ef ficiency of the hybrid techniques is in-deed much better than that of the finer FDTD method.B.Multiple Source TransitionIn addition to a pair of differential-via structure,there can be a group of signaling vias distributed in the various regions of planes.Considering the parallel-plate structure in Fig.9(a),three current sources are distributed around the center (0,0)and a probe is located at (1mm,9mm)to detect the voltage noise induced on the planes.The FEM meshes for the source region and the interface with the FDTD region are shown inFig.11.Parallel-plate structure with two differential pairs of current sources inside in reference to Fig.9(a).(a)Two differential pairs of sources on the plane in Fig.9(a).(b)FETD/FDTD meshdiscretization.parison of the simulated noise waveforms between three cases of differential-sources on the plane as in Fig.9(a).Fig.9(c).The current sources are Gaussian pulses with the rise time of 100ps and different current amplitudes of 0.5,0.25,and 0.3A.With the same settings of boundary conditions,the simulated voltage noise waveforms at the preallocated probe re-ferred to Fig.9(a)are presented in Fig.10.It is indicated that the hybrid FETD/FDTD techniques still reserves the great accuracy in predicting the traveling-wave behavior of plane noise.In the modern digital systems,many high-speed devices employ the multiple differential-traces for the purpose of data transmission.These traces are usually close to each other and may simultaneously penetrate the multilayered planes through via transitions.Hence,it is imperious for engineers to know how to realize the best power integrity by suitably arranging the positions of differential vias.Reconsidering the parallel plates in Fig.9(a),instead,two dif-ferential-current sources around the center and the probe is re-located at (25mm,25mm)as shown in Fig.11along with their corresponding mesh pro file.After serving for the same Gaussian pulses as input signals,the simulated waveformsatFig.13.At time of 400ps,the overall electric-field patterns of three cases of differential-source settings in reference to Fig.12.(a)Case 1:one pair of dif-ferential sources.(b)Case 2:two pairs of differential sources with the same polarity.(c)Case 3:two anti-polarity pairs of differential sources.the probe are presented in Fig.12while three cases of source settings are pared with the noise waveform of one pair of differential sources,the signal allocations of mul-tiple differential-sources diversely in fluence the induced voltage noise.For the more detailed understanding,Fig.13displays the overall electric-field patterns at the time of 400ps for three casesFig.14.Speci fications and measurement settings of test board.(a)Top view.(b)Sideview.parisons between the simulated and measured waveforms at both the TDR end and the probe as in Fig.14.(a)The TDR waveforms.(b)The waveforms at the probe.of differential-source settings on the plane.Note that the out-ward-traveling electric field of Case 3(the differential-sources with antipolarity)is the smallest fluctuation since the appear-ance of two virtual grounds provided by the positive-and-nega-tive polarity alternates the signal allocation.IV .E XPERIMENTAL V ERIFICATIONIn order to verify the accuracy of hybrid techniques,a test board was fabricated and measured by TEK/CSA8000B time-domain re flectometer.The designed test board comprises the single-ended and differential-via structures,connecting with the corresponding top-and bottom-layer traces.The design speci fi-cations and measurement settings of test board are illustrated in Fig.14.To perform the time-domain simulation,the launching voltage sources are drawn out of re flectometer.As thedrivingFig.16.Frequency-domain magnitude of the probing waveforms corre-sponding to Fig.15(b)and the plane resonances.signals pass through the differential vias,the parallel-plate structure is excited,incurring the SSN within the ter,the quiet trace will suffer form this voltage noise through the single-ended via transition.After extracting the equivalent circuit models of coupled-via structures and well dividing the parallel plates,the SI/PI co-analysis for test board can be achieved.Simulation results are compared with the measure-ment data as shown in Fig.15accordingly.As observed in Fig.15(a),the differential signals have the in-ternal skew of about 30ps and the bulgy noise arising at about 500ps is due to the series-wound connector used in the measure-ment.The capacitive effect of via discontinuities is occurred at about 900ps,while the deviations between the simulation and measurement are attributed to the excessive high-frequency loss of input signals.For the zoom-in view of probing waveforms as in Fig.15(b),it is displayed that the comparison is still in good agreement except for the lossy effect not included in the time-domain simulation.Applying the fast Fourier transform,the frequency-domain magnitude of probing waveforms is ob-tained in Fig.16.In addition to the similar trend of time-domain simulation and measurement results,the peak frequencies cor-respond to the parallel-plate resonances of test board exactly.Hence,the exactitude of the proposed hybrid techniques can be veri fied.V .C ONCLUSIONA hybrid time-domain technique has been introduced and applied successfully to perform the SI/PI co-analysis for the differential-via transitions in the multilayer PCBs.The signalpropagation on the differential traces is characterized by the known telegrapher’s equations and the parallel-plate structure is discretized by the combined FETD/FDTD mesh schemes.The coarser FDTD segmentation for most of regular regions inter-faces with an unconditionally stable FETD mesh for the local region having the differential-via transitions inside.In use of hybrid techniques,the computational time and memory requirement are therefore far less than those of a traditional FDTD space with thefiner mesh resolution but preserve the same degrees of numerical accuracy throughout the simulation.In face of the assemblages of multiple signal transitions in the specific areas,the hybrid techniques still can be adopted by slightly modifying the mesh profiles in the local FETD re-gions.Furthermore,the numerical results demonstrate that the best signal allocation for PI consideration is positive-and-nega-tive alternate.Once the boundary conditions between the FETD and FDTD regions are well defined,it is expected that the hy-brid techniques have a great ability to deal with the more real-istic problems of high-speed interconnect designs concerned in the signal traces touted through the multilayer structures.R EFERENCES[1]K.S.Yee,“Numerical solution of initial boundary value problemsinvolving Maxwell’s equations in isotropic media,”IEEE Trans.Antennas Propag.,vol.AP-14,no.3,pp.302–307,May1966.[2]K.S.Kunz and R.J.Luebbers,The Finite Difference Time DomainMethod for Electromagnetics.Boca Raton,FL:CRC,1993,ch.2,3.[3]S.V.Georgakopoulos,R.A.Renaut,C.A.Balanis,and C.R.Birtcher,“A hybrid fourth-order FDTD utilizing a second-order FDTD subgrid,”IEEE Microw.Wireless Compon.Lett.,vol.11,no.11,pp.462–464,Nov.2001.[4]M.F.Hadi and M.Piket-May,“A modified FDTD(2,4)scheme formodeling electrically large structures with high-phase accuracy,”IEEETrans.Antennas Propag.,vol.45,no.2,pp.254–264,Feb.1997.[5]A.R.Bretones,R.Mittra,and R.G.Martin,“A hybrid technique com-bining the method of moments in the time domain and FDTD,”IEEEMicrow.Guided Wave Lett.,vol.8,no.8,pp.281–283,Aug.1998.[6]A.Monorchio,A.R.Bretones,R.Mittra,G.Manara,and R.G.Martin,“A hybrid time-domain technique that combines thefinite element,fi-nite difference and method of moment techniques to solve complexelectromagnetic problems,”IEEE Trans.Antennas Propag.,vol.52,no.10,pp.2666–2674,Oct.2004.[7]R.-B.Wu and T.Itoh,“Hybridfinite-difference time-domain modelingof curved surfaces using tetrahedral edge elements,”IEEE Trans.An-tennas Propag.,vol.45,no.8,pp.1302–1309,Aug.1997.[8]D.Koh,H.-B.Lee,and T.Itoh,“A hybrid full-wave analysis of via-hole grounds usingfinite-difference andfinite-element time-domainmethods,”IEEE Trans.Microw.Theory Tech.,vol.45,no.12,pt.2,pp.2217–2223,Dec.1997.[9]S.Chun,J.Choi,S.Dalmia,W.Kim,and M.Swaminathan,“Capturingvia effects in simultaneous switching noise simulation,”in Proc.IEEEpat.,Aug.2001,vol.2,pp.1221–1226.[10]J.-N.Hwang and T.-L.Wu,“Coupling of the ground bounce noise tothe signal trace with via transition in partitioned power bus of PCB,”in Proc.IEEE pat.,Aug.2002,vol.2,pp.733–736.[11]J.Park,H.Kim,J.S.Pak,Y.Jeong,S.Baek,J.Kim,J.J.Lee,andJ.J.Lee,“Noise coupling to signal trace and via from power/groundsimultaneous switching noise in high speed double data rates memorymodule,”in Proc.IEEE pat.,Aug.2004,vol.2,pp.592–597.[12]S.-M.Lin and R.-B.Wu,“Composite effects of reflections and groundbounce for signal vias in multi-layer environment,”in Proc.IEEE Mi-crowave Conf.APMC,Dec.2001,vol.3,pp.1127–1130.[13]“Simulation Package for Electrical Evaluation and Design(SpeedXP)”Sigrity Inc.,Santa Clara,CA[Online].Available:[14]“High Frequency Structure Simulator”ver.9.1,Ansoft Co.,Pittsburgh,PA[Online].Available:[15]J.Jin,The Finite Element Method in Electromagnetics.New York:Wiley,1993,ch.12.[16]N.M.Newmark,“A method of computation for structural dynamics,”J.Eng.Mech.Div.,ASCE,vol.85,pp.67–94,Jul.1959.Wei-Da Guo was born in Taoyuan,Taiwan,R.O.C.,on September25,1981.He received the B.S.degreein communication engineering from Chiao-TungUniversity,Hsinchu,Taiwan,R.O.C.,in2003,andis currently working toward the Ph.D.degree incommunication engineering at National TaiwanUniversity,Taipei,Taiwan,R.O.C.His research topics include computational electro-magnetics,SI/PI issues in the design of high-speeddigitalsystems.Guang-Hwa Shiue was born in Tainan,Taiwan,R.O.C.,in1969.He received the B.S.and M.S.de-grees in electrical engineering from National TaiwanUniversity of Science and Technology,Taipei,Taiwan,R.O.C.,in1995and1997,respectively,and the Ph.D.degree in communication engineeringfrom National Taiwan University,Taipei,in2006.He is a Teacher in the Electronics Depart-ment of Jin-Wen Institute of Technology,Taipei,Taiwan.His areas of interest include numericaltechniques in electromagnetics,microwave planar circuits,signal/power integrity(SI/PI)and electromagnetic interference (EMI)for high-speed digital systems,and electrical characterization ofsystem-in-package.Chien-Min Lin(M’92)received the B.S.degreein physics from National Tsing Hua University,Hsinchu,Taiwan,R.O.C.,the M.S.degree in elec-trical engineering from National Taiwan University,Taipei,Taiwan,R.O.C.,and the Ph.D.degree inelectrical engineering from the University of Wash-ington,Seattle.He was with IBM,where he worked on the xSeriesserver development and Intel,where he worked onadvanced platform design.In January2004,he joinedTaiwan Semiconductor Manufacturing Company, Ltd.,Taiwan,as a Technical Manager in packaging design and assembly vali-dation.He has been working on computational electromagnetics for the designs of microwave device and rough surface scattering,signal integrity analysis for high-speed interconnect,and electrical characterization ofsystem-in-package.Ruey-Beei Wu(M’91–SM’97)received the B.S.E.E.and Ph.D.degrees from National Taiwan Univer-sity,Taipei,Taiwan,R.O.C.,in1979and1985,respectively.In1982,he joined the faculty of the Departmentof Electrical Engineering,National Taiwan Univer-sity,where he is currently a Professor and the De-partment Chair.He is also with the Graduate Instituteof Communications Engineering established in1997.From March1986to February1987,he was a Vis-iting Scholar at the IBM East Fishkill Facility,NY. From August1994to July1995,he was with the Electrical Engineering Depart-ment,University of California at Los Angeles.He was also appointed Director of the National Center for High-Performance Computing(1998–2000)and has served as Director of Planning and Evaluation Division since November2002, both under the National Science Council.His areas of interest include computa-tional electromagnetics,microwave and millimeter-wave planar circuits,trans-mission line and waveguide discontinuities,and interconnection modeling for computer packaging.。
格伦艾尔圆形连接器术语和定义说明书

Essential Connector Terms and Definitions for Specifiers of Interconnect Wiring SystemsBack-Mounted: A connector design used in panel or box applications in which the mounting flange is located inside the equipment enclosure.Bayonet Coupling: A mating design utilizing pins on the receptacle and ramps on the plug for quick-connect and disconnect coupling. “Reverse” bayonet puts the pins on the plug and ramps on the receptacle.Circular Connector:Any of a thousand flavors of mulitpin interconnects with cylindrical contact housings and circular contact interface geometries. Circular connectors are selected for ease of engagement and disengagement, their ability to conveniently house different types of contacts, their wide range of allowable contact voltages and currents, their ease of environmental sealing and their rugged mechanical performance. In military and other high-rel applications, the MIL-C-5015 and D38999 are the most commonly specified types.Note: A disadvantage of the circular design is loss of panel space when used in arrays.Closed Entry: A contact cavity design in which the entry diameter of the socket insulator is smaller than the O.D. of the socket contact. Closed entry limits the size or position of the mating contact to a maximum dimension.Connector Body:The metal or plastic shell of a connector. Its main purpose is to house the contacts, maintain their position and shield them from dust, dirt, moisture, and electrical interference. Coaxial Contacts (and Cable):A contact with inner and outer conductive elements separated by a center dielectric element. Coaxial contacts terminate coaxial cable, and are employed in high bandwidth, high-frequency applications such as video and audio. The cable offers a closed, controlled impedance medium for the transmission of RF energy. It also provides high frequency performance and RFI shielding.Contact:The conductive element in a connector. Contacts mate mechanically and electrically to transmit signals and/or power across a connector interface. Crimp style contacts are the most common type found in high-reliability cylindrical connectors. Male contacts are sometimes referred to as leads, posts or pins. Female contacts are universally known as sockets. Contact Arrangement or Pattern:The gauge, number, spacing and arrangement of contacts in a connector. Contact arrangement selections are based on the current and voltage requirements of the application, and the space available for the connector package.Contact Engaging and Separating Force:T ensile force required to engage or separate mating contacts. Measured in ounces, the force increases with the number of contacts and with contact size. Contact (or Circuit) Identifier: Wiring schematics identify and label each and every circuit with numbers, letters or special codes. On the connector, this process is maintained by marking small numbers or letters next to each contact cavity on the connector.Contact Resistance:The measure of electrical resistance across a pair of fully mated contacts. Measured in ohms or millivolt drop at a specified current, contact resistance is affected by normal force (the static force on the contact interface), plating quality and the physical geometry of the contact.Contact Retainer:A locking clip or tang used to secure a crimp contact in place within the connector insert. Contact retention specifications define the force required to remove a properly seated contact for each class of connector.Contact Retention:The pressure a contact can withstand, in either direction, without being dislodged from the retaining clip which holds it within the connector.Contact Size:An assigned number denoting the outside diameter of the engaging end of the pin contact. The larger the number, the smaller the size. Contact Spacing:Also referred to as pitch, the distance, center-to-center, between adjacent contacts.Coupling Ring:An accessory feature of the connector plug which aids in mating and unmating plugs and receptacles and prevents decoupling of the connector. Self-locking coupling rings are used for high-vibration applications.Crimp: The physical compression (deformation) of a contact barrel around a conductor in order to make an electrical connection.Crimp Contact: A connector pin or socket, shipped loose with the connector body, and designed to be crimped onto the end of the wire conductor with a special tool. Often referred to as “crimp and poke” contacts, the terminated contact is poked into the connector body either by hand, or in the case of small gauge wires, with the aid of a hand-held tool. The ease of assembly and maintenance afforded by crimp contacts is preferred for aerospace and other high reliability applications not requiring a hermetic seal. Dielectric: A material having electrical insulating properties, such as the contact insulator in a connector or the jacketing on a wire.Electrical Connector: A separable device which provides mechanical and electrical contact between two elements of an electronic system without unacceptable signal distortion or power loss. Environmentally Sealed:Connectors and backshells designed to prevent fluids, moisture, air or dust from degrading the performance of electrical contacts and conductors. “Environmental” components typically use gaskets, grommets, potting materials or interfacial and O-ring seals to prevent the penetration of foreign substances into the body of the part.Filter Contact or Filter Connector: Contact design which provides EMI suppression in addition to its normal function of transmitting electrical energy. Filtered connectors are typically specified for high-speed signal paths. Filtering is accomplished through the integration of capacitors into the contact to separate high-frequency noise from low-frequency signals. Firewall Connector: A class of high-reliability, feed-through connectors designed to prevent fire or sparks from penetrating through a sealed bulkhead. Firewall connectors must continue to function for a specific period of time when exposed to fire, and are typically specified in military applications such as fighter jets and Navy ships.Flange:The integral mounting plate on some bulkhead and feed-through connectors used to attach the connector to the chassis or panel. The connector flange is typically square, and is mounted to the panel with threaded screws.Front Mounted: A connector design used in panel or box applications in which the mounting flange is located on the inside or outside of the equipment enclosure.Front Release: “Crimp and poke” style contacts may be removed from the connector for maintenance using a special hand-held tool. The proper insertion and removal tool must be used at all times. In front release designs, the tool is inserted into the mating face of the connector to disengage the contact from its retaining clip. The disengaged contact is then removed from the back (cable-side) of the connector by lightly pulling on the attached wire.Grommet:An elastomeric seal used on the back side of a connector to seal out fluids, moisture, air and dust.Grounding (or EMI) Fingers: A set of spring fingers in certain connectors, used to facilitate shell to shell grounding and enhance EMI performance. The grounding fingers engage before contact mating and remain engaged until after contact separation. Guide Pins:Metal posts) with a rounded or pointed tip which projects beyond the contact interface, used to assist in the correct alignment and mating of connector shells and contacts. The post mates with a corresponding cavity on the mating connector before contacts are allowed to engage. Guide pins are typically used in rack and panel packaging and in other “blind-mate” applications. Guide pins can also be used to insure correct polarization.Hermetic Connector:A class of connectors equipped with a pressure seal for use in maintaining pressurized application environments. The hermetic element of the connector is typically fabricated from vitreous glass.Insert: A molded piece of dielectric material that fits inside the connector shell and supports the connector contacts. Inserts are tooled for each shell size, and contact arrangement. Inserts made from resilient materials also contribute to environmental properties. Insulation Displacement:Forcing an insulated wire into a terminal slot smaller than the conductor diameter, displacing the insulation to make electrical contact.Interfacial Seal: An elastomeric seal providing overall sealing of the mated connectors and their individual contacts. “Cork & bottle” style seals feature a raised shoulder around each pin contact that compresses into a corresponding hole on the socket contact insulator. Key: A short pin (sometimes referred to as a “dog” by crusty old machinists) which slides into a corresponding slot or keyway to guide the plug and receptacle together during mating. The principal function of the key is to insure polarization of the mating contacts. Levels of Interconnection:A classification system for connectors defining connector types in terms of interconnect system function. The levels of most use include Level 4 (subassembly to subassembly), Level 5 (subassembly to I/O) and Level 6 (system to system). The lower levels (1, 2 and 3) all concern interconnection inside the microscopic world of printed circuit boards.Mating and Unmating Force: The force required to join and separate two halves of a connector. This is the sum of contact engaging forces plus any additional force necessary to overcome minor misalignment of connector halves and any dimensional variations in the connector shells.Normal Force:A measure of the spring pressure applied perpendicularly to contacts in mated connectors. The force of this spring pressure creates the gas-tight interface between contact surfaces which prevents corrosive contaminants from penetrating or forming between the contacts. High normal force reduces resistance across the contacts, but contributes to contact wear and may overstress the connector housing and even damage the spring properties of contact sockets. However, maintaining a constant normal force is an essential requirement for electrical integrity in the connector. Package Size: The length, width and height of the connector; or alternatively the dimensions of the entire interconnect system. Package size is an issue in many applications where system miniaturization, faster operating speeds, higher operating temperatures and other application requirements place new demands on the envelope of space the connector and its accessories may occupy.Plug: The half of a connector pair which is designed to attach to a wire or cable; as opposed to the receptacle half which is typically mounted to a bulkhead, panel or box. Even though we usually picture plugs as having male (pin) contacts, they can in fact house any type of contact—pins, sockets or even both. Thus it is the design and location of the connector which makes it a plug, not the gender of its contacts.Polarize:Design features on mating connectors—such as keyways or shell geometries—that insure connectors can be mated in only one possible orientation. The shape of a D-Sub connector shell, for example, assures that the two halves of the connector can be mated in only one way.Potting:The permanent sealing of the cable end of a connector with a compound or material to exclude moisture or to provide a strain relief. Glenair typically uses epoxy compounds for this purpose because of their dimensional stability and high-temperature resistance.Rear Release: “Crimp and poke” style contacts (see Crimp Contacts above) may be removed from the connector for maintenance using a special hand-held tool. The proper insertion and removal tool must be used to install and remove wires from such crimp and poke connectors. In rear release designs, the tool is inserted into the rear (cable side) of the connector to disengage the contact from its retaining clip. The disengaged contact is then removed from the connector by lightly pulling on the attached wire. Receptacle:The other half of the connector pair, designed to be mounted—with jam nut fittings or other fastener hardware—to a bulkhead, panel or box. In-line receptacles are also available for cable-to-cable connections. As with the plug, it is the design and location of the receptacle in the system, not the gender of its contacts, which makes it a receptacle.Rectangular Connector:Any of the thousands of multipin interconnects with rectangular shell housings and rectangular insert interface geometries. Rectangular connectors are typically mounted in rack and panel configurations in which large arrays of fixed receptacle connectors are mated with plugs attached to a movable rack for efficient utilization of space. D-Subminiatures are the world’s most common rectangular connectors.Scoop-proof: Scoop-proof connectors feature a nice, long shell on the receptacle which prevents damage to the exposed contact pins during mating. No matter how hard that swabbie tries, it is impossible to cock the mating plug so as to damage the pins or electrically short the contacts.Service Rating:Also called Current Rating, the maximum voltage or current load a connector is designed to carry during continuous, long-term use. Good engineering practice usually entails preliminary testing of connectors which will be operated with most or all contacts at the maximum rated load. Designers will often maximize contact and wire size in such situations.Solder Cup: A connector design that typically uses potting material to permanently affix the contacts inside the connector shell. Termination of contact to wire is then accomplished by soldering the wire into the cup-like barrel on the back of the contact. In the United Kingdom it is important to pronounce the “l” in solder. Brits also prefer to say “bucket” rather than “cup” when specifying solder contacts. Surface Mount: A termination method in which solder “tails” or leads on the connector are soldered directly to a printed circuit board. In high-reliability commercial and military applications, surface mount receptacle connectors are typically limited to rectangular designs such as D-Subminiatures and Micro-D’s. But some surface-mount applications do use a cylindrical connector mounted to the box with ribbon cable or flying leads soldered directly to the PCB. The reason here is to provide a low-resistance pathway to ground of the shielded cable. In severe EMI applications, it is less satisfactory to bring the shielded cable directly to the printed circuit board because of the difficulty in shielding out interference conducted along the cable.Termination:Termination is the physical act of attaching a wire conductor to a contact. Effective termination contributes to electrical performance and to the durability and reliability of the interconnect system. Common termination methods include crimp, insulation displacement, surface mount, and soldering. Termination can also refer to the mechanical attachment of EMI shielding to the connector backshell.Threaded Coupling: An interconnect mating design which utilizes a threaded nut on the plug, and a corresponding set of threads on the receptacle, to mate the pair of components. The coupling nut is usually equipped with flats or knurling for easy assembly. Different thread types, profiles and geometries provide different functionality. “Buttress” threads, for example, are often specified on plastic connectors due to their enhanced tensile strength. The MIL-C-38999 Series III connector incorporates a triple-start threaded coupling mechanism for greater vibration protection and faster mating and unmating.Wiping Effectiveness: Maintaining a clean, metallic path is essential if contacts are to perform with low and stable contact resistance. Surface films and contaminants are removed from the surface of plated contacts each time mating occurs. This displacement of surface contaminants during mating is called contact wiping. Wiping effectiveness depends on the contact geometry, engagement length and normal force. Interestingly, oxide film does not form on gold plated contacts, so wiping pressure can be lighter to displace only the occasional surface contaminant.Wire Pull-Out Force: This defines the force required to separate a wire from a contact. In properly terminated crimp contacts, the wire will generally break before it pulls away from the contact.。
multisim 共模扼流圈

multisim 共模扼流圈英文版Multisim Common-Mode ChokeIn the realm of electronics, Multisim stands as a powerful tool for simulating circuits and electronic systems. Among the various components that can be simulated in Multisim, the common-mode choke, or common-mode inductor, plays a crucial role in filtering and suppressing unwanted noise and interference.A common-mode choke is a type of inductor designed to block or reduce common-mode currents, which are currents that flow in the same direction in two conductors. These currents are often caused by electromagnetic interference (EMI) or electromagnetic compatibility (EMC) issues. By effectively blocking these currents, common-mode chokes improve the overall performance and reliability of electronic systems.In Multisim, simulating a common-mode choke allows engineers and hobbyists to analyze its impact on a circuit's behavior. By inserting a common-mode choke into a simulated circuit, it's possible to observe how it affects the flow of currents and how it mitigates EMI or EMC issues. This simulation capability is invaluable in the design and optimization of electronic systems.Moreover, Multisim's simulation of common-mode chokes enables users to experiment with different configurations and parameters, such as inductance values and circuit arrangements. This flexibility allows for a more comprehensive understanding of how common-mode chokes work and how they can be optimized for specific applications.In conclusion, Multisim's simulation of common-mode chokes is a powerful tool for electronic design and analysis. It enables users to gain valuable insights into the behavior of these components and how they can be effectively used to improve the performance and reliability of electronic systems.中文版Multisim共模扼流圈在电子领域,Multisim是一款强大的电路和电子系统仿真工具。
飞兆关于功率转换器的电磁兼容性设计指导

© 2004 Fairchild Semiconductor Corporation Fairchild Semiconductor Application NoteApril 2004Revised April 2004AN-4145 Electromagnetic Compatibility for Power ConvertersAN-4145Electromagnetic Compatibility for Power ConvertersElectromagnetic Compatibility (EMC) has become a household name of the past decade. In the mid 1990’s,Europe required a reduction on the level of radiated and conducted emission in products that were sold into the region. From that point on many products today have in their design cycle EMC testing.A common question asked is, what is EMC? EMC is the ability of a device, product, or system to operate properly in its intended electromagnetic environment (presence of EMI), without degradation and without being a source of interference. There are bodies that produce EMC stan-dards that must be followed such as IEC and CISPR.This application note speaks about EMC regulations deal-ing with both radiated and conducted emissions. Con-ducted emissions consist of both common mode and differential mode noise. In order to deal with common and differential mode noise, an AC power main filter is required and a description and example of one is provided. These noises can reside on the power lines entering the unit, but are also produced by internal switching devices.EMC RegulationsIn order to achieve a solid EMC design, one must under-stand the EMC requirements. The requirements that will follow do not deal with module power supplies; rather they deal with system level standards in both Europe and in North America.The International Electrotechnical Commission (IEC) is responsible for deriving the European requirements, in say-ing that, the Comite International Special des Perturbations Radioelectriques (CISPR) – International Special Commit-tee on Radio Interference is responsible for the EMC requirements with CISPR 22 defining the strictest limits on conducted emissions. These limits (conducted emissions)are described in the product standards EN 55022 (Figure 1) and EN 55011 (Figure 2). The class A and class B requirements on Figure 1 and Figure 2 refer to the indus-trial standard and the domestic standard respectively.Depending on the antenna used for detecting the noise,the European standards give two limits. The higher limit for a quasi-peak antenna and a lower limit for an average antenna, but both limits must be met for the equipment to pass the requirement. The FCC standards used in North America have similar specifications to the European EN requirements (see note below Figure 2). Two European standards that are used in testing power supplies are EN 55011 and EN 55022. Figure 3 and Figure 4 show the radiated levels of EN 55011 and the FCC part 15 subpart B (North America) respectively.In North America, radiated EMI is most often measured in the frequency range from 30 MHz to 10 GHz (according to the FCC), while conducted EMI is most often measured in the frequency range of several kHz to 30 MHz (according to the FCC).FIGURE 1. EN 55022 Conducted EmissionsFIGURE 2. EN55011/FCC Part 15 Subpart BConducted LevelsNote: After May 23, 2004 the FCC Part 15 Subpart B and the EN 55011 will have the same noise conduction level specification.FIGURE 3. EN 55011 Radiated Emissions at 3 meters 2A N -4145EMC Regulations (Continued)FIGURE 4. FCC Part 15 Subpart B Radiated Emissionsat 3 meters The goal here is to develop a system that can comply with some or all of the emissions presented above whether it is a stand alone device or incorporated into a larger system.Common Mode and Differential Mode NoiseThere are two major sources of noise, common mode and differential mode. Common mode noise (Figure 5) comes from common mode current. Common mode energy is common to both lines in a single phase system. This energy travels on all the lines, or wires, in the same direc-tion, and this energy is between all these wires and ground.Because the same level is on both wires at the same time,no attenuation is given by any device between the lines.FIGURE 5. Common Mode NoiseCommon mode noise from common mode current always exists on cables entering the device. One way to minimize these currents is to test the cables early on prototype mod-els (this gives the designer the ability to make any changes necessary before the design is finalized for production) and prior to performing EMC compliance testing. In a lot of cases if the device fails the common-mode current test, it will also fail the radiated emission test. The common mode current can be easily measured by using a high frequency clamp on current probe and a spectrum analyzer. A current probe with a response range of up to 250 MHz should be sufficient.Differential mode noise (Figure 6) is the opposite of com-mon mode noise. This noise is produced by current flowing along either the live or neutral conductor and returning by the other. This produces a noise voltage between the live and neutral conductors.FIGURE 6. Differential Mode NoiseAN-4145AC Power Line Main FilterFIGURE 7. Single Phase AC Line FilterAn example of a single phase AC line filter is shown in Fig-ure 7. Filters of this type are commonly used in reducing both differential and common mode noise from entering and leaving the power supply. The filter in Figure 7 has been broken up into different sections to help better describe its overall function.Note: Both Section A blocks and Section B blocks perform the same func-tion with the only difference being one is for noise entering the device where the other is used for noise exiting the device.BlocksSection AInductors L1/L2 and capacitor C1 represent a differential filter for any noise trying to enter the power supply. Differ-ential mode noise is produced by current flowing along either the line or neutral conductor and returning by the other. The combination of L1 and C1 or L2 and C1 repre-sent a voltage divider. Depending on the frequency of the noise, the capacitor C1 represents a smaller impedance (larger load) to the signal thereby reducing any noise on the line. As an example if the impedance of L1 is 10K and the impedance of C1 is 1K at a particular frequency, the noise passing through the filter would be a tenth of its origi-nal strength or a reduction of 20dB.Section BCapacitors C2 and C3 represent a common mode filter with a reference to ground. Common mode noise manifests itself as a current in phase with the live and neutral conduc-tors and returns via the safety earth. This produces a noise voltage between live/neutral and earth. With all C2, C3, C4,and C5 all being equal, any common mode noise on these lines will be shunted to ground.Note: Section B is not used in medical equipment due to leakage current.Section CSection C of Figure 7 represents the Zorro Inductor (com-mon mode choke) without a reference. The direction of each winding is chosen to give an opposing current flow so any noise present will be cancelled. Magnetic flux caused by common mode current is accumulated, producing impedance, thereby reducing any noise on the line. Since differential mode has currents running in different direc-tions, magnetic flux caused by differential mode current cancels each other, and impedance is not produced thereby having no effect.Note: Capacitors C1 and C6 are X Class capacitors, used to reduce differ-ential noise and are tested to withstand mains voltage. X Class capacitors usually run in the 0.01uF to 2uF range. Capacitors C2 through C5 are Y Class capacitors for common mode noise and are tested to ensure thatthey cannot fail to short circuit (more expensive than X Class). Y Class capacitors are smaller in value usually running between 0.002uF to 0.1uF.AC Power LineFilter Design Example(AD/DC Flyback Converter)Design Requirements:•Transformer turns ratio (a) = 10•Output Impedance (Zs) = 10Ω (load impedance, worst case for maximum output power)•Noise reduction required at 20 kHz = 35dB•Additional headroom for unknown frequency spike = 6dB •AC Line Frequency (Fl) = 60Hz•PWM Switching Frequency (Fs) = 100 kHzTo determine the values of the filter, the output load imped-ance must be recognized. In order to recognize this imped-ance the output load (worst case) must be reflected back to the primary across the transformer using equation 1.whereOn the input side, the filter will be designed for 10 times the line frequency (keeping the filter transparent to both the line and load), thereby resulting in a frequency of 600Hz. In saying this, the cutoff frequency (Fo) must not be below 600Hz. With a noise reduction of 41dB (35dB plus the 6dB of headroom) at 20 kHz, the designer divides 20 kHz by 2and subtracts 12dB from 41dB (see Table 1). Initially a sin-gle inductor will be used to see if this can be accomplished;if not a second series inductor will be needed. A single inductor will give a drop off of 12dB/octave or 40dB/decade. As shown in Table 1, a single inductor is sufficient for this design with the cutoff frequency (Fo) being 1.25kHz (above the minimum 600Hz limit).Zp =Primary Impedance Zs =Secondary Impedancea =Transformer Turns Ratio (Np/Ns) 4A N -4145AC Power Line Filter Design Example (AD/DC Flyback Converter)(Continued)TABLE 1. Input Inductor Determination Now that the cutoff frequency (Fo) is known, the value of the inductor can be created using equation 2.whereUsing Equation 3, one can determine the differential capacitance (Cd) required to complete the differential mode circuit (Section A).whereFor a balanced filter (an inductor on both the live and neu-tral lines), the value is divided by 2, giving 64mH. With the inductance being so large, two inductors will be used to reduce its size. Also an advantage to having more induc-tors is not only to reduce the inductance, but the Q of the filter decreases, thereby decreasing the risk of oscillations.Table 2 represents a second inductor added to the filter giv-ing a 24dB/octave reduction.TABLE 2. Addition of a Second Inductor Using Equation 4 and 5 the subsequent new inductor and capacitor values can be computed.whereAgain, for a balanced filter (an inductor on both the live and neutral lines), the result is divided by 2, giving 16mH.whereThe common mode Zorro inductor is the remaining device to be calculated. The Zorro inductor is calculated the same way in which inductor (L) was, but instead of starting off using the cutoff frequency (Fo), one uses the PWM switch-ing frequency (Fs) (see Table 3) and the same dB loss.Since two differential mode inductors are required, two Zorro inductors will be used to complete the filter.TABLE 3. Zorro Inductor Calculations Frequency (kHz)dB(Limit of Conducted Emissions)2041 (35dB plus 6 dB of headroom)10295172.551.25 (Fo)−7L =Differential InductorZp =Primary Impedance(reflected back from the secondary)Fo =Cutoff Frequency from Table 1L =Differential InductorZp =Primary Impedance(reflected back from the secondary)Frequency (kHz)dB(Limit of Conducted Emissions)2041 (35dB plus 6 dB of headroom)10175 (Fnew)−7Lnew =New Differential InductorZp =Primary Impedance(reflected back from the secondary)Fnew =Cutoff Frequency from Table 2Lnew =New Differential InductorZp =Primary Impedance(reflected back from the secondary)Frequency (kHz)dB(Limit of Conducted Emissions)10041 (35dB plus 6 dB of headroom)501725 (Foz)−7AN-4145AC Power Line Filter Design Example (AD/DC Flyback Converter)(Continued)Using Equations 6 and 7, the Zorro inductance (Lzorro)and Zorro capacitance (Czorro) can be found.wherewhereThe final design is shown in Figure 8.If there are problems at the high frequencies, ferrite beads can be added (ferrite beads act as resistors (50 to 200Ω) at low frequencies and inductors at high ones (30MHz)). If dif-ferential problems occur, increase the Lnew inductors some, or improve the quality of the Cdnew capacitance,they may have too much leakage at the frequency in ques-tion. Common mode problems can be combated by increasing Lzorro inductors.FIGURE 8. Final Filter DesignDesign Guide to Reduce Internal andExternal In Power ConvertersThere are three areas of noise generation in an AC to DC power supply:1.Any noise already present on the AC mains enteringthe power supply unit (common mode/differential mode)2.The switching frequency of the power supply (commonmode)3.The fast switching edges and ringing produced whenthe MOSFET is turned off (common mode)1) AC MainsWith noisy power main lines, an AC power line filter is used. When using an AC power line filter make sure that it is mounted as close as possible to where the AC power line enters the printed circuit board (PCB), see Figure 9.Also the ground connection to the filter should be as short as possible with many vias to the ground plane of the pri-mary side of the power supply.FIGURE 9. Grounding the Common Mode Capacitorsto the Ground Plane In order to reduce common mode and differential mode noise from leaving and entering the unit, an AC power line filter needs to be used. See section on AC Power Line Main Filter.Lzorro =Common Mode InductorZp =Primary Impedance(reflected back from the secondary)Foz =Cutoff Frequency from Table 3Lzorro =Common Mode InductorZp =Primary Impedance(reflected back from the secondary) 6A N -4145Design Guide to Reduce Internal and External In Power Converters(Contin-2) Switching Frequency of the Power SupplyJust like in a system that uses a system clock, many power supplies have a pulse width modulator (PWM) device that operates at a frequency that is used to control the output voltage. So where a system clock needs to be carefully laid out on a PCB, so does the PWM controller.In a flyback, forward or other topology design using a trans-former, it is important to make the trace from the primary winding to the drain of the switching MOSFET (either inter-nal or external) as wide and short as possible (see Figure 10). This reduces the inductance path thereby keeping the ringing to a minimum. A solid ground plane with a minimal number of holes is preferred to ground both the MOSFET and PWM controller too. There should always be a ground running parallel to the trace for current return (if stray capacitance is not a problem), if there still is a noise issue,one can minimize the drain trace capacitance to the trans-former by removing the ground plane from under the trace shown in Figure 10. There are already parasitic capacitors within the MOSFET switch structure that pump current to and from ground. If the ground plane is not removed below the “cross hatched ” trace, then additional current will be passed into the ground causing more common mode con-ducted noise.FIGURE 10. Reducing Drain Trace CapacitanceNote: Especially at higher frequencies, example 500kHzThe source of the MOSFET doing the switching must have a solid connection to the primary side ground plane. In order to accomplish this make a large landing pad for the ground terminal so that a proper number of vias (depend-ing on the sinking current) can be used to make a solid connection to the ground plane, see Figure 11.FIGURE 11. Connecting the Source of an Internal MOSFET to the Ground Planewith a Sufficient Number of Vias 3) PWM Switching Edges and Subsequent Ringing Figure 12 shows a Resistor Capacitor Diode (RCD) cir-cuitry (R1, C1, and D1) that serves two purposes; firstly C1shows down the collector voltage rise time (smoothening,reducing radiated EMI) when Q1 is turned off and secondly,it maintains the input voltage to 2V CC as not to exceed the breakdown voltage of the switching MOSFET. In making C1 large enough, the rising collector voltage and falling col-lector current intersect so low down that the transistor dissi-pation is decreased significantly.The ringing circuitry (Figure 12 (C2 and R2)) is also impor-tant and used to reduce the ringing of the primary side of the transformer caused when the MOSFET relaxes to the input voltage of the power supply, shown below in Figure 13 and Figure 14.FIGURE 12. RCD Snubber and RC Ringing CircuitryAN-4145Design Guide to Reduce Internal and External In Power Converters (Contin-FIGURE 13. Primary Voltage Waveform Without Ringing Circuitry (C2, R2)FIGURE 14. Primary Voltage Waveform with Ringing Circuitry (C2, R2)As a first pass, one method of determining the values for C2 and R2 is as follows:1.Determine the frequency of the ringing waveform andcalculate the period.2.Multiply the period, determined in Step 1, by 5.3.Assume a value for the resistor (usually less than100R).4.Calculate the size of the capacitor by dividing the num-ber obtained in Step 2 by the size of the resistor inStep 3.Note: The advantage of using the resistor R2 and the capacitor C2 network is that it reduces the ringing as shown in Figure 11, but the disadvantage is that the high frequency ripple passing through capacitor C2 gets dissipated as heat in resistor R2. If noise reduction is more important than efficiency then proceed, otherwise efficiency will drop off some.8A N -4145 E l e c t r o m a g n e t i c C o m p a t i b i l i t y f o r P o w e r C o n v e r t e r sPrinted Circuit Board Guidelines1.Take the time to place and orient the components prop-erly.2.If heat sinks are used, make sure they are grounded.3. A component shield maybe required.mon mode capacitors should have low ESR val-ues as well as maintain a short lead length to the ground place.5.If a snubber circuit is being used across the trans-former to slow down the rise time of the MOSFET switch turning off, make sure that the trace lengths from the drain and two primary transformer pins are short. If possible place the snubber circuitry between the two primary pins.6.avoid slots in the ground and power (if used) planes7.Under 50 MHz (don ’t forget to consider the harmonicsof the PWM controller) traditional decoupling methods are effective. Use one or two decoupling capacitors (often 0.1 or 0.01 uF) placed close to the IC power and ground pins. Consider the loop area formed between the decoupling capacitor and the IC, and place the capacitor for minimum loop area.8.Keep ground runs as short as possible and as thickand large as possible.9.Avoid sharp corners on traces.10.Try to group all noisy component in the same area justin case shielding is e multi-layer printed circuit board if possible.Safety Dealing with Medical EquipmentCommon mode noise is a problem for sensitive equipment such as those in the medical field. If a device touches a patient, the total system leakage is limited to 100uA. This means that most power supply designers want to restrict this leakage current 20 to 40uA. In order to meet this strin-gent requirement, common mode filters with capacitors to ground are not used. Using common mode chokes, feed through capacitors (high frequency noise is shunted to the chassis ground instead of signal ground) to ground and adding a transformer or isolating the power supply lines into the power supply reduces these common mode con-ducted emission pulses. Safety standard: IEC950/UL1950class II is used in medical equipment.ConclusionEMC is an important stage of system design today and will become more stringent as time moves on. One must keep in mind that when switching occurs, so does noise whether it be conducted or radiated noise. This application note spoke about board level techniques to reduce noise, if more noise reduction is required, especially on the radia-tion side, conductive enclosures are an option. There is additional cost with all that is added so as a design engi-neer, standard compliance, safety compliance, and cost all play an important role in the final product.References:EMI Filter Design (1996)Richard Lee OzenbaughFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
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Power Tip 40: Common-mode currents and EMI in non-isolated power suppliesRobert Kollman, Texas Instruments10/14/2011 3:21 PM EDT(Editor's note: to see a linked list of entries #1 to #37 in the Power Tips series, click here; to see a linked list of all entries from #1 to the latest one, click here.)(Additional editor's note: if you are interested in EMC or EMI/RFI, be sure to check out our EMC Basics series, here.) Have you dismissed common-mode currents in a non-isolated power supply as a potential electromagnetic interference (EMI) source?In high-voltage supplies, such as one you might find in an LED light bulb, you may find that you can’t. On inspection, it really is no different than an isolated supply. There will be stray capacitance to ground from switching nodes that will generate common-mode currents. Figure 1 is a schematic of a LED power supply showing the parasitic capacitance that is the main cause of common-mode current in this buck regulator. It is the capacitance to earth from the switch node. It is surprising how small this capacitance can be and still create a problem.Figure 1: Even just 100 fF of capacitance from the switch nodecan create an EMI issue(click here to see enlarged image).The CISPR Class B (for residential equipment) conducted emissions limit allows a 46 dBµV (200µV) signal into a 50Ω source impedance at 1 MHz. This translates into only 4 µA of allowable current. If the converter switches with a 200 V pk-pk square wave on the drain of Q2 at 100 kHz, the fundamental will be around 120 volts peak. Since the harmonics decrease in proportion to frequency, there will be about 9 V rms at 1 MHz.That can be used to calculate an allowable capacitance to ground of around 0.1pF, or 100 fF (or a 2-MΩ impedance at 1 MHz) which is an entirely feasible amount of capacitance from this node. There is also capacitance from the remainder of the circuitry to earth that provides a path for the common-mode currents to return. (This is notated as C_Stray2 in Figure 1.)In an LED light application, there is no chassis connection: only hot and neutral are available, so common-mode EMI filtering is a problem. That is because the circuit is high impedance. It can be represented by a 9 V rms voltage source in series with a 2 MΩ capacitive reactance as shown in Figure 2, and there is no realistic way to add impedance to reduce the current.Figure 2: Even 100 fF can cause you to exceed EMI limits(click here to see enlarged image).To reduce the emissions at 1 MHz, you need to reduce the voltage or reduce the stray capacitance. Two ways to reduce the voltage is with dithering or rise time control. Dithering varies the operating frequency of a power supply to spread out the spectrum.For a discussion on dithering, look at Power Tip 8 (February 2009). Rise-time control slows the switching speed in the power supply, to limit the high-frequency spectrum and is better suited for EMI problems above 10 MHz. Reducing the stray capacitance from the switching node can be as simple as minimizing the etch area or it may involve shielding. Capacitance from this node to one of the rectified supply lines does not create common-mode current, so you can bury the trace in a multilayer printed wiring board (PWB) and reduce much of the unwanted capacitance.However, you can not completely eliminate it because there is still capacitance remaining from the drain of the FET and inductor. Figure 2 provides a graph and steps you through the calculation of the EMI spectrum.The first step is to calculate the spectrum of the voltage waveform (red). This is accomplished by calculating the Fourier series of the drain-voltage waveform, or more simply by calculating the fundamental component and approximating the envelope as one divided by the harmonic number and the fundamental.A further adjustment is made at high frequency [1/(π×rise time)], as shown above 7 MHz. The next step involves dividing this voltage by the reactance of the stray capacitance. Interestingly, the low-frequency emissions are flat with frequency until you cross the pole that is set by rise time.Finally, the CISPR Class B limits are also plotted. With only 0.1 pF of stray capacitance and a high-voltage input, emissions are close to the limits.EMI problems can also exist at higher frequencies due circuit resonances and radiated emissions caused by resonances of input cabling. Common-mode filtering can help these issues because there is a reasonable amount of capacitance in C_Stray2.For instance, if it were 20 pF, its impedance would be less than 2 kΩ at 5 MHz. Common-mode inductors of sufficient impedance can be added between the circuit and the 50 Ω test resistor to reduce measured emissions. This is also true at higher frequencies.To summarize, with high-voltage, non-isolated power supplies, common-mode currents can cause EMI emissions to exceed standard limits. In two-wire designs (no chassis connection), they are particularly difficult to handle because of the high impedances involved.The best way to approach this kind of challenge is to minimize the stray capacitance and to dither the switching frequency. At higher frequencies, where the impedance of the distributed capacitance from the remainder of the circuit becomes small, common-mode inductors can reduce both radiated and conducted emissions.Please join us next month when we will discuss power supplies for DDR memory.For more information about this and other power solutions, visit: /power-ca.。