再谈SDRAM的布线——有关Mentor WG、DxDesinger、Expedition、CES
SDRAM布线规则及技巧
SDRAM布线规则及技巧SDRAM（Synchronous Dynamic Random Access Memory）是一种同步动态随机存取存储器，广泛应用于计算机系统中。
SDRAM的性能受到布线的影响，因此在设计SDRAM布线时需要遵守一些规则和技巧，以保证其性能和稳定性。
首先，布线规则是确保时序要求满足的基础。
时序要求是指控制信号在SDRAM上正确传输和演变的时间约束。
布线规则的主要目标是减少时序延迟和时序失真，确保信号的准确到达。
一些常见的布线规则包括：1.长度匹配：确保信号线的长度尽量相等，可以通过差分对和匹配长度来实现。
2.延迟匹配：保证信号线的延迟尽量相等，可以通过使用等长路径和准确的电缆长度来实现。
3.信号间隔：确保信号线之间的间隔足够，避免相互干扰。
4.层间切换：尽量减少信号线在不同层之间的切换，减少反射和串扰。
其次，布线技巧可以帮助优化布线效果和避免一些常见的布线问题。
1.差分对布线：差分对布线是一种常见的布线技巧，用于减少信号线之间的串扰和提高抗干扰能力。
差分对布线需要保持差分对的长度和延迟匹配。
2.绕行规则：在布线时需要避免绕行，尽量使用直线布线路径，减少信号线的长度和延迟。
3.层交叉规则：避免信号线在不同层之间频繁切换，减少反射和串扰。
如果需要交叉布线，应尽量避免延迟不匹配。
4.电源和地线：为SDRAM提供稳定的电源和地线是非常重要的。
布线时需要确保电源和地线的可靠连接、低噪声和低电阻。
最后，还有一些其他的技巧可以帮助优化SDRAM布线：1.参考设计：可以参考已有的成熟设计和布局规则，避免重复工作和一些常见的布线问题。
2.仿真与验证：使用电磁仿真工具和布线验证工具进行仿真和验证，确保布线符合设计要求并满足性能要求。
3.信号完整性分析：通过信号完整性分析工具，检测和分析信号线中的时序失真和耦合问题，从而优化布线布局。
总结起来，SDRAM布线规则和技巧可以帮助优化布线效果、提高信号完整性，确保SDRAM的性能和稳定性。
SDRAM的布线规则 基于Allegro嵌入式高速电路布线设计
SDRAM的布线规则基于Allegro嵌入式高速电路布线设计1 引言随着嵌入式微处理器主频的不断提高，信号的传输处理速度越来越快，当系统时钟频率达到100MHZ以上，传统的电路设计方法和软件已无法满足高速电路设计的要求。
在高速电路设计中，走线的等长、关键信号的阻抗控制、差分走线的设置等越来越重要。
笔者所在的武汉华中科技大学与武汉中科院岩土力学所智能仪器室合作.以ARM9微处理器EP9315为核心的嵌入式系统完成工程检测仪的开发。
其中在该嵌入式系统硬件电路设计中的SDRAM和IDE等长走线、关键信号的阻抗控制和差分走线是本文的重点，同时以cirrus logic公司的网络物理层接13芯片cs8952为例详细介绍了网络部分的硬件电路设计，为同类高速硬件电路设计提供了一种可借鉴的方法。
2 硬件平台 2.1 主要芯片本设计采用的嵌入式微处理器是Cirrus Logic公司2004年7月推出的EP93XX系列中的高端产品EP9315。
该微处理器是高度集成的片上系统处理器，拥有200兆赫工作频率的ARM920T内核，它具有ARM920T内核所有的优异性能，其中丰富的集成外设接口包括PCMCIA、接口图形加速器、可接两组设备的EIDE、1/10/100Mbps以太网MAC、3个2.0全速HOST USB、专用SDRAM通道的LCD接口、触摸屏接口、SPI串行外设接口、AC97接口、6通道I2S接口和8*8键盘扫描接口.并且支持4组32位SDRAM的无缝连接等。
主芯片丰富的外设接口大大简化了系统硬件电路.除了网络控制部分配合使用Cirrus Logic公司的100Base—X/10Base-T物理层(PHY)接口芯片CS8952外，其他功能模块无需增加额外的控制芯片。
2.2 系统主体结构由图1可见.系统以微处理器EP9315为核心，具有完备的外设接口功能，同时控制工程检测仪。
IDE/CF卡接口为工程检测数据提供大容量移动存储设备；扩展32M的SDRAM作为外部数据存储空间；3个主动USB 接口支持USB键盘鼠标；LCD接口支持STN/TFT液晶和触摸屏.为用户提供友好的交互界面；1/10/100 Mbps以太网为调试操作系统时下载内核及工程检测时远程监控提供途径；面板按键为工程人员野外作业无法使用键盘鼠标时提供人机交互接口。
DDRSDRAM布线规则
DDRSDRAM布线规则DDRSDRAM布线规则是指在电路板上设计和布置DDRSDRAM的电路和连线时需要遵循的一些规则和原则。
DDRSDRAM是一种双倍速率同步动态随机存储器，用于高速数据存储和访问，因此布线规则尤为重要，可以确保信号的完整性和稳定性，提高系统的性能和可靠性。
以下是DDRSDRAM布线规则的一些重要方面：1.线长匹配：DDRSDRAM的布线中，所有的时钟、地址、数据和控制信号必须尽量保持相等的线长。
由于DDRSDRAM使用双倍速率，信号频率较高，线长差异可能导致信号到达时间不一致，影响系统的稳定性。
通过保持线长相等，可以降低信号的传输延迟，减少时钟失真和时序错误。
2.地与电源平面：DDRSDRAM的布线中，要为信号线和电源线提供良好的地和电源环境。
通过使用地和电源平面，可以降低信号线上的互损耗和串扰，提高信号的信噪比和阻抗匹配。
电源平面还可以提供稳定的电源供应，减少功率噪声和波动对信号传输的影响。
3.信号隔离：DDRSDRAM的布线中，需要将不同类型的信号线进行隔离，避免互相干扰。
例如，时钟信号和数据信号应尽量分开布线，以减少互相之间的串扰。
同时，还应将高速信号线和低速信号线进行分离，避免高速信号对低速信号的影响。
4.差分信号：DDRSDRAM的部分信号采用差分传输方式，例如，地址和数据线。
在布线时，要确保差分线对称和匹配。
差分线对称性可以减少共模噪声的影响，而差分线匹配可以提高差分信号的传输效率和抗干扰能力。
5.终端电阻：DDRSDRAM的布线中，需要正确设置终端电阻来匹配信号线的特性阻抗。
终端电阻的作用是反射信号的能量，减少信号反射和回波干扰。
正确设置终端电阻可以提高信号的传输质量，减少时序错误和噪声。
6.时序调整：DDRSDRAM的布线中，需根据具体的DDRSDRAM芯片和系统要求进行时序调整。
时序调整包括延迟设置、预充电设置和时钟节拍调整等。
通过合理设置时序参数，可以确保DDRSDRAM正常工作，提高数据传输的稳定性和速度。
DDR2 DDR3 SDRAM的PCB布线规则指导
Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 MemoriesFidus Systems Inc.900, Morrison Drive, Ottawa, Ontario, K2H 8K7, CanadaChris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed BokhariSession # 8.13AbstractThe paper addresses the challenge of meeting Signal Integrity (SI) and Power Integrity (PI) requirements of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conventional technology. Some design guidelines have been provided.1. IntroductionDDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently, 1066 Mbps. DDR3 [2] targets a data rate of 1600 Mbps. From a PCB implementation standpoint, a primary requirement is delay matching which is dictated by the timing requirement. This brings into it a number of related factors that affect waveform integrity and delay. These factors are interdependent, but where a distinction can be made, they can be termed PCB layer stackup and impedance, interconnect topologies, delay matching, cross talk, PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations.Table 1: Comparison of DDR2 and DDR3 requirementsSignals common to both technologies and a general comparison of DDR2 and DDR3 is shown in Table 1. It must be noted that “matching” includes cases where the clock net may be made longer (termed DELTA in ALLEGRO SigXP). We have assumed a configuration comprising a Controller and two SDRAMs in most illustrations that follow.2. PCB Layer stackup and impedanceIn a layer constrained implementation, a 4 layer PCB (Figure 1) is a minimum with all routing on TOP and BOTTOM layers. One of the internal layers will be a solid ground plane (GND). The other internal plane layer is dedicated to VDD. Vtt and Vref can be derived from VDD. Use of a 6-layer PCB makes the implementation of certain topologies easier. PI is also enhanced due to the reduced spacing between power and GND planes. The interconnect characteristic impedance for DDR2 implementation can be a constant. A single-ended trace characteristic impedance of 50 Ohms can be used for all single-ended signals. A differential impedance of 100 Ohms can be used for all differential signals, namely CLOCK and DQS. Further, the termination resistor pulled up to VTT can be kept at 50 Ohms and ODT settings can be kept at 50 Ohms.In the case of DDR3 however, single ended trace impedances of 40 and 60 Ohms used selectively on loaded sections of ADDR/CMD/CNTRL nets have been found to be advantageous. Further, the value of the termination resistor pulled up to Vtt needs to be optimized in combination with the trace impedance through SI simulations. Typically, it is in the range 30 – 70 Ohms. The differential trace impedance can remain at 100 Ohms.Figure 1 : Four and Six layer PCB stackup3. Interconnect TopologiesIn both cases of DDR2 and DDR3, DQ, DM and DQS signals are point-to-point and do not need any topological consideration. An exception is in the case of multi-rank Dual In Line Memory Modules (DIMMs). Waveform integrity is also easily addressed by a proper choice of drive strengths and On Die Termination (ODT). The ADDR/CMD/CNTRL signals, and sometimes the clock signal will involve a multipoint connection where a suitable topology is needed. Possible choices are indicated in Figure 2 for cases involving two SDRAMs. The Fly-By Topology is a special case of a daisy chain with a very short or no stub.For DDR3, any of these topologies will work, provided that the trace lengths are minimized. The Fly-by topology shows the best waveform integrity in terms of an increased noise margin. This can be difficult to implement on a4-layer PCB and the need for a 6-layer PCB arises. The daisy chain topology is easier to implement on a 4 layer PCB. The tree topology on the other hand requires the length of the branch AB to be very close to that of AC (Figure 2). Enforcing this requirement results in the need to increase the length of the branches which affects waveform integrity. Therefore, for DDR3 implementation, the daisy chain topology with minimized stubs proves to be best suited for 4-layer PCBs.For DDR2-800 Mbps any of these topologies are applicable with the distinction between each other being less dramatic. Again, the daisy chain proves to be superior in terms of both implementation as well as SI.Where more than two SDRAMs are present, often, the topology can be dictated by constraints on device placement. Figure 3 shows some examples where a topology could be chosen to suit a particular component placement. Of these, only A and D are best suited for 4-layer PCB implementation. Again, for DDR2-800 Mbps operations all topologies yield adequate waveform integrity. For a DDR3 implementation, in particular at 1600 Mbps, only D appears to be feasible.Vtt RtRtRtTree topology Fly-By topologyFigure 2: ADDR/CMD/CNTRL topologies with 2 SDRAMS(A)Figure 3: ADDR/CMD/CNTRL topologies with four SDRAMS4. Delay matchingImplementing matched delay is usually carried out by bending a trace in a trombone shape. Routing blockage may require layer jumping. Unfortunately, while physical interconnect lengths can be made identical in layout, electrically, the two configurations shown in Figure 4 will not be the same.The case of trombone delay has been well understood, and the case of a via is obvious. The delay of a trombone trace is smaller than the delay of a straight trace of the same center-line length. In the case of a via, the delay is more than that of a straight microstrip trace of length equal to the via length. The problem can be resolved in two different ways. In the first approach, these values can be pre-computed precisely and taken into account while delay matching. This would become a tedious exercise which could perhaps be eased with userRtRtRt(B)(C)(D)Rtdefined constraints in ALLEGRO 16.0. In the second approach, one would use means to reduce the disparity to an acceptable level.Trombone traceStraight traceL 3L 2 L 4 ≠L 1L 5Figure 4: Illustration of Trombone traces and ViasFigure 5: Circuit for estimation of trombone effect and resulting waveforms.≠Straight traceVia cross sectional viewConsider the case of a trombone trace. It is known that the disparity can be reduced by increasing the length of L3 (Figure 4). Details can be found in reference [3]. A simulation topology can be set up in SigXP to represent parallel arms of a trombone trace as coupled lines. A sweep simulation is carried out with L3 (S in Figure 5) as a variable and the largest reasonable value that reduces the delay difference with respect to a reference trace is selected. For microstrip traces, L3 > 7 times the distance of the trace to ground is needed.Delay values are affected in a trombone trace due to coupling between parallel trace segments. Another way to reduce coupling without increasing the spacing is to use a saw tooth profile. The saw tooth profile shows better performance as compared to a trombone although it eventually ends up requiring more space. In either case, it is possible to estimate the effect on delay precisely by using a modified equation for the computation of the effective trace length [3]. This would need to be implemented as a user defined constraint in ALLEGRO.Consider the case of a through hole via on the 6 layer stackup of Figure 2. Ground vias placed close to the signal vias play an important role in the delay. For the illustration, the microstrip traces on TOP and BOTTOM layers are 150 mils long, and 4 mils wide. The via barrel diameter = 8 mils, pad diameter is 18 mils and the anti-pad diameter is 26 mils.Three different cases are considered. In the first case, the interconnect with via does not have any ground vias in its immediate neighborhood. Return paths are provided at the edges of the PCB 250 mils away from the signal via. In the second case, a reference straight microstrip trace of length = 362 mils is considered. The third case is the same as case 1 with four ground vias in the neighborhood of the signal via. Computed s-parameters with 60 Ohm normalization are shown in Figure 6. It can be seen that the use of 4 ground vias surrounding the signal via makes its behavior more like a uniform impedance transmission line and improves the s21 characteristic. In the absence of a return path in the immediate neighborhood, the via impedance increases. For the present purpose, it is important to know the resulting impact on the delay.A test circuit is set up similar to Figure 5. The driver is a linear source of 60 Ohms output impedance and outputs a trapezoidal signal of rise time = fall time = 100 ps and amplitude = 1V. It is connected to each of the 3 interconnects shown in Figure 6 and the far end is terminated in a 60 Ohm load. The excitation is a periodic signal with a frequency of 800 MHz. The time difference between the driver waveform at V = 0.5 V and the waveform at the receiver gives the switched delay.Results are illustrated in Figure 7 where only the rising edge is shown. It can be seen that the delay with four neighboring ground vias differs from that of the straight trace by 3 ps. On the other hand, the difference is 8 ps for the interconnect with no ground vias in the immediate neighborhood.It is therefore clear that increasing the ground via density near signal vias will help. However, in the case of 4 layer PCBs, this will not be possible as the signal traces adjacent to the Power plane will be referenced to a Power plane. Consequently, the signal return path would depend on decoupling. Therefore, it is very important that the decoupling requirement on 4 layer PCBs addresses return paths in addition to meeting power integrity requirements.The clock net is differential in both DDR2 and DDR3. In DDR2, DQS can be either single ended or differential although it is usually implemented as differential at higher data rates. The switched delay of a differential trace is less than that of a single ended trace of identical length. Where timing computations indicate the need, the clock and DQS traces may need to be made longer than the corresponding ADDR/CMD/CNTRL nets and DATA nets.and DQ nets.Since DQ and DM nets run at the maximum speed, it is desirable that all of these nets in any byte lane be routed identically, preferably without vias. Differential nets are less sensitive to discontinuities and where layer jumping is needed, the DQS and CLOCK nets should be considered first.Figure 6: s-parameters of interconnects with vias (60 Ohm normalization)Figure 7: Driver and Receiver waveforms for the 3 cases of Figure 6. (Plot colors correspond)5. CrosstalkCross talk contributes to delay uncertainty being significant for microstrip traces. This is generally reduced by increasing the spacing between adjacent traces for long parallel runs. This has the drawback of increasing the total trace length and therefore a reasonable value must be chosen. Typically the spacing should be greater than twice the trace distance to ground. Again, ground vias play an important role. Near and far end coupling levels are illustrated in Figure 8. Use of multiple ground vias reduces coupling levels by 7 dB. To derive the interconnect budget, a simulation of a victim trace with two aggressors on both sides is adequate. Using a periodic excitation on all nets will yield the cross talk induced jitter. Using a pseudo random excitation on all nets will show the effect of both cross talk as well as data dependencies. Time domain results are not shown here, but it is easily done by setting up a 5 coupled line circuit in SigXP with the spacing between traces set up for sweeping. Reasonable spacing values that keep the jitter in the waveform due to both cross talk as well as pattern dependence at an acceptable level are chosen.Figure 8: s-parameters of coupled traces (60 Ohm normalization)6. Power IntegrityPower Integrity here refers to meeting the Power supply tolerance requirement under a maximum switching condition. Failure to address this requirement properly leads to a number of problems, such as increased clock jitter, increased data dependent jitter, and increased cross talk all of which eventually reduce timing margins.The theory for decoupling has been very well understood and usually starts with the definition of a “target impedance” as [4]CurrentTransient tolerance Voltage Z et t =arg (1)An important requirement here is knowledge of the transient current under worst case switching condition. A second important requirement is the frequency range. This is the range of frequencies over which the decoupling network must ensure that its impedance value is equal to or below the required target impedance. On a printed circuit board, capacitance created by the Power-Ground sandwich and the decoupling capacitors needs to handle a minimum frequency of ~100 kHz up to a maximum frequency of ~100-200 MHz. Frequencies below 100 kHz are easily addressed by the bulk capacitance of the voltage regulator module. Frequencies above 200 MHz should be addressed by the on-die and in some cases on-package decoupling capacitance. Due to the finite inductance of the package, there is no need to provide decoupling on the PCB to handle frequencies greater than 200 MHz. The actual computation of power integrity can be very complex involving IC package details, simultaneously switched signals and the PCB power distribution network. For PCB design, the use of the target impedance approach to decoupling design is simpler and provides a practical solution with very little computational effort.The three power rails of concern are the VDD, VTT and Vref. The tolerance requirements on the VDD rail is ~ 5% and the transient current is determined as the difference between Idd7 and Idd2 as specified by JEDEC [1,4]. This is accomplished by using plane layers for power distribution and a modest number of decoupling capacitors. It is preferable to use decoupling capacitors of 10 different values distributed in the range of 10 nF to 10 uF. Further, the capacitor pad mounting structure should be designed for reduced mounted inductance.The Vref rail has a tighter tolerance, but it draws very little current. Its target impedance is easily met using narrow traces and one or two decoupling capacitors. It is important however that the capacitors be located very close to the device pins.The VTT rail proves to be challenging because it not only has a tighter tolerance, but it also draws a transient current close to that of the VDD rail. The transient current is easily calculated as described in reference [5]. Again, the target impedance requirement can be met using an increased number of decoupling capacitors.On a 4 layer PCB, the planes are too far apart and consequently the advantage of inter-plane capacitance is lost. The number of decoupling capacitors needs to be increased and higher frequency capacitors with values less than 10 nF may be needed. These computations are easily done using ALLEGRO SI Power Integrity option.7. TimingTiming computation is carried out as described in reference [6]. A table needs to be setup for the following eight cases: 1. 2. 3. 4. 5. 6. 7. 8. Write Setup analysis DQ vs. DQS Write Hold analysis DQ vs. DQS Read Setup analysis DQ vs. DQS Read Hold analysis DQ vs. DQS Write Setup analysis DQS vs. CLK Write Hold analysis DQS vs. CLK Write Setup analysis ADDR/CMD/CNTRL vs. CLK Write Hold analysis ADDR/CMD/CNTRL vs. CLKAn example is shown for the case of Write setup analysis in Table 2. Actual numbers have been omitted as they are not precisely known yet for DDR3. These numbers are obtained from data sheets of Controller and memory manufacturers. The numbers in the interconnect section are determined by SI simulations. All the eight cases need to be analyzed for DDR2. For DDR3, 5 and 6 are not needed due to its write leveling feature. In the PCB implementation, length match tolerances must ensure that the total margin is positive. ElementControllerSkew Componenta.)DQ vs. DQS skew at transmitter output b.) Data / Strobe PLL jitter a+b Setup requirement (tDSb @ Vih/Vil level) DQ slew rate DQS slew rateSetupUnitsps ps ps psCommentsFrom controller design data Used if not included in transmitter skewTotal Controller SDRAM (or DIMM)V/ns V/ns psTotal SDRAM setup requirement InterconnecttDSb + slew rate adjustmentFrom SDRAM datasheet; this number is to be adjusted based on DQ and DQS slew rates Measured as per JEDEC specification from SI simulation results Measured as per JEDEC specification from SI simulation results Includes slew rate adjustmenta.) Data Xtalk b.) DQS Xtalk c.) Length matching tolerance d.) Characteristic impedance mismatch Total Interconnect Min. Total Setup Budget Setup margin Interconnect skew (a + b + c + d) 0.24*tckps ps ps ps2 aggressors (one each side of the victim); victim – repetitive; aggressor- PRBS 2 aggressors (one each side of the victim); victim – repetitive; aggressor- PRBS Extracted from SI simulation results longest data net, worst case PVT corner can be omitted if routing of DQ and corresponding DQS signals are done on same layerps ps From SDRAM datasheet (includes clock duty cycle variation) Must be positiveMin. Total Setup Budget – (Total Controller + Total SDRAM + Total Interconnect )psTable 2: Illustration of DDR3 Write Setup timing analysis summary for DQ vs. DQS8. PCB LayoutImplementation on a PCB involves a number of tradeoffs to meet SI requirements. Often, the question is how far does one need to go? PCB layout tasks are facilitated using the following approach: 1. Set up topology and constraints in ALLEGRO Constraint Manager. 2. Design Controller BGA breakout. A controller pin arrangement with ADDR/CMD/CNTRL pins in the middle and DQ/DQS/DM byte lanes on either side is best suited. Within these groups, individual pins may need to be swapped to ensure routing with minimum cross-over. 3. Attempt routing with reduced stub length and a minimum trace spacing as obtained from cross talk simulation. Often, most stubs can be eliminated but it will not be possible for all the pins. One may try two traces between BGA pads of the memory devices. This would require narrow PCB traces which can increase manufacturing cost. Yet, it will not be possible for all signals unless micro via and via-in-pad technology is used. Complete routing with coarse length matching tolerances. 4. Place Vref decoupling capacitors close to the Vref pins. Vtt decoupling can be placed at the far end of the last SDRAM and will not come in the way of routing. VDD decoupling can be placed close to devices where possible without blocking routing channels. The smaller valued capacitors should be placed closer to the devices. With a proper decoupling design, it will not be necessary to cram all capacitors close to the devices. All decoupling capacitors should use a fan out for the footprint designed for reduced inductance. This is typically two short wide traces perpendicular to the capacitor length. This can be automated by using a user defined capacitor footprint that can be attached to all the decoupling capacitors in the schematic. 5. Implement fine length matching and insert multiple ground vias where signal traces jump layers. It is better to use the delay matching option in ALLEGRO and one must include z-axis delay. Typically, P and N nets of differential pairs should be matched with a tolerance of +/- 2ps and the tolerance for all other matched nets can be +/- 10 ps or more based on the timing margin computation.9. DIMMConsiderations described above apply to the case of PCBs containing one or more DIMMs. The only exception is that the decoupling requirement for the memories can be relaxed as it is already accounted for on the DIMM PCB. SI analysis of registered DIMMs is also much simpler where the DIMM is treated as a single load. While the routing topology for ADDR/CMD/CNTRL nets is usually a daisy chain with reduced stubs, tree topologies can also be used for registered DIMMs. Analysis of un-buffered DIMMs can become tedious as the timing requirement at all the SDRAMs must be analyzed. DIMM routing on 4-layer PCBs is relatively simpler compared to the case of SDRAMs.10. ExamplesThe detail described above has been used in the implementation of a DDR2 PCB, a DDR3 PCB and a DDR3 – DIMM PCB. The controller is from MOSAID [7] which is designed to provide both DDR2 as well as DDR3 functionality. For the SI simulations, IBIS models have been used. Models for the memories are from MICRON Technology, Inc [8]. The IBIS models for the DDR3 SDRAMs were available at 1333 Mbps speed. These were used at 1600 Mbps. For the unbuffered DDR3 DIMM (MT_DDR3_0542cc) EBD models from Micron Technology were used. All waveforms are for the typical case and are computed at the SDRAM die. The 6 layer PCB stackup of Figure 2 is used with routing on TOP and BOTTOM layers only. The memory consists of 2 SDRAMsrouted as a daisy chain. In the case of the DIMM, a single unbufferred DIMM is used. TOP/BOTTOM layer routing and Signal Integrity waveforms are shown in Figures. 9-11.Snapshots ofFigure 9: Illustration of TOP and BOTTOM layers of a DDR3 PCB with computed waveforms at the farthest SDRAM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net. Clock frequency = 800 MHz and data rate is 1600 Mbps.Figure 10: Illustration of TOP and BOTTOM layers of a DDR2 PCB with computed waveforms at the farthest SDRAM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net. Clock frequency = 400 MHz and data rate is 800 Mbps.Figure 11: Illustration of TOP and BOTTOM layers of a DDR3 – DIMM PCB with computed waveforms at the 8th (last) SDRAM on DIMM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net.Lastly, Figure 12 shows a comparison of computed and measured DATA eye patterns of an 800 Mbps DDR2. In all cases waveform integrity can be seen to be excellent.Figure 12: Computed (Red) and Measured (blue) waveforms of a data net of an 800 Mbps DDR2 PCB.11. ConclusionIn this paper, all aspects related to SI, and PI of DDR2 and DDR3 implementation have been described. Use of Constraint Manager in ALLEGROTM makes implementation easy. While a four layer PCB implementation of 800 Mbps DDR2 and DDR3 appears to be feasible, DDR3-1600 Mbps will prove to be challenging. It will become clearer as the memory devices become available and one has a good handle on timing numbers.References[1] DDR2 SDRAM Specification, JEDEC JESD79-2B, January 2005. [2] DDR3 SDRAM Standard, JEDEC JESD79-3, June 2007. [3] Syed Bokhari, “Delay matching on Printed Circuit Boards”, Proceedings of the CDNLIVE 2006, San Jose. [4] Larry D Smith, and Jeffrey Lee, “Power Distribution System for JEDEC DDR2 memory DIMM, Proc. IEEE EPEP conference, Princeton, N.J., pp. 121-124, October 2003. [5] Hardware and layout design considerations for DDR2 SDRAM Memory Interfaces, Freescale semiconductor Application Note, Doc. No. AN2910, Rev. 2, 03/2007. [6] DDR2 design guide for 2 DIMM systems, Technical Note, Micron Technology Inc. TN-47-01, 2003. [7] /corporate/products-services/ip/SDRAM_Controller_whitepaper_Oct_2006.pdf [8] /products/dram/ddr2/partlist.aspx?speed=DDR2-800 [9] /products/dram/ddr3/partlist.aspx?speed=DDR3-1066。
SDRAM布线规则
SDRAM布线规则一：SDRAM 类高速器件布线规则通用基本法则：（1）DDR和主控芯片尽量靠近（2）高速约束中设置所有信号、时钟线等长(最多允许50mil的冗余)，所有信号、时钟线长度不超过1000mil （3）尽量0过孔，元件层下面一定要有一个接地良好的地层，所有走线不能跨过地的分割槽，即从元件层透视地层看不到与信号线交叉的地层分割线。
这样的话200M的DDR基本上是没有太大问题。
其它的一些3W 20H法则能做到就尽量做到吧时钟信号：以地平面为参考，给整个时钟回路的走线提供一个完整的地平面，给回路电流提供一个低阻抗的路径。
由于是差分时钟信号，在走线前应预先设计好线宽线距，计算好差分阻抗，再按照这种约束来进行布线。
所有的DDR差分时钟信号都必须在关键平面上走线，尽量避免层到层的转换。
线宽和差分间距需要参考DDR控制器的实施细则，信号线的单线阻抗应控制在50～60 Ω，差分阻抗控制在100～120 Ω。
时钟信号到其他信号应保持在20mil以上的距离来防止对其他信号的干扰。
蛇形走线的间距不应小于20 mil。
串联终端电阻RS值在15～33Ω，可选的并联终端电阻RT 值在25～68 Ω，具体设定的阻值还是应该依据信号完整性仿真的结果。
数据信号组：以地平面为参考，给信号回路提供完整的地平面。
特征阻抗控制在50～60 Ω。
线宽要求参考实施细则。
与其他非DDR 信号间距至少隔离20 mil。
长度匹配按字节通道为单位进行设置，每字节通道内数据信号DQ、数据选通DQS和数据屏蔽信号DM长度差应控制在±25 mil内(非常重要)，不同字节通道的信号长度差应控制在1 000 mil内。
与相匹配的DM和DQS串联匹配电阻RS值为0～33 Ω，并联匹配终端电阻RT值为25～68Ω。
如果使用电阻排的方式匹配，则数据电阻排内不应有其他DDR信号。
地址和命令信号组：保持完整的地和电源平面。
特征阻抗控制在50～60 Ω。
SDRAM介绍及PCBLayout处理
SDRAM介绍及PCBLayout处理SDRAM的特点是操作和数据的同步，数据的读写都是在时钟信号的驱动下进行的。
相较于其他类型的DRAM，SDRAM具有更高的带宽和更快的访问速度。
它的数据传输是按照时钟信号的边沿触发进行的，数据的传输速率取决于时钟频率。
在PCBLayout处理中，布局和布线是两个主要方面。
对于SDRAM的布局，需要考虑以下几个因素：1.电源和地线：为SDRAM提供稳定的电源和接地，可以采用多层板设计，将电源和地线尽可能地贴近SDRAM芯片。
2.时钟线：时钟信号对于SDRAM的读写操作非常重要，应避免与其他信号线相交，减少互相干扰。
可以采用较短的时钟线长度，以减小传输延迟。
3.数据线：数据线也是SDRAM的关键信号，需要将其布置得尽可能短且对称。
对称布线可以减小信号传输的抖动，提高数据传输的稳定性。
4.地域规划：在整个布局过程中，需要合理规划SDRAM芯片的位置和周围的元器件。
将相应的引脚和信号线放置在合适的位置，以提高信号传输的效率和可靠性。
在布线处理中，需要考虑以下几个因素：1.长度匹配：对于时钟线和数据线，需要保持匹配的长度，以避免信号传输的不同步。
可以使用电荷平衡的技术来实现长度匹配。
2. 隔离：对于时钟信号和数据信号，需要尽量避免相互干扰。
可以采用隔离插入（isolation insertion）的方法，在时钟线和数据线之间插入隔离段，使它们互不干扰。
3.地域规划：在布线过程中，需要合理规划地面线。
保持地面线的平稳和连续性，减小信号的回流路径，避免信号互相干扰。
4.控制线：除了时钟和数据线外，还需要合理布置控制线。
控制线主要用于SDRAM的读写控制和激活操作，需要与其他信号线保持一定的距离，以防止相互干扰。
总之，在PCBLayout处理中，要考虑SDRAM的布局和布线因素，以保证SDRAM的正常工作和高性能。
合理的布局和布线可以减小信号传输的延迟和抖动，提高数据传输的速度和稳定性。
SDRAM布线
再谈SDRAM的布线——有关Mentor WG、DxDesinger、Expedition、CES2008-06-18 14:57•前言的前言这篇文章我写了很久很久，因为最近很忙很忙。
现在我逐渐开始接触开关电源和可靠性设计的东西，好像离原来我定义的EE越来越远了。
也许以后我要向模电或管理人员发展了……我还是纯朴地希望自己能一直保持做一个不断钻研的EE工程师。
不说了，做人要厚道，转载请注明来自我是一只鱼同学的EE小站，邮件地址cosine@。
•前言最近一个多月都在研究Mentor WG，已经对DxDesigner + Expedition的画板流程有了比较清醒的认识，我对Mentor WG评价可以套用对目前国产汽车的评价——配置齐全、做工粗糙。
虽然WG有很强的功能，但是BUG实在是数不胜数，而且有些BUG可能导致你的工程彻底报废，所以建议使用时辅以自动备份软件，减小工程崩溃带来的损失。
今天要谈的话题都是基于WG的，因为PADS、Protel / DXP之类的软件没有这样的功能或功能不完整。
不过，也可以使用其他软件进行PCB前仿、手动完成线长匹配等工作；工具只是人的技巧的辅助和延伸，要是没有高速PCB设计的知识，同样完不成高速数字PCB的设计。
本文为我是一只鱼同学EE小站的原创文章，转载请注明出处；本文对初学者而言，技术难度较高，如果有不明白的地方，可以留言。
另外继续废话几句，事实上SDRAM对布线的要求是很低的，DDR才是真正有挑战的东西，可惜我目前没有DDR的项目，也没有办法验证我对理论的理解，希望以后有机会和大家分享我的心得。
下面正式开始：•什么是高速数字PCB，怎么入手？高速数字PCB简单来说可以理解为关键部分如存储器总线的工作频率高于数十至一百MHz的PCB，更严格的定义应该用传输线来描述，当PCB上的信号的传输延迟大于上升时间的1/10时，这个信号的传输路径就应该视为传输线；即应当用与传统低速数字电路不同的方法对待。
DDR2 BGA布局、布线经验谈
DDR2 SDRAM×32布局、布线经验谈对于DDR2的布局、布线来说，最关键的就是要非常地熟悉DDR2中DQ、DM、DQS 和FPGA芯片中DQ/DQS Pins的分布情况，为了更直白的说明这个问题，咱们来看图说话，解析：考虑到DDR2走高速信号时的信号完整性质量，首先要满足最基本的布线要求（还有信号线的等长）：（1）DQ[0:7]、DM0、DQS0这10根信号线要在同一层；（2）DQ[8:15]、DM1、DQS1这10根信号线要在同一层；（3）DQ[16:23]、DM2、DQS2这10根信号线要在同一层；（4）DQ[24:31]、DM3、DQS3这10根信号线要在同一层；其中（1）和（3）可以在同一层（如S1）实现顺利布线，而（0）和（2）可以在同一层（如S2）实现顺利布线。
上面这个图中我特意用笔把所有Pins的分布情况给大致分割了一下，这样看起来会一目了然。
布线时应该把上面一个部分（即A、B、C、D）里面的DQ、DM、DQS总共10根信号线作为一个单元，对应FPGA芯片里特定的一个PIN区域，下面E、F、G、H这个部分也是类似的。
不过布线时还应该注意的地方就是：FPGA里的那个所谓的“特定部分”中只有DQS这个Pin是固定不可被替代的，其他的9个Pins中DQ[n:n+7]和DM线是可以任意换序的，因为DQ和DM信号线所对应的Pins在FPGA芯片中是同一个电气属性的。
这个相当关键，不然的话，会给布线带来比较大的麻烦。
关于那个“特定的部分”，我截个图如下所示，不同的颜色即为一个“独立的特定的区域”，我布线时主要用的是下方中间四个“独立的特定的区域”——用于两个DDR2的布线需要，实现32位并行数据流。
画这个板子时我设置的是六层结构（四个信号层+两个参考层），布局、布线结束后的各信号层结果如下：TOP LAYER：LAYER S1：LAYER S2：BOTTOM LAYER：ALL LAYERS：。
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再谈SDRAM的布线——有关Mentor WG、DxDesinger、Expedition、CESPCB 2009-12-01 16:49:27 阅读212 评论0 字号：大中小∙前言的前言这篇文章我写了很久很久，因为最近很忙很忙。
现在我逐渐开始接触开关电源和可靠性设计的东西，好像离原来我定义的EE越来越远了。
也许以后我要向模电或管理人员发展了……我还是纯朴地希望自己能一直保持做一个不断钻研的EE工程师。
不说了，做人要厚道，转载请注明来自我是一只鱼同学的EE小站，邮件地址cosine@。
∙前言最近一个多月都在研究Mentor WG，已经对DxDesigner + Expedition的画板流程有了比较清醒的认识，我对Mentor WG评价可以套用对目前国产汽车的评价——配置齐全、做工粗糙。
虽然WG有很强的功能，但是BUG实在是数不胜数，而且有些BUG可能导致你的工程彻底报废，所以建议使用时辅以自动备份软件，减小工程崩溃带来的损失。
今天要谈的话题都是基于WG的，因为PADS、Protel / DXP之类的软件没有这样的功能或功能不完整。
不过，也可以使用其他软件进行PCB前仿、手动完成线长匹配等工作；工具只是人的技巧的辅助和延伸，要是没有高速PCB设计的知识，同样完不成高速数字PCB的设计。
本文为我是一只鱼同学EE小站的原创文章，转载请注明出处；本文对初学者而言，技术难度较高，如果有不明白的地方，可以留言。
另外继续废话几句，事实上SDRAM对布线的要求是很低的，DDR才是真正有挑战的东西，可惜我目前没有DDR的项目，也没有办法验证我对理论的理解，希望以后有机会和大家分享我的心得。
下面正式开始：∙什么是高速数字PCB，怎么入手？高速数字PCB简单来说可以理解为关键部分如存储器总线的工作频率高于数十至一百MHz的PCB，更严格的定义应该用传输线来描述，当PCB 上的信号的传输延迟大于上升时间的1/10时，这个信号的传输路径就应该视为传输线；即应当用与传统低速数字电路不同的方法对待。
那么怎么入手？我是学机械出身的，电路原理和模电都是三脚猫知识；我个人认为High-Speed Digital System Design是本不错的书。
首先看书，弄明白在频率高了以后会出现什么样的现象，有什么东西需要考虑之后，再继续后面的设计。
不过我可以做个简单的概括，高频数字电路设计的大部分工作是解决传输线中信号反射问题和延迟问题。
BTW，很久以前我还很菜的时候写了一篇文章/blog/cns!4201FDC93932DDAF!171.entry，这是关于PCB后仿的（这个词下面马上解释），大家有兴趣可以看看。
∙高速PCB设计的流程元件布局——〉前仿真——〉布线——〉后仿真——〉出CAM文件其他不多说了，就解释下前仿真和后仿真。
前仿真就是在器件IBIS模型、网络拓扑结构和器件分布的基础上做的对PCB可实现性仿真。
举个例子解释前仿真的作用，如果器件、板子的机械结构都已经定下来了，CPU和SDRAM插座相隔10000mil，那么在布完这个板子之前，怎么知道这个板子能不能正常工作？关于如何使用WG进行前仿真，后面再说。
后仿真就是在板子走线已经成型之后，对布线结果进行验证而作的仿真。
后仿真会在前仿真基础上加上过孔模型、串扰、电磁兼容性等仿真内容。
刚才提到的我的菜菜鸟文章/blog/cns!4201FDC93932DDAF!171.entry，说的就是后仿真。
SDRAM对布线有什么要求？首先必须明白SDRAM是一种什么样的存储器，搞清其接口工作的逻辑时序。
SDRAM是一种同步动态存储器，所有接口信号都是通过时钟同步和采样的。
这就对SDRAM的布线提出了要求——保证采样的正确性。
于是，应用高速数字电路的知识结合某种具体SDRAM器件和你的PCB进行分析，发现在正常工作频率（如100MHz）下，在PCB走线上的信号传输时间大于其上升时间1/10。
于是，接下来考虑高速数字电路两大问题反射和延迟：反射造成SDRAM时钟线信号出现振铃，多次穿越门限造成误触发；数据线和时钟线的传输延迟不相同，造成时钟上升沿采样不到所需要的数据。
接下来应用解决方法：时钟线串联电阻做阻抗匹配；布线时控制数据线和时钟线的长度差在一定范围内。
当然，我这里说的是一个很简单的演绎过程，还有拓扑结构、最大布线长度等重要问题没有考虑，请大家仔细阅读我是一只鱼同学刚才推荐的课本。
提示下，拓扑结构和最大布线长度的选择可以通过前仿真进行验证。
进一步的问题，SDRAM布线用什么拓扑结构好？这个问题困扰了我很久很久，终于在学会前仿真后解决了，哈哈。
其实大家已经很清楚SDRAM要尽量使用Y型分支结构（也叫T型分支），因为链式结构会产生两个问题：一、两片SDRAM的传输延迟不一样，影响CPU对数据输出进行采样；二、链式结构的节点处阻抗不连续，是一个反射点，而且反射点和源的距离太大，反射效果明显。
但是，如果使用Y型分支结构，到底是先分支好呢还是后分支好呢？经过前仿真的验证，分支点靠近CPU的时候效果稍微好那么一点点。
我想这是因为分支点本身是一个阻抗不连续点，也是会发生反射的。
如果分支点靠近源端CPU，反射就会因为传输线的缩短而显得不太明显。
我给分枝点靠近CPU的这种拓扑结构起个名字，叫短桩Y型分支结构。
怎样用WG进行PCB前仿真？WG中PCB的前仿真的步骤：DxDesigner画原理图——〉Expedition布局——〉CES指定IBIS模型——〉CES指定网络的拓扑结构——〉ICX Pro 前仿真。
我们来看图说话。
对于下面这样一个已经完成布局的PCB，从Expedition的工具栏中选择CES在CES的窗口中见的选项卡中，选择Parts例如对SDRAM的走线进行前仿真，就需要制定CPU、SDRAM以及其他连接在数据总线上的器件的IBIS模型。
相应的模型可以在器件的官方网站上下载到。
在Parts里选中要指定模型的器件。
在弹出的窗口中按照步骤1、2、3（后续图片中的1、2、3、4亦表示步骤）选择IBIS模型文件选好后就OK，重复以上步骤直到把要进行仿真的信号所连接的所有器件的IBIS模型都选上。
有的IBIS文件中含有多个器件的模型，选择你需要的在SDRAM信号设计的时候往往会使用电阻对信号进行阻抗匹配，这时候SDRAM布线的拓扑结构就会变成下面这样这个电阻也必须包含到前仿真中去。
但是在实际设计中，往往有很多需要匹配的信号，所以一般是使用排阻的。
但是默认情况下，CES是不认识排阻的，这需要设置。
选择Setup菜单下的Settings…在弹出的窗口中选择Discrete Component Prefixes选项页，将你所用的排阻前缀输入（如RM），然后确认随后你就会发现CES把你的排阻认为是串行器件了。
顺便提下，如上面这张图所示，CES会把这些已经定义前缀的器件识别为串行器件。
识别为串行器件有好处也有坏处，好处是对于真正用于阻抗匹配等目的的器件，前后的网络会被归为一个网络进行识别（CES在原来的网络名后面加上“^^^”符号，将两个网络合并）；坏处是很多功能性质的电阻，如运放中设定放大比例的电阻两端的网络也会被归为一个网络识别，这时候就需要把下面这张图中所示的钩号去掉。
接下来，点击Parts边上的Nets选项卡，选择SDRAM的信号随后配置网络拓扑结构。
对于SDRAM的控制线来说，它们不连接在SDRAM之外的其他上，因此其拓扑结构一般都是之前描述的这种：对于一般的地址线而言，往往需要连接除SDRAM芯片之外的其他器件，如NOR Flash，其拓扑结构可能是这样的我建议将NOR Flash连接在一个SDRAM的之后，因为如果再搞短桩Y 型分支，那么将会有3组分支线，布线就很困难了。
当然，连接在哪里要根据前仿真的结果来调整，我提供的这种连接对于某些器件应该会有问题。
下面要把SDRAM的信号定义成上面这2种拓扑结构中的一种，在Nets 列表里找到Topology这一列，点击下拉列表。
对于SDRAM时钟信号SDCK这种串联阻抗匹配电阻的拓扑结构而言，选择Complex。
随后点击工具栏上的Netline order按钮（这个按钮左边的几个按钮可以定义其他不同的拓扑结构，与上图列表中对应，依次是MST、Chained、T、Star、HTree、Custom，这些不同拓扑结构的含义可以Google下或者参看Mentor WG CES的手册）出来这样一个对话框之前已经提到SDRAM的地址和控制信号应当是短桩Y型分支，如果还有别的器件就连接在SDRAM之后。
先说明下，因为定义了排阻为串行期间，所以CES自动的将CPU到排阻的连接识别出来并列在管脚对列表里了；管脚列表里蓝色背景的部分是已经在管脚对列表中存在的管脚。
随后就需要定义Y型分支，点击Y型分支拓扑结构图标，再依次点击信号源管脚和两个负载管脚，如下图所示在管脚列表中就会出现如下显示这说明已经定义了一个Y型分支。
定义之后的Y型分支可以删除和修改，具体细节请看CES手册。
随后点击对话框下面的那个复选框，“Automatically create pin pairs from from-tos”，确定，CES的Nets列表中，刚才定义的Net下就出现如下图所示的内容那些L:VP_T_1_1_1181, L:D19-38之类的东西就是产生的拓扑结构描述。
刚才已经提到SDRAM的地址线因为还需连接其他器件，拓扑结构的设置还需要有一步添加自定义管脚对。
以地址线A2举例，同样选择其为Complex结构然后选择工具栏上的Netline order，在出现的对话框中将CPU和SDRAM 之间的连接配置为Y型分支，如下图所示随后配置和NOR Flash芯片的连接，先点击“From pin / pin set”下面的文本框，然后依次点击SDRAM和NOR Flash的管脚，再点击右边的下箭头，如下图于是一个自定义的Pin Pair就出现了，同时管脚列表中对应的管脚背景色也会变蓝，显示这个管脚被指派过了。
需要注意的是，NOR Flash连接在那个SDRAM器件的管脚上是没有要求的，但是为了走线方便，还是建议连接在理NOR Flash相应管脚较近的SDRAM器件上。
接下来同样选中“Automatically create pin pairs from from-tos”复选框，确定，A2的拓扑结构就配置好了。
这里还需要提一个概念——Virtual Pin（虚拟管脚），这是WG为了方便对拓扑结构的管理而设定的一种虚拟的控制点。
还是用图来说明，对于SDRAM的连接拓扑结构WG把图中红圈标示的那个分支点分立出来，当作一个可以控制的元素Virtual Pin，这个元素可以移动、定位；一个Y型分支的拓扑结构就拆分成了各个元件到这个Virtual Pin连接的结构。