伪随机码生成器

M序列发生器
M序列是最常用的一种伪随机序列，是一种线性反馈移位寄存器序列的简称。

带线性反馈逻辑的移位寄存器设定各级寄存器的初试状态后，在时钟的触发下，每次移位后各级寄存器状态都会发生变化。

其中一级寄存器（通常为末级）的输出，随着移位寄存器时钟节拍的推移会产生下一个序列，称为移位寄存器序列。

他是一种周期序列，周期与移位寄存器的级数和反馈逻辑有关。

以4级移位寄存器为例，线性反馈结构如下图：
4级以为寄存器反馈图
其中a4=a1+a0
信号a4:a0禁止出现全0，否则将会出现全0，序列不变化。

实验仿真
Code：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity random_4 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (3 downto 0);
dout : out STD_LOGIC_VECTOR (3 downto 0);
load : in STD_LOGIC);
end random_4;
architecture Behavioral of random_4 is
signal rfsr :std_logic_vector(3 downto 0);
--signal temp:std_logic;
begin
process(clk,reset,load,din)
begin
if (reset ='1') then
rfsr <=(others =>'0');
elsif (clk' event and clk='1') then
if(load ='1') then ----load =1
rfsr<= din;
else
rfsr(3) <= rfsr(0) xor rfsr(1);
rfsr(2 downto 0) <= rfsr(3 downto 1);
end if;
end if;
end process;
------signal rename----
dout <= rfsr;
end Behavioral;
testbench：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY random_testbench IS
END random_testbench;
ARCHITECTURE behavior OF random_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT random_4
PORT(
clk : IN std_logic;
reset : IN std_logic;
din : IN std_logic_vector(3 downto 0);
dout : OUT std_logic_vector(3 downto 0);
load : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal din : std_logic_vector(3 downto 0) := (others => '0'); signal load : std_logic := '0';
--Outputs
signal dout : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
---variable
signal cnt: integer :=0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: random_4 PORT MAP (
clk => clk,
reset => reset,
din => din,
dout => dout,
load => load
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process(clk)
begin
-- hold reset state for 100 ns. if(cnt = 0) then
--initialization
reset <= '1' after 100 ps;
load <= '1' after 100 ps;
din <="0001";
cnt <= cnt +1;---
elsif(cnt =1) then
reset <= '0' after 100 ps;
load <= '1' after 100 ps;
din <="0001";
cnt <= cnt +1;
elsif(clk' event and clk ='1') then reset <= '0' after 100 ps;
load <= '0' after 100 ps;
din <="0001";
---executue
cnt <= cnt +1;
if(cnt = 100) then
cnt <= 2;
end if;
end if;
end process;
END;。