数字钟程序

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div isport(clk3:IN std_logic;clkout1,clkout2:OUT std_logic);end div;architecture one of div isbeginprocess(clk3)variable cnt:integer range 0 to 25000000;variable tmp:std_logic;beginif(clk3'event and clk3='1')thenif cnt>=24999999 then --1s分频cnt:=0;tmp:=not tmp;else cnt:=cnt+1;end if;end if;clkout1<=tmp;end process;process(clk3)variable cnt:integer range 0 to 100000;variable tmp:std_logic;beginif(clk3'event and clk3='1')then --1ms分频if cnt>=25000 thencnt:=0;tmp:=not tmp;else cnt:=cnt+1;end if;end if;clkout2<=tmp;end process;end one;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport ( clk:in std_logic;h1,h0:out std_logic_vector(3 downto 0));end hour;architecture hour_aa of hour issignal q1,q0: std_logic_vector(3 downto 0); BEGINprocess(clk)BEGINIF(clk'event AND clk='1')THENIF (q1="0010" AND q0="0011") THENq1<="0000";q0<="0000";elsif(q0="1001")THENq1<=q1+1;q0<="0000";else q1<=q1;q0<=q0+1;end if;end if;end process;h1<=q1;h0<=q0;end hour_aa;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity min isport ( clk:in std_logic;m1,m0:out std_logic_vector(3 downto 0);co:out std_logic);end min;architecture min_aa of min issignal q1,q0: std_logic_vector(3 downto 0); BEGINp0:process(clk)BEGINIF(clk'event AND clk='1')THENIF (q1="0101" AND q0="1001") THENq1<="0000";q0<="0000";co<='1';elsif(q0="1001")THENq1<=q1+1;q0<="0000";elsif q1="0100" and q0="0000"then q1<="0100" ;q0<="0001";elseq1<=q1;q0<=q0+1;co<='0';end if;end if;end process;m1<=q1;m0<=q0;end min_aa;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux_21a isport ( a,b,sel:in std_logic;y:out std_logic);end mux_21a;architecture one of mux_21a isbeginy<=b when sel='1' elsea;end one;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux_21b isport ( a,b,sel:in std_logic;y:out std_logic);end mux_21b;architecture one of mux_21b isbeginy<=b when sel='1' elsea;end one;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_unsigned.ALL;ENTITY pianxuan ISPORT( clk: IN std_logic;q: OUT std_logic_vector(2 downto 0));END pianxuan ;ARCHITECTURE pianxuan_aa OF pianxuan IS BEGINPROCESS(clk)VARIABLE a: std_logic_vector(2 downto 0); BEGINIF (clk'event AND clk='1')THENA:=a+1;END IF;Q<=a;END PROCESS;END pianxuan_aa;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport ( clk:in std_logic;s1,s0:out std_logic_vector(3 downto 0);co:out std_logic);end second;architecture second_aa of second issignal q1,q0: std_logic_vector(3 downto 0); BEGINp0:process(clk)BEGINIF(clk'event AND clk='1')THENIF (q1="0101" AND q0="1001") THENq1<="0000";q0<="0000";co<='1';elsif(q0="1001")THENq1<=q1+1;q0<="0000";elseq1<=q1;q0<=q0+1;co<='0';end if;end if;end process ;s1<=q1;s0<=q0;end second_aa;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity seltime isport(disclk:in std_logic_vector(2 downto 0);conv:in std_logic;s0,s1,m0,m1,h0,h1:in std_logic_vector(3 downto 0);dataout:out std_logic_vector(3 downto 0);wsel:out std_logic_vector(3 downto 0);y:out std_logic);end seltime;architecture st of seltime issignal count:std_logic_vector(1 downto 0);beginp0:process(disclk,conv)beginif conv='0' thencase disclk iswhen "000"=>dataout<=h1;when "001"=>dataout<=h0;when "010"=>dataout<=m1;when others=>dataout<=m0;end case;case disclk iswhen "000"=>wsel<="0111";when "001"=>wsel<="1011";when "010"=>wsel<="1101";when others=>wsel<="1110";end case;elsecase disclk iswhen "000"=>dataout<=s1;when others=>dataout<=s0;end case;case disclk iswhen "000"=>wsel<="1101";when others=>wsel<="1110";end case;end if;end process;p1:process(m1,m0)beginif (m1="0101" and m0="1001" and s1="0101") thenif(s0="0000"or s0="0010" or s0="0100" or s0="0110" or s0="1000") then y<='0';else y<='1';end if;end if;end process;end st;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport(a:in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end xianshi;architecture one of xianshi isbeginy<="1111110" WHEN a="0000" else"0110000" WHEN a="0001" else"1101101" WHEN a="0010" else"1111001" WHEN a="0011" else"0110011" WHEN a="0100" else"1011011" WHEN a="0101" else"1011111" WHEN a="0110" else"1110000" WHEN a="0111" else"1111111" WHEN a="1000" else"1111011" WHEN a="1001" else"0000000" ;end one;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shuzizhong isport (P,Q,R,O:in std_logic;S:out std_logic_vector(6 downto 0);T:out std_logic_vector(3 downto 0);W:out std_logic);end shuzizhong;architecture shuzi of shuzizhong iscomponent secondport ( clk:in std_logic;s1,s0:out std_logic_vector(3 downto 0);co:out std_logic);end component;component minport ( clk:in std_logic;m1,m0:out std_logic_vector(3 downto 0);co:out std_logic);end component;component hourport ( clk:in std_logic;h1,h0:out std_logic_vector(3 downto 0));end component;component mux_21aport ( a,b,sel:in std_logic;y:out std_logic);end component;component mux_21bport ( a,b,sel:in std_logic;y:out std_logic);end component;component div isport(clk3:IN std_logic;clkout1,clkout2:OUT std_logic);end component;component pianxuanPORT( clk: IN std_logic;q: OUT std_logic_vector(2 downto 0)); end component ;component xianshiport(a:in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end component;component seltimeport(disclk:in std_logic_vector(2 downto 0);conv:in std_logic;s0,s1,m0,m1,h0,h1:in std_logic_vector(3 downto 0);dataout:out std_logic_vector(3 downto 0);wsel:out std_logic_vector(3 downto 0);y:out std_logic);end component;signal C,F,I,J,N,Z:std_logic;signal A,B,D,E,G,H,L:std_logic_vector(3 downto 0); signal K,M:std_logic_vector(2 downto 0);beginu1:second port map(clk=>N,s1=>A,s0=>B,co=>C);u2:min port map(clk=>I,m1=>D,m0=>E,co=>F);u3:hour port map(clk=>J,h1=>G,h0=>H);u4:mux_21a port map(a=>C,b=>N,sel=>P,y=>I);u5:mux_21b port map(a=>F,b=>N,sel=>Q,y=>J);u6:div port map(clk3=>O,clkout1=>N,clkout2=>Z);u7:pianxuan port map(clk=>z,q=>K);u8:xianshi port map(a=>L,y=>S);u9:seltime port map(disclk=>K,conv=>R,s0=>B,s1=>A,m0=>E,m1=>D,h0=>H,h1=>G,dataout=>L,wsel=>T,y=>W); end shuzi;。