DDR3 Webmina

– /go/hyperlynxsi
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Click to edit Master title style
Thank You!
Steven McKinney Steven_McKinney@
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ODT Signal leveling
பைடு நூலகம்
No No
Yes Yes
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DDR3 Architecture
• 800 MT/s – 1333 MT/s for 2 DIMM slots Looking at 1066Mbs – Margins will be tight for Slot1 Slot2 1333 MT/s on Read operations • 1600 MT/s only supports 1 DIMM slot 65% 61% – It seems one can not achieve Looking at 1333Mbs reliable data transfer Slot1 Slot2 with 2 slots
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Write Leveling
• • • • Write leveling adjusts the DQS to CK relationship by the controller – Uses a simple feedback provided by the DRAM Memory controller has an adjustable delay setting on DQS – Used to align the rising edge of DQS with the clock at the DRAM pin DRAM asynchronously feeds back CK sampled with the rising edge of DQS The controller repeatedly delays DQS until a transition from 0 to 1 is detected and determines DQS delay
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Termination
• On-Die Termination used for Data/Strobes – Dynamic and controllable as in DDR2 • Address, Command, and Control signals no longer require pull-up terminations on PCB – Termination is on DIMM module • 39 ohm pull-up termination
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Summary
• HyperLynx DDRx wizard can give you complete signal and timing verification of your DDR designs – Easy to use interface – Re-usable setups – Comprehensive results • Special thanks to Micron and Samsung for their contributions to market trend and DDR3 specification information • For additional information visit
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Processing Simulation Data
• Based on the Simulation results
– Comprehensive timing measurements taken on every switching edge • Data to Strobe • Address to Clock • Clock to Strobe • Slew rate detrating – Signal Quality checks made – Results compilation and reporting • All waveform data saved • Spreadsheets created with various levels of pass fail criteria
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HyperLynx Simulation
• Based on the input data and knowing the DDRx standard we..
– Assign stimulus to every driver • Components will drive signals during analysis just as the actual hardware does – Run a comprehensive set SI simulations • Read/Write cycles • Appropriate ODT settings • Use actuate interconnect models included coupling, trace impedances, single and coupled via models
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DDR2/3 Timing Characteristics
• Signal Derating – Adjust setup and hold time based on the input slew rate of the signal • Buy back margin in your system
50%
55%
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Fly-by Architecture
• Address, Control, and Clocks use Fly-by architecture vs. branch architecture for routing – Daisy-chain topology for these signals • Provides improved signal quality – Reduces number of stubs and their length • Requires write leveling to optimize timing – Fly-by creates too much skew between clock and strobe
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DDR3 Timing Characteristics
• Performing signal setup and hold adjustments with JEDEC standard derating tables
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DDR2 and DDR3 Design challenges
• • • • Dynamic ODT selection Source Synchronous relational timing Accounting for Derating Timing analysis with delays accounting for SI effects • Signal quality and Reliability issues • Accounting for Read/Write leveling
Source: Samsung Electronics
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Lead-in vs. Loaded routing
• Neck down traces on DIMM modules to compensate for capacitive loads L Zo = – Increases impedance on traces C – 55 ohms on PCB and 60 ohms on module
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DDR Market Trends
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Lower Power
• Supply voltage reduced from 1.8V to 1.5V – 30% reduction in power supply voltage • Higher impedance driver requires less current – Driver impedance of 34 ohms vs. 18 ohms in DDR2
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DDR Feature Comparison
DDR Data Rate System support Signaling Technology DQS signals
200 - 400 Mbps 4 slots – 8 loads SSTL_2 Bi-directional single ended
Click to edit Master title style Mentor Graphics HyperLynx
Meeting the Challenges of DDRx Design
Steven McKinney Steven_McKinney@
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Agenda
• • • • • • • Market drivers/trends Performance overview Power comparisons Feature comparison Architecture HyperLynx verification solution Demonstration
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How do we automate DDRx analysis?
• Take the following input..
– DDRx bus version and data rate – Identify controller and dram devices – Identify “Net Groups” – Select ODT option to try – Assign default JEDEC compliant timing models – Select simulation settings • Model corners (Min/Typ/Max) • Xtalk • All nets in protocol or subset