FPGA可编程逻辑器件芯片EP2SGX60DF780C4中文规格书
FPGA可编程逻辑器件芯片EP3SL70F780C4中文规格书
•Encrypted transistor and logic cell library models •Encrypted input or output buffer circuit models for single-ended and differential I/O •Single-ended and differential sample SPICE decks •User guide describing the model usageThe HSPICE models provide options to simulate buffer behavior for following I/O feature:•RS OCT with and without calibration •RT OCT with calibration •Internal weak pull-up •Open drain •Bus-hold5.1.20.2. Net Length ReportsThe net length information consists of the package trace delay information from die pad to package pin. Each pin in an FPGA package has its own net length information.This information is important for you to perform board trace compensation to optimize the channel-to-channel skew on your board design.You can obtain the net length reports for Intel Agilex devices from the Board Design Guidelines Solutions Center under Tools, Models, and Libraries .Related InformationBoard Design Guidelines Solution Center: Tools, Models, and Libraries Download center for net length reports for Intel FPGA devices5.2. Intel Agilex LVDS SERDES Design Guidelines5.2.1. Use PLLs in Integer PLL Mode for LVDSEach I/O sub-bank has its own PLL (I/O PLL) to drive the SERDES channels. These I/O PLLs operate in integer mode only.5.2.2. Use High-Speed Clock from PLL to Clock SERDES OnlyThe high-speed clock generated from the PLL is intended to clock the SERDES circuitry only. Do not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted by the PLL F OUT specification.For more information about the F OUT specification, refer to the Intel Agilex Device Data Sheet .5.I/O and LVDS SERDES Design GuidelinesUG-20214 | 2021.04.05Send Feedback5.2.3. Pin Placement for Differential ChannelsEach GPIO sub-bank contains its own PLL. A PLL can drive all receiver and transmitter channels in the same sub-bank. However , the individual PLL cannot drive receiver and transmitter channels in another I/O sub-bank. You must use the dedicated clock pins to drive the LVDS PLLs.The pin index number 0-47 and pin index number 48-95 from device pin out files are respectively assigned to bottom sub-bank and top sub-bank in a single GPIO bank.Refer to External Memory Interface Pin Placement Requirements for more information about the sub-bank arrangement for each I/O bank.PLLs Driving DPA-Enabled Differential Receiver ChannelsFor differential receivers, the PLL can drive all channels in the same I/O sub-bank but cannot drive across banks.Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel Quartus Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.Related InformationExternal Memory Interface Pin Placement Requirements on page 1225.2.4. SERDES Pin Pairs for Soft-CDR ModeYou can use only specific SERDES pin pairs in soft-CDR mode. Refer to the pinout file of each device to determine the SERDES pin pairs that support the soft-CDR mode.5.2.5. Placing LVDS Transmitters and Receivers in the Same I/O BankIf you want to place both LVDS transmitter and receiver interfaces in the same I/O bank, you can use an external PLL.5.2.5.1. Using an External PLL•To use an external PLL, in the LVDS SERDES IP parameter editor , turn on the Use external PLL option.•You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter .•In each instance, you can use up to the following number of channels:—12 transmitters —12 DPA or non-DPA receivers —8 soft-CDR receivers5.I/O and LVDS SERDES Design GuidelinesUG-20214 | 2021.04.05Send Feedback6.Troubleshooting GuidelinesGPIO Debug GuidelinesThe following table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing GPIO systems with Intel Agilex devices. These debug guidelines are just initial debug actions and do not necessarily resolve the failures in your designs.Table 72.GPIO Debug Guidelines Failure SymptomsRecommended Debug Actions 1.2 V LVCMOS output at the entire bank does not reach 1.2V •Check the power-up and power-down sequences of each voltage rail with respect to time.•Compare the power sequences as per recommendation in the Intel Agilex Power Management User Guide.•Verify the VCCIO_PIO voltage signal is 1.2 v.Intel Quartus Prime software shows an error messages to indicate incorrect I/O settings for V CCIO during design compilation.Error message example: Illegal constraint of I/O bank to the location <I/O bank>.•Select the I/O pins specified in the error message and check the I/O settings for the pins.Intel Quartus Prime software shows illegal I/O error message during design compilation.Error message example: Programmable VOD option is set to 1 for pin <pin_name>, but setting is not supported by <I/O standard>.•Select the I/O pins specified in the error message and set the pins to the correct I/O function. Refer to the device pin-outs file for more information about the pin functions.Unable to configure a pin as an open-drain output pin.•Make sure the pin is set to the correct voltage specification per the device data sheet.•To ensure the pin is correctly set to open-drain output,check the compilation report or the resource property editor .Unable to configure a pin to use the bus-hold feature.•Make sure the pin is not set to programmable pull-up resistor . The bus-hold feature is not available when the pin is set to programmable pull-up resistor .High-Speed SERDES I/O Debug GuidelinesThe following table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing high-speed SERDES systems with Intel Agilex devices. These debug guidelines are just initial debug actions and do not necessarily resolve the failures in your designs.UG-20214 | 2021.04.05Send FeedbackISO 9001:2015Registered。
FPGA可编程逻辑器件芯片EP2SGX60EF1152C5中文规格书
Introduction●8B/10B encoder and decoder perform 8-bit to 10-bit encodingand 10-bit to 8-bit decoding●Phase compensation FIFO buffer performs clock domaintranslation between the transceiver block and the logic array●Receiver FIFO resynchronizes the received data with the localreference clock●Channel aligner compliant with XAUIf Certain transceiver blocks can be bypassed. Refer to the Stratix II GXArchitecture chapter in volume 1 of the Stratix II GX Device Handbook formore details.Table1–1 lists the Stratix II GX device features.Table1–1.Stratix II GX Device Features (Part 1 of2)Feature EP2SGX30C/D EP2SGX60C/D/E EP2SGX90E/F EP2SGX130/G C D C D E E F GALMs13,55224,17636,38453,016 Equivalent LEs33,88060,44090,960132,540 Transceiverchannels484812121620Transceiver data rate600 Mbps to6.375Gbps 600 Mbps to 6.375Gbps600 Mbps to6.375 Gbps600 Mbps to6.375 GbpsSource-synchronousreceive channels (1)31313142475973Source-synchronoustransmit channels29292942455971M512 RAM blocks(32×18bits)202329488699M4K RAM blocks(128×36bits)144255408609M-RAM blocks(4K×144 bits)1246 Total RAM bits1,369,7282,544,1924,520,4486,747,840 Embeddedmultipliers (18×18)64144192252 DSP blocks16364863 PLLs444888 Maximum user I/Opins361364364534558650734This module detects word boundaries for the 8B/10B-based protocols, SONET, 16-bit, and 20-bit proprietary protocols. This module is also used to align to specific programmable patterns in PRBS7/23 test mode. Pattern DetectionThe programmable pattern detection logic can be programmed to align word boundaries using a single 7-, 8-, 10-, 16-, 20, or 32-bit pattern. The pattern detector can either do an exact match, or match the exact pattern and the complement of a given pattern. Once the programmed pattern is found, the data stream is aligned to have the pattern on the LSB portion of the data output bus.XAUI, GIGE, PCI Express, and Serial RapidIO standards have embedded state machines for symbol boundary synchronization. These standards use K28.5 as their 10-bit programmed comma pattern. Each of these standards uses different algorithms before signaling symbol boundary acquisition to the FPGA.The pattern detection logic searches from the LSB to the most significant bit (MSB). If multiple patterns are found within the search window, the pattern in the lower portion of the data stream (corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored.Once a pattern is detected and the data bus is aligned, the word boundary is locked. The two detection status signals (rx_syncstatus andrx_patterndetect) indicate that an alignment is complete.Figure2–18 is a block diagram of the word aligner.Figure2–18.Word AlignerAdaptive Logic ModulesFigure2–44.Example of a 3-Bit Add Utilizing Shared Arithmetic ModeShared Arithmetic ChainIn addition to the dedicated carry chain routing, the shared arithmeticchain available in shared arithmetic mode allows the ALM to implementa three-input add, which significantly reduces the resources necessary toimplement large adder trees or correlator functions. The sharedarithmetic chains can begin in either the first or fifth ALM in a LAB. TheQuartus II Compiler automatically links LABs to create shared arithmeticchains longer than 16 (8ALMs in arithmetic or shared arithmetic mode).For enhanced fitting, a long shared arithmetic chain runs vertically。
FPGA可编程逻辑器件芯片EP1S20F780C5中文规格书
dataa datab datac datad
Six-Input LUT
(Function0)
datae1 dataf1
Six-Input LUT
(Function1)
combout0 combout1
In a sparsely used device, functions that could be placed into one ALM may be implemented in separate ALMs. The Quartus II Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically utilizes the full potential of the Stratix II ALM. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments.
FPGA可编程逻辑器件芯片EP3SE260H780C4N中文规格书
Tables 4–98 through 4–105 show the maximum DCD in absolutionderivation for different I/O standards on Stratix II GX devices. Examplesare also provided that show how to calculate DCD as a percentage.Here is an example for calculating the DCD as a percentage for anon-DDIO output on a row I/O on a -3 device:If the non-DDIO output I/O standard is SSTL-2 Class II, the maximumDCD is 95ps (see Table 4–99). If the clock frequency is 267MHz, the clockperiod T is:T = 1/ f = 1 / 267MHz = 3.745ns = 3,745psTo calculate the DCD as a percentage:(T/2 – DCD) / T = (3,745ps/2 – 95ps) / 3,745ps = 47.5% (for lowboundary)(T/2 + DCD) / T = (3,745ps/2 + 95ps) / 3,745ps = 52.5% (for highboundary)Table 4–98.Maximum DCD for Non-DDIO Output on Row I/O PinsRow I/O Output StandardMaximum DCD (ps) for Non-DDIO Output -3 Devices -4 and -5 Devices Unit 3.3-V LVTTTL245275ps 3.3-V LVCMOS125155ps 2.5 V105135ps 1.8 V180180ps 1.5-V LVCMOS165195ps SSTL-2 Class I115145ps SSTL-2 Class II95125ps SSTL-18 Class I5585ps 1.8-V HSTL Class I80100ps 1.5-V HSTL Class I85115ps LVDS 5580psTable4–100.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices Note(1)Maximum DCD (ps) for Row DDIO Output I/OStandardInput I/O Standard (No PLL in Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL LVDS3.3 and2.5 V1.8 and1.5 V2.5 V1.8 and1.5 V3.3 V3.3-V LVTTL260380145145110ps 3.3-V LVCMOS21033010010065ps 2.5 V195315858575ps 1.8 V1502658585120ps 1.5-V LVCMOS255370140140105ps SSTL-2 Class I175295656570ps SSTL-2 Class II170290606075ps SSTL-18 Class I155275555090ps 1.8-V HSTL Class I150270606095ps 1.5-V HSTL Class I150270555590ps LVDS180180180180180psTherefore, the DCD percentage for the output clock is from 48.4% to51.6%.Table4–101.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note(1)Maximum DCD (ps) for Row DDIO Output I/OStandardInput I/O Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL LVDS3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3V3.3-V LVTTL440495170160105ps 3.3-V LVCMOS39045012011075ps 2.5 V3754301059590ps 1.8 V32538590100135ps 1.5-V LVCMOS430490160155100ps SSTL-2 Class I355410857585ps SSTL-2 Class II350405807090ps SSTL-18 Class I3353906565105ps 1.8-V HSTL Class I3303856070110ps 1.5-V HSTL Class I3303906070105ps LVDS180180180180180ps(1)Table4–101 assumes the input clock has zero DCD.Table4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 1 of2)Note(1)Maximum DCD (ps) for DDIO Column Output I/OStandardInput IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL HSTL123.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 1.2V3.3-V LVTTL260380145145145ps 3.3-V LVCMOS210330100100100ps 2.5 V195315858585ps 1.8 V150265858585ps 1.5-V LVCMOS255370140140140ps SSTL-2 Class I175295656565ps SSTL-2 Class II170290606060ps SSTL-18 Class I155275555050psSSTL-18 Class II140260707070ps 1.8-V HSTL Class I150270606060ps 1.8-V HSTL Class II150270606060ps 1.5-V HSTL Class I150270555555ps 1.5-V HSTL Class II125240858585ps 1.2-V HSTL240360155155155ps LVPECL 180180180180180ps(1)Table 4–102 assumes the input clock has zero DCD.Table 4–103.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note (1)Maximum DCD (ps) forDDIO Column Output I/OStandardInput IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL 3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3-V LVTTL440495170160ps 3.3-V LVCMOS390450120110ps 2.5 V37543010595ps 1.8 V32538590100ps 1.5-V LVCMOS430490160155ps SSTL-2 Class I3554108575ps SSTL-2 Class II3504058070ps SSTL-18 Class I3353906565ps SSTL-18 Class II3203757080ps 1.8-V HSTL Class I3303856070ps 1.8-V HSTL Class II3303856070ps 1.5-V HSTL Class I3303906070ps 1.5-V HSTL Class II33036090100ps LVPECL180180180180ps (1)Table 4–103 assumes the input clock has zero DCD.Table 4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 2 of 2) Note (1)Maximum DCD (ps) forDDIO Column Output I/OStandardInput IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL HSTL123.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 1.2V。
FPGA可编程逻辑器件芯片EP2SGX60DF780C5中文规格书
PLL SpecificationsPLLSpecificationsf See the DC & Switching Characteristics chapter in volume 1 of theStratix II GX Device Handbook (or the Stratix II Device Handbook) forinformation about PLL timing specificationsClocking Stratix II and Stratix II GX devices provide a hierarchical clock structureand multiple PLLs with advanced features. The large number of clockingresources in combination with the clock synthesis precision provided byenhanced and fast PLLs provides a complete clock-management solution.Global and Hierarchical ClockingStratix II and Stratix II GX devices provide 16 dedicated global clocknetworks and 32 regional clock networks. These clocks are organized intoa hierarchical clock structure that allows for 24 unique clock sources perdevice quadrant with low skew and delay. This hierarchical clockingscheme provides up to 48 unique clock domains within the entireStratix II or Stratix II GX device. Table1–17 lists the clock resourcesavailable on Stratix II devices.There are 16 dedicated clock pins (CLK[15..0]) on Stratix II andStratix II GX devices to drive either the global or regional clock networks.Four clock pins drive each side of the Stratix II device, as shown inFigures1–39and 1–40. Enhanced and fast PLL outputs can also drive theglobal and regional clock networks.Table1–17.Clock Resource Availability in Stratix II and Stratix II GX Devices(Part 1 of2)Description Stratix II Device Availability Stratix II GX Device Availability Number of clock input pins24 12Number of global clock networks1616Number of regional clocknetworks3232Global clock input sources Clock input pins, PLL outputs, logicarray Clock input pins, PLL outputs, logic array, inter-transceiver clocksRegional clock input sources Clock input pins, PLL outputs, logicarray Clock input pins, PLL outputs, logic array, inter-transceiver clocksNumber of unique clock sources in a quadrant 24 (16 global clocks and 8 regionalclocks)24 (16 GCLK and 8 RCLK clocks)Number of unique clock sources in the entire device 48 (16 global clocks and 32 regionalclocks)48 (16 GCLK and 32 RCLK clocks)ClockingTables1–20 and 1–21 show which PLLs are available in each Stratix II andStratix II GX device, respectively, and which input clock pin drives whichPLLs.Table1–20.Stratix II Device PLLs and PLL Clock Pin Drivers(Part 1 of2)Input PinAll Devices EP2S60 to EP2S180 Devices Fast PLLsEnhancedPLLsFast PLLsEnhancedPLLs 123456789101112CLK0v v v(1)v (1)CLK1(2)v v v(1)v (1)CLK2v v v(1)v (1)CLK3(2)v v v(1)v (1)CLK4v v CLK5v v CLK6v v CLK7v v CLK8v v v(1)v (1)CLK9 (2)v v v(1)v (1)CLK10v v v(1)v (1)CLK11 (2)v v v(1)v (1)CLK12v vCLK13v vCLK14v vCLK15v vPLL5_FB vPLL6_FB vPLL11_FB vPLL12_FB v PLL_ENA v v v v v v v v v v v v FPLL7CLK(2)vFPLL8CLK(2)vFPLL9CLK(2)vDocument Revision HistoryContents Stratix II Device Handbook, Volume2ClockingTables1–23 and 1–24 show the global and regional clocks that the PLLoutputs drive.Table1–23.Stratix II Global and Regional Clock Outputs From PLLs(Part 1 of3)Clock NetworkPLL Number and TypeEP2S15 through EP2S30 Devices EP2S60 through EP2S180 Devices Fast PLLsEnhancedPLLsFast PLLsEnhancedPLLs 123456789101112GCLK0v v v vGCLK1v v v vGCLK2v v v vGCLK3v v v vGCLK4v v GCLK5v v GCLK6v v GCLK7v v GCLK8v v v vGCLK9v v v vGCLK10v v v vGCLK11v v v vGCLK12v vGCLK13v vGCLK14v vGCLK15v vRCLK0v v vRCLK1v v vRCLK2v v vRCLK3v v vRCLK4v v vRCLK5v v vRCLK6v v vRCLK7v v vRCLK8v v RCLK9v v。
FPGA可编程逻辑器件芯片EP3SL50F780C4N中文规格书
Stratix III Device Handbook, Volume 2Electrical CharacteristicsThis chapter describes the electrical characteristics, switching characteristics, and I/O timing for Stratix ®III devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include core performance specifications and periphery performance. A glossary is also included for your reference.Operating ConditionsWhen Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Stratix III devices, system designers must consider the operating requirements described in this chapter.Stratix III devices are offered in both commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4, and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speed grades.1In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with a “C” prefix and industrial with an “I” prefix. For example, commercial devices are indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.Absolute Maximum RatingsAbsolute maximum ratings define the maximum operating conditions for Stratix III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functionaloperation of the device is not implied at these conditions. Conditions beyond those listed in Table 1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.Table 1–1.Absolute Maximum Ratings for Stratix III Devices (Note 1)(Part 1 of 2)SymbolParameterMinimum Maximum Unit V CCL Selectable core voltage power supply -0.5 1.65V V CC I/O registers power supply-0.5 1.65V V CCD_PLL Phase-locked loop (PLL) digital power supply -0.5 1.65V V CCA_PLL PLL analog power supply-0.5 3.75V V CCPT Programmable power technology power supply -0.5 3.75V V CCPGM Configuration pins power supply -0.5 3.9V V CCPD I/O pre-driver power supply -0.5 3.9V V CCIOI/O power supply-0.53.9VSIII52001-2.3Chapter 1:Stratix III Device Datasheet: DC and Switching CharacteristicsElectrical CharacteristicsStratix III Device Handbook, Volume 2V CC_CLKIN Differential clock input power supply (top and bottom I/O banks only)-0.5 3.75V V CCBAT Battery back-up power supply for design security volatile key register -0.5 3.75V V I DC Input voltage-0.5 4.0V T J Operating junction temperature -55125°C I OUT DC output current, per pin -2540mA T STGStorage temperature (No bias)-65150°CTable 1–1.Absolute Maximum Ratings for Stratix III Devices (Note 1)(Part 2 of 2)Symbol ParameterMinimum Maximum UnitChapter 1:Stratix III Device Datasheet: DC and Switching Characteristics Electrical CharacteristicsStratix III Device Handbook, Volume 2Table 1–2.Maximum Allowed Overshoot During TransitionsSymbolParameterConditionOvershoot Duration as a % ofHigh TimeUnit Vi (AC)AC Input Voltage (1)4100.000%4.0579.330%4.146.270%4.1527.030%4.215.800%4.259.240%4.3 5.410%4.353.160%4.4 1.850%4.45 1.080%4.50.630%4.550.370%4.60.220%4.650.130%4.70.074%4.750.043%4.80.025%4.850.015%Chapter 1:Stratix III Device Datasheet: DC and Switching CharacteristicsElectrical CharacteristicsStratix III Device Handbook, Volume 2V CCPGMConfiguration pins power supply, 3.3 V— 3.135 3.3 3.465V Configuration pins power supply, 3.0 V — 2.853 3.15V Configuration pins power supply, 2.5 V — 2.375 2.5 2.625V Configuration pins power supply, 1.8 V — 1.71 1.8 1.89V V CCPD (1)I/O pre-driver power supply, 3.3 V— 3.135 3.3 3.465V I/O pre-driver power supply, 3.0 V — 2.85 3 3.15V I/O pre-driver power supply, 2.5 V — 2.375 2.5 2.625V V CCIOI/O power supply, 3.3 V — 3.135 3.3 3.465V I/O power supply, 3.0 V— 2.85 3 3.15V I/O power supply, 2.5 V — 2.375 2.5 2.625V I/O power supply, 1.8 V — 1.71 1.8 1.89V I/O power supply, 1.5 V — 1.425 1.5 1.575V I/O power supply, 1.2 V— 1.14 1.2 1.26V V CC_CLKIN Differential clock input power supply (top and bottom I/O banks only)— 2.375 2.5 2.625V V CCBAT (3)Battery back-up power supply for design security volatile key register — 1.0— 3.3V V I DC Input voltage —-0.3— 3.6V V OOutput voltage—0—V CCIO V T J Operating junction temperatureFor commercialuse 0—85°C For industrial use (2)-40—100°C t RAMPPower Supply Ramptime (For V CCPT )Normal POR (PORSEL=0)50 µs — 5 ms —Fast POR (PORSEL=1)50 µs — 5 ms —Power Supply Ramptime (For all power supplies except V CCPT )Normal POR (PORSEL=0)50 µs —100 ms —Fast POR (PORSEL=1)50 µs—12 ms—Notes to Table 1–3:(1)V CCPD is 2.5, 3.0, or 3.3V. For a 3.3-V I/O standard, V CCPD =3.3 V. For a 3.0-V I/O standard, V CCPD = 3.0 V. For a 2.5-V or lower I/O standard,V CCPD =2.5V.(2)For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0° C to100° C, regardless of supply voltage.(3)Altera recommends a 3.0-V nominal battery voltage when connecting V CCBAT to a battery for volatile key backup. If you do not use the volatilesecurity key, you may connect the V CCBAT to either GND or a 3.0-V power supply.Table 1–3.Recommended Operating Conditions for Stratix III Devices (Part 2 of 2)SymbolParameterConditionsMinimum Typical Maximum UnitChapter 1:Stratix III Device Datasheet: DC and Switching Characteristics Electrical CharacteristicsStratix III Device Handbook, Volume 2Parameter Symbol Conditions V CCIOUnit1.2V 1.5V 1.8V2.5V3.0V/3.3V MinMaxMinMaxMinMaxMinMaxMinMaxLow sustaining current I SUSL V IN >V IL (maximum)22.5 —25.0 —30.0 —50.0 —70.0 —µA High sustaining current I SUSH V IN <V IH (minimum)-22.5 —-25.0 —-30.0 —-50.0 —-70.0 —µA Low overdrive currentI ODL0V <V IN <V CCIO—120—160—200—300—500µA。
FPGA可编程逻辑器件芯片EP2S60F1020C4中文规格书
Table 4–96 shows the maximum output clock toggle rate for Stratix II GXdevice series-terminated dedicated clock pins.SSTL-2 Class IOCT_50_OHMS 600 500 500 MHz SSTL-2 Class IIOCT_25_OHMS 600 550 500 MHz SSTL-18 Class I OCT_50_OHMS 590 400 350 MHz 1.5-V HSTLClass IOCT_50_OHMS 600 550 500 MHz 1.8-V HSTLClass IOCT_50_OHMS 650 600 600 MHz DifferentialSSTL-2 Class IOCT_50_OHMS 600 500 500 MHz DifferentialSSTL-2 Class II OCT_25_OHMS 600550 500 MHz Differential SSTL-18 Class I OCT_50_OHMS 590400 350 MHz Differential HSTL-18 Class I OCT_50_OHMS 650600600MHz Differential HSTL-15 Class IOCT_50_OHMS600550500Table 4–95.Stratix II GX Maximum Output Clock Rate for Row Pins (Series Termination)(Part 2 of 2)I/O StandardDrive Strength -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit Table 4–96.Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Series Termination)(Part 1 of 2)I/O StandardDrive Strength -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit LVTTLOCT_25_OHMS 400 400 350 MHz OCT_50_OHMS 400 400 350 MHz LVCMOSOCT_25_OHMS 350 350 300 MHz OCT_50_OHMS 350 350 300 MHz 2.5 VOCT_25_OHMS 350 350 300 MHz OCT_50_OHMS 350 350 300 MHz 1.8 VOCT_25_OHMS 700 550 450 MHz OCT_50_OHMS 700 550 450 MHz 1.5 VOCT_50_OHMS 550 450 400 MHz SSTL-2 Class IOCT_50_OHMS 600 500 500 MHz SSTL-2 Class II OCT_25_OHMS 600550 500 MHz SSTL-18 Class I OCT_50_OHMS450 400 350 MHzSSTL-18 Class II 8mA173206206---155********mA150160160---14016016018mA120130130---11013013020mA109127127---941271272.5-V SSTL-2Class I8mA 36468068036468068035068068012mA 1632072071632072071882072072.5-V SSTL-2Class II 16mA 1181471471181471479414714720mA 99122122---8712212224mA 91116116---851161161.8-V SSTL-18 Class I 4mA 4585705704585705705055705706mA 3053803803053803803363803808mA 22528228222528228224828228210mA 16722022016722022019022022012mA 129175175---1481751751.8-V SSTL-18 Class II 8mA 173206206---155********mA 150160160---14016016018mA 120130130---11013013020mA 109127127---941271271.8-V HSTL Class I 4mA 2452822822452822822292822826mA 1641881881641881881531881888mA 12314014012314014011414014010mA 11012412411012412410812412412mA 97110110971101101041101101.8-V HSTL Class II 16mA 101104104---9910410418mA 98102102---9310210220mA 939999---8899991.5-V HSTL Class I 4mA 1681961961681961961881961966mA 1121311311121311311251311318mA 84999984999995999910mA 879898---90989812mA 869898---879898Table 4–97.Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 5)I/O Standard DriveStrength Maximum Output Clock Toggle Rate Derating Factors (ps/pF)Column I/O PinsRow I/O Pins Dedicated Clock Outputs -3-4-5-3-4-5-3-4-51.5-V HSTL Class II 16mA 95101101---96101101 18mA 95100100---101100100 20mA 94101101---1041011012.5-V differential SSTL Class II (3)8mA 364680680---350680680 12mA 163207207---188207207 16mA 118147147---94147147 20mA 99122122---87122122 24mA91116116---851161161.8-V differential SSTL Class I (3)4mA 458570570---505570570 6mA 305380380---336380380 8mA 225282282---248282282 10mA 167220220---190220220 12mA 129175175---1481751751.8-V differential SSTL Class II (3)8mA 173206206---155206206 16mA 150160160---140160160 18mA 120130130---110130130 20mA 109127127---941271271.8-V differential HSTL Class I (3)4mA 245282282---229282282 6mA 164188188---153188188 8mA 123140140---114140140 10mA 110124124---108124124 12mA 97110110---1041101101.8-V differential HSTL Class II (3)16mA 101104104---99104104 18mA 98102102---93102102 20mA 939999---8899991.5-V differential HSTL Class I (3)4mA 168196196---188196196 6mA 112131131---125131131 8mA 849999---959999 10mA 879898---909898 12mA 869898---879898Table4–97.Maximum Output Clock Toggle Rate Derating Factors (Part 4 of5)I/O StandardDriveStrengthMaximum Output Clock Toggle Rate Derating Factors (ps/pF) Column I/O Pins Row I/O PinsDedicated ClockOutputs -3-4-5-3-4-5-3-4-5。
FPGA可编程逻辑器件芯片EP2S60F484I4中文规格书
Tables 5–77 through 5–79 show the I/O toggle rates for Stratix II devices.
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Parameter
tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T
Minimum Timing Industrial Commercial
-3 Speed Grade (1)
-3 Speed Grade (2)
-4 Speed Grade
-5 Speed Grade
Column I/O Pins (MHz) Row I/O Pins (MHz)
-3 -4
-5
-3 -4
-5
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
Input I/O Standard
LVTTL 2.5-V LVTTL/CMOS 1.8-V LVTTL/CMOS 1.5-V LVTTL/CMOS LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I
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MultiTrack InterconnectC16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can crossM-RAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar toLAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has localinterconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks,labclk[5..0].Table 2–18 shows the Stratix II GX device’s routing scheme.Table 2–18. Stratix II GX Device Routing Scheme (Part 1 of 2)SourceDestinationS h a r e d A r i t h m e t i c C h a i nC a r r y C h a i nR e g i s t e r C h a i nL o c a l I n t e r c o n n e c tD i r e c t L i n k I n t e r c o n n e c t R 4 I n t e r c o n n e c tR 24 I n t e r c o n n e c tC 4 I n t e r c o n n e c tC 16 I n t e r c o n n e c tA L MM 512 R A M B l o c kM 4K R A M B l o c kM -R A M B l o c kD S P B l o c k sC o l u m n I O ER o w I O EShared arithmetic chain v Carry chain v Register chain vLocal interconnect v v v v v v vDirect link interconnect v R4 interconnect v v v v v R24 interconnect v v v v C4 interconnect vvv C16 interconnect v v v vALMv v v v v vv M512 RAM block v v v v M4K RAM block v v vv M-RAM block v v v vDSP blocksv vvStratix II GX ArchitectureTriMatrix MemoryTriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2–19 shows the size and features of the different RAM blocks.Column IOE v v vRow IOEv v v vTable 2–18. Stratix II GX Device Routing Scheme (Part 2 of 2)SourceDestinationS h a r e d A r i t h m e t i c C h a i nC a r r y C h a i nR e g i s t e r C h a i nL o c a l I n t e r c o n n e c tD i r e c t L i n k I n t e r c o n n e c t R 4 I n t e r c o n n e c tR 24 I n t e r c o n n e c tC 4 I n t e r c o n n e c tC 16 I n t e r c o n n e c tA L MM 512 R A M B l o c kM 4K R A M B l o c kM -R A M B l o c kD S P B l o c k sC o l u m n I O ER o w I O ETable 2–19.TriMatrix Memory Features (Part 1 of 2)Memory FeatureM512 RAM Block (32×18 Bits)M4K RAM Block (128×36 Bits)M-RAM Block (4K ×144Bits)Maximum performance 500 MHz550 MHz420 MHzT rue dual-port memory vv Simple dual-port memory v v v Single-port memory v v vShift register v v ROM v v (1)FIFO buffer v v v Pack mode v v Byte enablev v v Address clock enable v v Parity bits v v v Mixed clock mode v v vMemory initialization (.mif )vvTriMatrix MemorySimilar to all RAM blocks, M-RAM blocks can have different clocks ontheir inputs and outputs. Either of the two clocks feeding the block canclock M-RAM block registers (renwe, address, byte enable, datain,and output registers). The output register can be bypassed. The sixlabclk signals or local interconnect can drive the control signals for theA andB ports of the M-RAM block. ALMs can also control the clock_a,clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, andclocken_b signals, as shown in Figure2–53.Figure2–53.M-RAM Block Control SignalsThe R4, R24, C4, and direct link interconnects from adjacent LABs oneither the right or left side drive the M-RAM block local interconnect. Upto 16 direct link input connections to the M-RAM block are possible fromthe left adjacent LABs and another 16 possible from the right adjacentLAB. M-RAM block outputs can also connect to left and right LABsthrough direct link interconnect. Figure2–54 shows an example floorplanfor the EP2SGX130 device and the location of the M-RAM interfaces.Figures2–55 and 2–56 show the interface between the M-RAM block andthe logic array.PLLs and Clock NetworksStratix II GX Architecture。