5,6 MOSFET

MOSFET
• What does a MOSFET look like and how does it work? • How does lateral transport through the inversion layer take place? • What are the DC I-V characteristics of a MOSFET? • What are the common MOSFET geometry variations?
4 terminal MOS structure: MOSFET
Cross-section
plan
Mode of operation (enhancement mode, normally off)
i.e. no drain current when the gate voltage VGS = 0
tox
Key design parameters are:
– – – – Gate length (~electrical channel length) Gate dielectric (usually oxide) thickness, tox Source/drain junction depth, xj Doping in the body, NA
kT – Close to threshold, VGS-V(y)-Vt ~ q →Diffusion current significant At pinch-off and in subthreshold
I-V characteristic
in strong inversion Qi(y) = -Cox (VGS - V(y) - Vt) So that
Example: Estimate the cut-off frequency, ft , and mobility, , for an n-channel MOSFET designed to operate at 2.5 V.
Answer: nMOS faster than pMOS, so chose gm/W = 320 mS/mm
Transistor evolution
Transistor Delay Time This can be estimated from the time taken for one transistor to supply sufficient current to charge up the gate of a second.
3.3 V
2.5 V
3.3 V
2.5 V
tox
L
7 nm
0.41 m
6 nm
0.33 m
7 nm
0.37 m
6 nm
0.33 m
gm
S
230mS/mm 320 mS/mm
80 mV/dec 80 mV/dec
150 mS/mm
80 mV/dec
180 mS/mm
80 mV/dec
Which column represents data for an n-channel MOSFET designed to operate at 2.5 V?
Mode of operation (enhancement mode, normally off)
i.e. no drain current when the gate voltage VDS = 0 3) For higher drain voltages, VDS, the channel between the pinch-off point and the drain has a high resistance and so the drain current remains constant (saturation regime). There is just sufficient channel beyond pinch-off to allow the saturation current to flow. 4) The minimum gate voltage, VGS, at which a channel current can be sustained is called the threshold voltage, Vt. Thus pinch-off will begin when VGS and VDS differ by Vt: VDSsat = VGS - Vt
Drift-diffusion equations: Inversion charge,
dn( y ) J e q e n( y ) E y ( y ) qDe dy
Qi(y) = -Cox (VGS - V(y) - Vt) = -qn(y) dQi ( y ) dV ( y ) dn( y ) Cox q -Ey dy dy dy
W 1 I D eCox VGS VDS Vt VDS L 2
Valid in strong inversion, VDS<VGS-Vt
When VDS VGS – Vt → ID saturation (i.e. constant as VDS ↑)
I Dsat I D (VDS
Id T1 C GS Cs g T2
Q = It, Q = CV → t GS I gm CGS = Cox WL is the gate capacitance But the charging time is the inverse of the (angular) frequency:
CV
0
GS
V ( y ) Vt dV ( y )
Je
eCox
L
1 VGS VDS Vt VDS 2
Terminal drain current:
W 1 I D eCox VGS VDS Vt VDS L 2
I-V characteristic
8.85 1012 4 Cox 5.9 103 Fm 2 6 109
1 gm ft 2t 2C gs gm 2C oxWL
WCox gm (VGS Vt ) L g 1 4L Vt VGS m 4 W Cox 3VGS 4 0.33 10 6 320 5.9 10 3 3 2.5 9.6 10 3 m 2 / Vs 96cm 2 / Vs
q Since D kT
then
dV ( y ) kT J e e Qi ( y ) Cox q dy
Relative contribution of drift versus diffusion Qi(y) vs kT C ox q Two cases: kT – Strong inversion, VGS-V(y)-Vt >> q →Drift current dominates
0V VGS=3V VDS=0.01V
1)When a gate voltage of 3 V is applied, an inversion layer exists along the channel and current flows (linear regime).
e Qi ( y )
dV ( y ) dy
dV ( y ) J e eCox VGS V ( y ) Vt dy
Integrate over channel J e dy eCox (separate variables V, y) 0

L
VDS
V
dI D WCox gd (VGS Vt ) dVDS L
If VDS<<VGS-Vt
Power MOSFET
• A vertical MOSFET structure is used for high power applications. Large voltages can be dropped vertically through the Si wafer.
SOI MOSFET
gate s channel d
Buried Oxide (BOX)
• Replace Si substrate by insulating layer (oxide) • Reduces source/drain capacitance • Improves short channel effects lower doping
dI D WCox gd (VGS Vt ) dVDS L
If VDS<<VGS-Vt
I-V characteristic
=Vt
dI D WCox (VGS Vt ) (Saturation regime) Transconductance, g m dVGS L
Channel conductance,
0V
VGS=3V
VDS=2.5V
I-V characteristic
Energy Bands, EF
Depletion Regions
Inversion layer current depends on:
– Lateral field across inversion layer (~ source-drain voltage) – Electron concentration in inversion layer (~ gate-source voltage)
1. 2. 3. 4.
Column One ColumnTwo Column Three Column Four
What is the gate capacitance/unit area COX for this device?