K4D623238B-GC60中文资料

• 2.5V + 5% power supply for device operation • VDD/VDDQ = 2.8V ± 5% for -33 • VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40 • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs -. Read latency 3,4,5 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave) • Full page burst length for sequential burst type only • Start address of the full page burst should be even • All inputs except data & DM are sampled at the positive going edge of the system clock • Differential clock input • No Wrtie-Interrupted by Read Function • 4 DQS’s ( 1DQS / Byte )
64M DDR SDRAM
3
DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC
4
VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0
5
DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0
Revision 1.2 (September 1, 2001)
• Added K4D623238B-GL* as a low power part (ICC6=1mA) • Added ICC7 (Operating current at 4bank interleaving) • Added 100MHz@CL2
12
DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CK CKE
13
DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC MCL VREF
VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS A10 A2 A1ision 1.1 (August 2, 2001)
• Changed tCK(max) of K4D623238B-GC45/-50/-55/-60 from 7ns to 10ns.
Revision 1.0 (June 22, 2001)
• Changed VDD/VDDQ of K4D623238B-GC33 from 2.5V to 2.8V.
Revision 1.4 September 2002
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.4 (Sep. 2002)
元器件交易网
Revision 0.3 (February 10, 2001) - Preliminary
• Changed tDAL of K4D623238B-GC45 from 6tCK to 7tCK.
Revision 0.2 (December 13, 2000) - Target Spec
• Defined Target Specification
- 4 -
Rev. 1.4 (Sep. 2002)
元器件交易网
K4D623238B-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol Type Function The differential system clock Input. CK, CK*1 Input
64M DDR SDRAM
All of the inputs are sampled on the rising edge of the clock except D Q’s and DM ’ that are sampled on both edges of the DQS. s Activates the CK signal when high and deactivates the CK signal
Revision 0.4 (April 10,2001) - Preliminary Spec
• Added K4D623238B-GC50 • Added K4D623238B-GC55 • Added K4D623238B-GC60 • Defined tWR_A that means write recovery time @ Auto precharge.
- 3 -
Rev. 1.4 (Sep. 2002)
元器件交易网
K4D623238B-GC
PIN CONFIGURATION (Top View)
2 B C D E F G H J K L M N
DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS
ORDERING INFORMATION
Part NO. K4D623238B-GC/L33 K4D623238B-GC/L40 K4D623238B-GC/L45 K4D623238B-GC/L50 K4D623238B-GC/L55 K4D623238B-GC/L60 Max Freq. 300MHz 250MHz 222MHz 200MHz 183MHz 166MHz Max Data Rate 600Mbps/pin 500Mbps/pin 444Mbps/pin 400Mbps/pin 366Mbps/pin 333Mbps/pin SSTL_2 144-Ball FBGA Interface Package
PIN DESCRIPTION
CK,CK CKE CS RAS CAS WE DQS DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA 0 , BA 1 A 0 ~A 10 D Q0 ~ DQ3 1 V DD VS S V DDQ V SSQ NC MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQ’ s Ground for DQ’ s No Connection Must Connect Low
6
DQ2 DQ1 VSSQ VSSQ
7
DQ0 VDDQ VDD VSS
8
DQ31 VDDQ VDD VSS
9
DQ29 DQ30 VSSQ VSSQ
10
DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS RFU 2 A7
11
VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CK A8/AP
Revision 0.0 (November 21, 2000)
- 2 -
Rev. 1.4 (Sep. 2002)
元器件交易网
K4D623238B-GC
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL FEATURES
64M DDR SDRAM
• Data I/O transactions on both edges of Data strobe • DLL aligns DQ and DQS transitions with Clock transition • Edge aligned data & data strobe output • Center aligned data & data strobe input • DM for write masking only • Auto & Self refresh • 16ms refresh period (2K cycle) • 144-Ball FBGA • Maximum clock frequency up to 300MHz • Maximum data rate up to 600Mbps/pin
GENERAL DESCRIPTION
FOR 512K x 32Bit x 4 Bank DDR SDRAM
The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32 bits, fabricated with SAMSUNG ’ high performance CMOS technology. Synchronous features with Data Strobe allow s extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.