LDPC decoding
多电平闪存信道下阈值电压高效检测算法

多电平闪存信道下阈值电压高效检测算法范正勤; 韩国军【期刊名称】《《应用科技》》【年(卷),期】2019(046)005【总页数】6页(P57-62)【关键词】阈值电压检测; NAND闪存; 重读机制; 原始误码率; 电压重叠区; 读电压优化; 读时延; 数据存储【作者】范正勤; 韩国军【作者单位】广东工业大学信息工程学院广东广州 510000【正文语种】中文【中图分类】TN919.5随着半导体制程工艺的进一步缩小、多电平存储技术的使用,存储单元成本大幅下降,NAND固态数据存储已广泛应用于各种消费类电子产品及部分数据中心。
对于NAND闪存器件,存储密度提升的同时,存储单元受到的噪声干扰进一步加剧,导致数据存储可靠性降低[1]。
一般数据存储误码率要求必须低于10-15。
相较于使用硬判决译码方法的Bose-Chaudhuri-Hocquenghem (BCH)纠错码,低密度奇偶校验(low-density parity-check,LDPC)纠错码使用软判决译码方法,能极大地降低误码率[2]。
多种噪声引起阈值电压偏移而产生误读数据,单元间干扰[3]和持久性噪声[4]是制约NAND闪存数据存储可靠性的主要噪声。
目前,为了补偿噪声对阈值电压的影响,闪存采用重读机制[5-8]。
动态优化读参考电压[7-11]以适应阈值电压的偏移,采用优化的读参考电压可以获得最低的原始误码率,从而达到改善存储可靠性的目的。
在读电压检测范围内,Cai等[7]提出等间隔降低读参考电压操作,该方案可以降低阈值电压检测的范围。
针对阈值电压检测时读操作带来的时延问题,通过对重叠区的原始误码率分析,本文提出了非均匀迭代更新读电压优化方案,该方案有效地降低了读操作的次数。
1 阈值电压检测1.1 系统模型数据闪存系统模型如图1所示,数据经过LDPC编码后通过编程和擦除操作写入闪存单元;经过信道噪声干扰后(单元间干扰和持久性噪声),单元阈值电压产生偏移造成数据误读,需要进行信道检测优化;读操作得到单元对应的对数似然比信息,再通过LDPC译码算法进行纠错处理[1-2,12]。
ldpc码基本原理

ldpc码基本原理
LDPC码(Low Density Parity Check Code),又称低密度奇偶校验码,是一种现代编码技术,被广泛应用于许多领域,如移动通信、数据存储和广播,以提高数据传输的稳定性和可靠性。
LDPC码的基本原理是建立一个稀疏的矩阵,根据发送的信息符号,将其转换为一组编码符号。
编码符号的特点是它们之间的相关性很小,而且可以在接收端进行解码,以确保数据的准确性。
LDPC码是由一个稀疏的矩阵组成,这个矩阵由一系列的行和列组成,每一行和每一列都代表一个符号,这些符号之间的关系用0和1来表示。
在解码的过程中,接收端会计算每一行和每一列的符号之间的关系,根据这些符号的关系来计算出编码的结果。
LDPC码的优点在于它的译码速度比其他编码技术更快,也更易于实现,并且错误率更低。
此外,LDPC码也可以用于可变编码速率,提高传输过程中的效率。
总之,LDPC码是一种有效的编码技术,可以帮助我们提高数据传输的稳定性和可靠性,并提高传输的效率。
它的基本原理是建立一个稀疏的矩阵,根据发送的信息符号,将其转换为一组编码符号,这些符号之间的关系可以在接收端进行解码,以确保数据的准确性。
LDPC码编译码算法的研究与实现的开题报告

LDPC码编译码算法的研究与实现的开题报告一、研究背景和意义随着现代通信技术的不断发展,纠错编码逐渐成为提高无线通信和有线通信性能不可或缺的一个技术手段。
LDPC码(Low-Density Parity-Check Code),是一种具有良好性能的纠错编码方案,被广泛应用于无线通信和有线通信领域。
如何高效地进行LDPC 码的编码和解码,成为LDPC码的研究重点。
LDPC码的编码可以采用矩阵形式来表述,解码可以采用消息传递算法,如Belief Propagation算法、Min-Sum算法等。
当前研究重点是如何提高编码和解码效率,减少复杂度,并增强对信道噪声的抵抗能力。
本文将研究LDPC码编译码算法的现有研究,探究其在高纠错性能、低复杂度和适应于不同噪声环境等方面的改进和优化,以期提高LDPC码系统的性能,为通信领域的发展做出贡献。
二、研究内容和技术路线(一)研究内容:1. 探究当前LDPC码编解码算法的现有研究,分析其中存在的问题和可改进的方向。
2. 深入探讨LDPC码的编码和解码原理,分析编码和解码算法的理论优势和实际应用局限性。
3. 提出LDPC码编解码算法的改进,以提高其纠错性能和降低复杂度。
- 对消息传递算法进行优化,改进权值的更新方式,提高迭代收敛速度,增强对噪声的容错性。
- 在码长、码率和最小距离等方面做出兼顾,实现对指定信道下LDPC码系统的自适应调节- 提出模块化LDPC码编码方案,可动态添加LDPC码单元,支持LDPC码编码系统的灵活性和可扩展性。
4. 实现LDPC码编解码算法,验证算法的正确性和性能。
(二)技术路线1. 文献研究法:进行国内外相关领域的文献资料查询与阅读,了解当前LDPC码编解码算法的研究现状和存在的问题,为后续的研究打下基础。
2. 理论研究法:探究LDPC码的编码和解码原理,分析其算法优劣势,通过归纳总结分析,提出改进方案。
3. 模拟验证法:使用MATLAB等工具对提出的算法进行模拟和验证,评估算法的运行性能和准确性。
5g编码方案

5G编码方案引言随着5G通信技术的发展,人们对高速、低延迟、高可靠性的通信需求不断增加。
编码方案作为5G通信中的重要环节,起着关键的作用。
本文将介绍几种常见的5G编码方案,包括LDPC(低密度奇偶校验码)、Polar码、Turbo码等,并对它们的特点进行分析。
1. LDPC(低密度奇偶校验码)LDPC码是一种线性纠错码,最早由Robert G. Gallager教授在1962年提出。
它的编码和解码算法相对简单,并且具有很好的性能。
在5G通信中,LDPC码被广泛应用于物理层和信道编码。
LDPC码的编码过程是利用稀疏矩阵的特性,通过调整校验节点与信息节点之间的连接关系,达到高效的纠错性能。
它的解码过程通常采用迭代译码算法,例如和min-sum算法。
通过多次迭代,LDPC码可以达到接近信道容量的性能。
2. Polar码Polar码是由Erdal Arıkan教授于2008年提出的一种编码方案,它是一种基于概率分析的编码方案。
Polar码以简单的结构和优秀的性能而闻名。
Polar码的特点是通过编码矩阵的特殊结构,将原有的信息序列转化为具有不同可靠性的编码序列和冻结序列,从而实现纠错编码。
它的编码和解码算法相对复杂,通常采用递归解码算法,例如successive cancellation(SC)算法。
Polar码在5G通信中被广泛应用于控制信道和数据信道的编码,具有较低的解码复杂度和较好的纠错性能。
3. Turbo码Turbo码是一种串联系统的纠错码,由Claude Berrou等人于1993年提出。
Turbo码通过在编码和解码过程中引入交织器和迭代译码算法,提供了优秀的纠错性能。
Turbo码的编码过程是通过串行连接两个卷积码器来实现的,其中每个卷积码器采用不同的生成多项式。
解码过程则采用迭代译码算法,例如迭代软输出(SOVA)算法。
Turbo码在5G通信中被广泛应用于数据信道的编码,具有较好的纠错性能和较低的误比特率。
ldpc译码算法方法 -回复

ldpc译码算法方法-回复LDPC译码算法方法是一种基于低密度奇偶校验码(Low-Density Parity Check code,简称LDPC码)的译码算法。
LDPC码是一类特殊的线性分组码,具有译码性能良好的特点,并且可以通过使用合适的解码算法来降低译码复杂度。
在本文中,我们将逐步介绍LDPC译码算法的方法和步骤。
第一步,需要了解LDPC码的基本概念和特点。
LDPC码是一种具有稀疏校验矩阵的线性分组码,其校验矩阵的非零元素分布在矩阵的较少位置上,因此得名低密度奇偶校验码。
LDPC码具有较低的编码和解码复杂度,并且在无线通信、存储介质以及数字电视等领域得到广泛应用。
第二步,选择合适的LDPC码。
LDPC码的选择通常依赖于所需的编码效率和可靠性性能。
较高的编码效率可以提供更高的信息传输速率,而较高的可靠性性能可以减少译码错误的概率。
根据应用需求,可以选择不同的LDPC码类型,如Gallager码、Tanner码等。
第三步,构建LDPC码的校验矩阵。
LDPC码的校验矩阵是译码算法的关键,它决定了译码的能力和复杂度。
校验矩阵可以通过多种方法构建,如随机生成、洗牌算法、稀疏矩阵生成等。
构建校验矩阵的目标是使LDPC 码具有良好的纠错性能和较低的译码复杂度。
第四步,选择合适的LDPC译码算法。
LDPC码的译码算法可以分为迭代译码和非迭代译码两类。
迭代译码算法包括信念传播算法(Belief Propagation)和概率传播算法(Probability Propagation),它们通过多次迭代交换信息来逐步修正译码结果。
非迭代译码算法包括似然比译码算法(Log-Likelihood Ratio decoding)和软判决译码算法(Soft-Decision Decoding),它们通过计算不同译码路径的似然比来选择最佳译码结果。
第五步,实施LDPC译码算法。
实施LDPC译码算法涉及到编码和解码两个过程。
LDPC DECODING WITH FINITE PRECISION AND DYNAMIC AD

专利名称:LDPC DECODING WITH FINITE PRECISION AND DYNAMIC ADJUSTMENT OF THENUMBER OF ITERATIONS发明人:JAIN, Raj Kumar,SINGH, Ravindra申请号:EP2015/076974申请日:20151118公开号:WO2016/079185A1公开日:20160526专利内容由知识产权出版社提供专利附图:摘要:A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node (502) values representing bits of the result signal and check node (501) values representing constrains (505) of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.申请人:LANTIQ BETEILIGUNGS-GMBH & CO.KG地址:85579 DE国籍:DE代理人:NEUSSER, Sebastian更多信息请下载全文后查看。
decoding of LDPC

LDPC 码的解码算法LDPC 码的解码算法是保证其纠错性能的关键因素,主要包括三个方面:硬判决解码算法、软判决解码算法以及软信息和硬判决相结合的混合解码算法。
硬判决解码算法的复杂度最低,由于在解码前进行硬判决操作损失了信号的幅度信息从而使得该算法的性能较差。
软判决解码算法通过接收信号的幅度可以得到码字符号的概率信息,是性能最好的解码算法。
不同节点的概率信息通过Tanner图中的边来回传递提高了码字的纠错性能,但是软判决解码算法的复杂度很高。
混合解码算法在硬判决的同时利用了信号的幅度信息,性能和复杂度在前两种算法之间取得了一定的折衷。
混合解码算法对软信息的利用往往比较简单,性能提升较小,因此将作为硬判决算法的改进进行介绍。
随着硬件水平的发展以及一些降低软判决算法复杂度的改进算法的提出,软判决算法逐渐成为LDPC 码的主流解码算法,在实用性方面取得了较好的发展。
§1.1 LDPC 码的硬判决解码算法1.1.1 比特翻转算法比特翻转(Bit-Flipping, BF )算法是Gallager 在其论文中最先提出的一种针对LDPC 码的硬判决解码算法。
该算法实现结构简单,在解码过程中只有0、1比特上的操作,因此具有很好的硬件可实现性。
假设长度为K 的信息序列a =(a 0,a 1,…,a K -1),经过编码后得到长度为N 的码字序列v =(v 0,v 1,…v N -1)。
采用BPSK 调制方式,调制后的序列X =(x 0,x 1,…,x N -1),其中x i =2v i -1。
在接收端对接收到的信号Y =(y 0,y 1,…,y N -1)进行硬判决,得到Z =(z 0,z 1,…,z N -1)。
令LDPC 码的校验矩阵为,其中,M =N -K 。
011[,,...,]T M −=H h h h ,0,1,1(,,...,)T i i i i N h h h −=h 根据硬判决序列Z 和校验矩阵H ,计算得到码字的伴随式S 如式(1)所示:(1) 0110,00,10,11,01,11,10111,01,11,1(,,...,)(,,...,)M TTN N N M M M N s s s h h h h h h z z z h h h −−−−−−−−= =⎛⎞⎜⎟⎜⎟ =⎜⎟⎜⎟⎜⎟⎝⎠S ZH i其中(2)1,0N i i j j s −===∑Zh i j z h ⎟⎟上式中的加法运算是二进制域的模2加操作。
低SNR下基于LDPC译码的迭代SNR估计

2010年第01期,第43卷 通 信 技 术 Vol.43,No.01,2010 总第217期Communications Technology No.217,Totally ·传 输·低SNR下基于LDPC译码的迭代SNR估计包建荣a, 詹亚锋b, 殷柳国b, 陆建华ab(清华大学 a. 电子工程系;b.宇航技术研究中心,北京100084)【摘 要】针对低信噪比(≤0 dB)下SNR估计的难题,提出了基于低密度奇偶校验码(LDPC)译码辅助的迭代SNR估计算法。
该算法先采用期望最大(EM)原理及LDPC译码软信息实现SNR粗估计,再以不同SNR下LDPC软信息硬判结果满足校验矩阵约束程度的差异为判决依据,实现基于判决反馈的SNR精估计。
仿真表明,该算法能以相对较小的计算复杂度,使LDPC编码系统在低SNR下获得了较高精度的SNR估计。
【关键词】低密度奇偶校验码;信噪比;迭代信噪比估计【中图分类号】TN919.3 【文献标识码】A【文章编号】1002-0802(2010)01-0001-03Iterative SNR Estimation Based on LDPC Decoding at Low SNRsBAO Jian-rong a, ZHAN Ya-feng b, YIN Liu-guo b, LU Jian-hua ab(a. Department of Electronic Engineering;b. Tsinghua Space Center, Tsinghua University, Beijing 100084, China)【Abstract】It is difficult to estimate signal-to-noise ratio (SNR) at low SNR (≤0dB). An iterative SNR estimation algorithm based on LDPC decoding is proposed. By utilizing the expectation-maximization (EM) principle and LDPC decoding, this algorithm could get rough SNR estimation. Then the difference of the code constraint feedback of the hard decision from LDPC decoding with two different SNRs is used as the errors in a decision feedback method, thus obtaining accurate SNR estimation. Simulation results indicate that this algorithm could realize accurate SNR estimation for the LDPC coded systems at the cost of fairly less computation complexity.【Key words】LDPC code;SNR;iterative SNR estimation0 引言LDPC码通常采用置信传播(BP)译码来获得接近香农限的性能[1]。
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IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 53, NO. 2, FEBRUARY 2005209Transactions Letters________________________________________________________________Shuffled Iterative DecodingJuntan Zhang and Marc P. C. Fossorier, Senior Member, IEEEAbstract—Shuffled versions of iterative decoding of low-density parity-check codes and turbo codes are presented. The proposed schemes have about the same computational complexity as the standard versions, and converge faster. Simulations show that the new schedules offer better performance/complexity tradeoffs, especially when the maximum number of iterations has to remain small. Index Terms—Belief propagation (BP), iterative decoding, lowdensity parity-check (LDPC) codes, scheduling, turbo codes.two different angles, and eventually, achieve similar gains. The vertical scheduling proposed in this letter is an algorithmic approach intended to speed up BP decoding at no cost in complexity. For very-large-scale integration (VLSI) considerations, groups are introduced to preserve some parallel advantages of BP decoding. The horizontal scheduling of [6] and [7] is a hardware approach intended to serialize the totally parallel BP decoding. In the serialization, new updates become available at the same iteration, and speed up is also achieved by using them. II. ITERATIVE DECODING OF LDPC CODES LDPC code of length and A regular binary has a parity-check matrix , with dimension ones in each column and ones in each row. We denote the set of bits that participate in check by , and the set of checks in which bit participates as . Assume a codeword is transmitted over an additive white Gaussian noise (AWGN) channel with zero mean and variance using binary phasebe shift keying (BPSK) signaling, and let the corresponding received sequence. A. Standard BP for Iterative Decoding of LDPC Codes be the log-likelihood ratio (LLR) of bit Based on [1], let and initially set . Let and be the to bit node LLRs of bit which is sent from check node , and sent from the bit node to check node , respectively. Let denote the a posteriori LLR of bit . The standard BP algorithm [1] is carried out as follows. Initialization: Set , maximum number of iterations . For each , , set . to Step 1: a) Horizontal Step, for and each , process (1)I. INTRODUCTIONITERATIVE decoding based on belief propagation (BP) [1] has received significant attention recently, mostly due to its near-Shannon-limit error performance for the decoding of lowdensity parity-check (LDPC) codes [2] and turbo codes [3]. Like the maximum a posteriori (MAP) probability decoding scheme [4], it is a symbol-by-symbol soft-in/soft-out decoding algorithm. It processes the received symbols recursively to improve the reliability of each symbol based on constraints that specify the code. In the first iteration, the decoder only uses the channel output as input, and generates soft output for each symbol. Subsequently, the output reliability measures of the decoded symbols at the end of each decoding iteration are used as inputs for the next iteration. The decoding-iteration process continues until a certain stopping condition is satisfied. Then hard decisions are made, based on the output reliability measures of decoded symbols from the last decoding iteration. The aim of this letter is to develop shuffled versions of the standard iterative decoding algorithms for both LDPC and turbo codes. A similar approach for low-latency decoding of turbo product codes was proposed in [5]. In [6] and [7], a horizontal partitioning of the parity-check matrix was proposed to serialize the decoding of LDPC codes, and in the process, speed-up of the convergence was achieved. In this letter, we consider a vertical partitioning of the parity-check matrix to speed up the decoding. The two approaches are well introduced in [8]. It is interesting to note that the vertical and horizontal schedulings come fromPaper approved by P. Hoeher, the Editor for Coding and Communication Theory of the IEEE Communications Society. Manuscript received November 3, 2003; revised May 7, 2004; August 20, 2004; and September 21, 2004. This work was supported by the National Science Foundation under Grant CCR-00-98029 and Grant CCF-04-30576. This paper was presented in part at the 36th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 2002. The authors are with the Department of Electrical Engineering, University of Hawaii at Manoa, Honolulu, HI 96822 USA (e-mail: marc@aravis.eng. ). Digital Object Identifier 10.1109/TCOMM.2004.841982(2) b) Vertical Step, for process and each , (3) (4)0090-6778/$20.00 © 2005 IEEE210IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 53, NO. 2, FEBRUARY 2005Step 2: Hard decision and stopping criterion test such that if , a) Create if . and b) If or the maximum iteration number is reached, stop the decoding iteration and go and go to Step 1. to Step 3. Otherwise, set Step 3: Output as the decoded codeword., process jointly the following two Step 1) For steps. a) Horizontal Step, for and each , processB. Shuffled BP for Iterative Decoding of LDPC Codes At the th iteration of the standard BP algorithm, first all values of the check-to-bit messages are updated by using the th values of the bit-to-check messages obtained at the iteration, i.e., each is updated by using . Then, all values of the bit-to-check messages are updated by using the values of the check-to-bit messages newly is updated from obtained at the th iteration, i.e., each . In general, for both the check-to-bit messages and bit-to-check messages, the more independent information is used to update the messages, the more reliable they become. Iteration of the standard two-step implementation of the BP algorithm uses all values computed at the previous iteration in (1). However, certain values could already be computed in (3) based on a partial computation of the values obtained from (2), and then be used instead of in (1) to compute the remaining values . This suggests a shuffling of the horizontal and vertical steps of the standard BP decoding. Hence, we refer to this new version as shuffled BP decoding. Note that the updating procedure in shuffled BP is bit-based. In the shuffled BP algorithm, the initialization, stopping criterion test, and output steps remain the same as in the standard BP algorithm. The only difference between the two algorithms lies in the updating procedure. Step 1 of the shuffled BP algorithm and each , process is modified as: For the horizontal step and vertical step jointly, with (1) modified as(6)(7) b) Vertical Step, for , process each and(8) (9) For , the group shuffled BP becomes the standard BP, is the previously while the group shuffled BP with proposed shuffled BP.1 As an example, consider the code with parity-check matrix (10) The decoding processes for one iteration of the group shuffled BP is illustrated in Fig. 1 with 1 (standard BP), 2, and 6 (original shuffled BP). The shuffled BP algorithm for the decoding of LDPC codes keeps the computational advantages of the forward–backward implementations of the standard iteratively decoded BP, and requires the same computational complexity [10].2 Furthermore, when the Tanner graph of the LDPC code is acyclic and connected, the proposed method is optimal in the sense of MAP decoding and converges faster (or at least, no more slowly) than the standard BP algorithm [10] (proofs follow from the fact that shuffled BP is simply a new scheduling on the same graph). It is also straightforward to generalize the shuffled approach to various suboptimum versions of BP decoding. C. Simulation Results Fig. 2 depicts the word-error rate (WER) of iterative decoding of a (8000,4000) (3,6) LDPC code, with the group shuffled BP 1 (standard BP), 2, 8, 100, and 8000 (origalgorithm, for and a maxinal shuffled BP). We observe that at the WER imum of 20 iterations, the original shuffled BP algorithm performs about 0.2 dB better than standard BP algorithm, and the larger the value of , the better the error performance. How, no significant difference from is ever, for1A scheme similar to this totally sequential approach was proposed simultaneously in [11]. 2An increase in complexity due to more control logic may result.(5) We observe, however, that while one iteration of the standard BP algorithm can be fully processed in parallel, that of the shuffled BP algorithm becomes totally serial. To decrease decoding delay and preserve the parallelism advantages of the standard BP algorithm, a parallel shuffled decoding scheme named “group shuffled BP” is developed next. In the group shuffled BP algorithm, the code length is divided into a number of groups. In each group, the updating of messages is processed in parallel, but the processing of groups remains sequential. bits of a codeword are divided More precisely, assume the into groups, and each group contains bits for simplicity). Step 1 of the group (assuming shuffled BP algorithm is carried out as follows.IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 53, NO. 2, FEBRUARY 2005211Fig. 2. Error performance for iterative decoding of the (8000,4000) (3,6) LDPC code with group shuffled BP algorithm, for G = 1, 2, 8, 100, and 8000, and at most 20 iterations.Fig. 1. Group shuffled BP with G = 1; 2; 6 for decoding a code with N = 6. (a) G = 1 (standard BP). (b) G = 2. (c) G = 6 (original shuffled BP).Fig. 3. Average number of iterations for iterative decoding the (8000,4000) (3,6) LDPC code with group shuffled BP for G = 1, 2, 8, 100, and 8000, and at most 20 iterations.observed. Fig. 3 depicts the corresponding average number of iterations. We observe that the average number of iterations of the original shuffled BP algorithm is about half that of the standard BP algorithm, and the same type of differences as in Fig. 2 with respect to the values of . Both standard and shuffled BP decoding achieve the same error performance with a maximum of 2000 iterations, which indicates that the speedup is not achieved at the expense of a poorer achievable error performance. Similar gains were also achieved with suboptimum versions of BP decoding and the shuffled decoding approach. III. ITERATIVE DECODING OF TURBO CODE A turbo code [3] encoder comprises the concatenation of two (or more) convolutional encoders, and its decoder consists of two (or more) soft-in/soft-out convolutional decoders which feed reliability information back and forth to each other. For simplicity, we consider a turbo code that consists of tworatesystematic convolutional codes with encoders in feedback form. Let be an information be the correblock of length , and sponding coded sequence, where for is the output code block at time . Suppose BPSK transmission over an AWGN channel, with and all taking values in for and . Let be the received seis the received block quence, where at time . Let denote the estimate of . Let denote the encoder state at time . Following [4], define , , , where , , , and be the corresponding and let . values computed in component decoder , with Let denote the extrinsic value of the estimated infordelivered by component decoder at the th mation bit iteration.212IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 53, NO. 2, FEBRUARY 2005A. Standard Serial and Parallel Turbo Decoding The decoding approach proposed in [3] operates in serial mode, i.e., the component decoders take turns generating the extrinsic values of the estimated information symbols, and each component decoder uses the extrinsic messages delivered by the last component decoder as the a priori values of the information symbols. The disadvantage of this scheme is high decoding delay. In the parallel turbo decoding algorithm [9], all component decoders operate in parallel at any given time. After each iteration, each component decoder delivers extrinsic messages to other decoder(s) which use these messages as a priori values at the next iteration. B. Shuffled Turbo Decoding Although the parallel turbo decoding overcomes the drawback of high decoding delay of serial decoding, the extrinsic messages are not taken advantage of as soon as they are available, because the extrinsic messages are delivered to component decoders only after each iteration is completed. The aim of the shuffled turbo decoding is to use the more reliable exbe the trinsic messages at each time. Let permuted sequence by the interleaver corresponding to the orig, according to inal information sequence , for . We assume that the mapping . There is a unique corresponding reverse mapping , for and . In shuffled turbo decoding, the two component decoders operate simultaneously as in the parallel turbo decoding scheme, but the scheme of updating and delivering messages is different. We further assume that the two component decoders deliver , where extrinsic messages synchronously, i.e., and denote the times at which decoders 1 and 2 deliver the extrinsic values of the th estimated symbol of the original information sequence , and of the interleaved sequence , respectively. The shuffled turbo decoding scheme processes the backward recursion followed by the forward recursion. Let us first consider the forward recursion stage at the th itera, the values of tion of component decoder 1. After time should be updated, and the values of are needed. , There are two possible cases. The first case is which means the extrinsic value of the information bit is not available yet. Then the values , which are stored in the backward-recursion stage of the current iteration, are used to update the values and . The second case is , which means the extrinsic value of the information bit has already been delivered by decoder 2. Then this newly available is used to com(then stored), , and . pute the values The backward recursion in decoder 1, as well as both recursions in decoder 2, are realized based on the same principle. iterations, the shuffled turbo decoding algorithm outAfter as the decoded codeword, where puts , which is different from that in the standard serial turbo decoding [3]. The decoding processes of the standard serial, parallel, and shuffled turbo decoding are illustrated in Fig. 4.Fig. 4. Serial, parallel, and shuffled turbo decoding.Fig. 5. Bit-error performance of three-component turbo code with interleaver size 16384, for parallel decoding (dashed line) and shuffled decoding (solid line).It is straightforward to generalize the shuffled turbo decoding to multiple turbo codes which consist of more than two component codes. Based on the above descriptions, the total computational complexity of the shuffled turbo decoding for multiple turbo codes at each decoding iteration is the same as that of the parallel turbo decoding, and each of them has a decoding delay of the decoding delay of serial turbo dewhich is about coding, where is the number of component codes. C. Simulation Results We observed that shuffled turbo decoding does not present an advantage over standard decoding for turbo codes with two component codes. A possible reason is that with an increasingIEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 53, NO. 2, FEBRUARY 2005213number of component codes, the proportion of new updated extrinsic messages taken advantage of by each component decoder also increases. It is also known that parallel decoding outperforms serial decoding for turbo codes with more than two component codes [9]. Fig. 5 depicts the bit-error performance of a turbo code with three component codes (rate-1/4) and interleaver size 16384, with standard parallel decoding and shuffled decoding. After five iterations, the shuffled turbo decoder outperforms its parallel counterpart by several tenths of a decibel. REFERENCES[1] D. J. C. MacKay, “Good error-correcting codes based on very sparse matrices,” IEEE Trans. Inf. Theory, vol. 45, pp. 399–431, Mar. 1999. [2] R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, 1963. [3] C. Berrou and A. Glavieux, “Near-optimum error-correcting coding and decoding: Turbo-codes,” IEEE Trans. Commun., vol. 44, pp. 1261–1271, Oct. 1996.[4] L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inf. Theory, vol. IT-20, pp. 284–287, Mar. 1974. [5] C. Argon and S. McLaughlin, “A parallel decoder for low-latency decoding of turbo product codes,” IEEE Commun. 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