Induced burstiness in generalized processor sharing queues with long-tailed traffic flows

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Design And Application Guide For High Speed MOSFET Gate Drive Circuits

Design And Application GuideFor High Speed MOSFET Gate Drive CircuitsBy Laszlo BaloghABSTRACTThe main purpose of this paper is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest to power electronics engineers at all levels of experience.The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special chapter deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications.Several, step-by-step numerical design examples complement the paper.INTRODUCTIONMOSFET – is an acronym for Metal Oxide Semiconductor Field Effect Transistor and it is the key component in high frequency, high efficiency switching applications across the electronics industry. It might be surprising, but FET technology was invented in 1930, some 20 years before the bipolar transistor. The first signal level FET transistors were built in the late 1950’s while power MOSFETs have been available from the mid 70’s. Today, millions of MOSFET transistors are integrated in modern electronic components, from microprocessors, through “discrete” power transistors.The focus of this topic is the gate drive requirements of the power MOSFET in various switch mode power conversion applications. MOSFET TECHNOLOGYThe bipolar and the MOSFET transistors exploit the same operating principle. Fundamentally, both type of transistors are charge controlled devices which means that their output current is proportional to the charge established in the semiconductor by the control electrode. When these devices are used as switches, both must be driven from a low impedance source capable of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. From this point of view, the MOSFETs have to be driven just as “hard” during turn-on and turn-off as a bipolar transistor to achieve comparable switching speeds. Theoretically, the switching speeds of the bipolar and MOSFET devices are close to identical, determined by the time required for the charge carriers to travel across the semiconductor region. Typical values in power devices are approximately 20 to 200 picoseconds depending on the size of the device. The popularity and proliferation of MOSFET technology for digital and power applications is driven by two of their major advantages over the bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in high frequency switching applications. The MOSFET transistors are simpler to drive because their control electrode is isolated from the current conducting silicon, therefore a continuous ON current is not required. Once the MOSFET transistors are turned-on, their drive current is practically zero. Also, the controlling charge and accordingly the storage time in the MOSFET transistors is greatly reduced. This basicallyeliminates the design trade-off between on state voltage drop – which is inversely proportional to excess control charge – and turn-off time. As a result, MOSFET technology promises to use much simpler and more efficient drive circuits with significant economic benefits compared to bipolar devices.Furthermore, it is important to highlight especially for power applications, that MOSFETs have a resistive nature. The voltage drop across the drain source terminals of a MOSFET is a linear function of the current flowing in the semiconductor. This linear relationship is characterized by the R DS(on) of the MOSFET and known as the on-resistance. On-resistance is constant for a given gate-to-source voltage and temperature of the device. As opposed to the -2.2mV/°C temperature coefficient of a p-n junction, the MOSFETs exhibit a positive temperature coefficient of approximately 0.7%/°C to 1%/°C. This positive temperature coefficient of the MOSFET makes it an ideal candidate for parallel operation in higher power applications where using a single device would not be practical or possible. Due to the positive TC of the channel resistance, parallel connected MOSFETs tend to share the current evenly among themselves. This current sharing works automatically in MOSFETs since the positive TC acts as a slow negative feedback system. The device carrying a higher current will heat up more – don’t forget that the drain to source voltages are equal – and the higher temperature will increase its R DS(on) value. The increasing resistance will cause the current to decrease, therefore the temperature to drop. Eventually, an equilibrium is reached where the parallel connected devices carry similar current levels. Initial tolerance in R DS(on) values and different junction to ambient thermal resistances can cause significant – up to 30% – error in current distribution.Device typesAlmost all manufacturers have got their unique twist on how to manufacture the best power MOSFETs, but all of these devices on the market can be categorized into three basic device types. These are illustrated in Figure 1.Figure 1. Power MOSFET device types Double-diffused MOS transistors were introduced in the 1970’s for power applications and evolved continuously during the years. Using polycrystalline silicon gate structures and self-aligning processes, higher density integration and rapid reduction in capacitances became possible. The next significant advancement was offered by the V-groove or trench technology to further increase cell density in power MOSFET devices. The better performance and denser integration don’t come free however, as trench MOS devices are more difficult to manufacture.The third device type to be mentioned here is the lateral power MOSFETs. This device type is constrained in voltage and current rating due to its inefficient utilization of the chip geometry. Nevertheless, they can provide significant benefits in low voltage applications, like in microprocessor power supplies or as synchronous rectifiers in isolated converters.The lateral power MOSFETs have significantly lower capacitances, therefore they can switch much faster and they require much less gate drive power.MOSFET ModelsThere are numerous models available to illustrate how the MOSFET works, nevertheless finding the right representation might be difficult. Mostof the MOSFET manufacturers provide Spice and/or Saber models for their devices, but these models say very little about the application traps designers have to face in practice. They provide even fewer clues how to solve the most common design challenges.A really useful MOSFET model which would describe all important properties of the device from an application point of view would be very complicated. On the other hand, very simple and meaningful models can be derived of the MOSFET transistor if we limit the applicabilityof the model to certain problem areas.The first model in Figure 2 is based on the actual structure of the MOSFET device and can be used mainly for DC analysis. The MOSFET symbol in Figure 2a represents the channel resistance and the JFET corresponds to the resistance of the epitaxial layer. The length, thus the resistance of the epi layer is a function of the voltage rating of the device as high voltage MOSFETs require thicker epitaxial layer.Figure 2b can be used very effectively to model the dv/dt induced breakdown characteristic of a MOSFET. It shows both main breakdown mechanisms, namely the dv/dt induced turn-on of the parasitic bipolar transistor - present in all power MOSFETs - and the dv/dt induced turn-onof the channel as a function of the gate terminating impedance. Modern power MOSFETs are practically immune to dv/dt triggering of the parasitic npn transistor due to manufacturing improvements to reduce the resistance between the base and emitter regions.It must be mentioned also that the parasitic bipolar transistor plays another important role. Its base – collector junction is the famous body diode of the MOSFET.Figure 2. Power MOSFET modelsFigure 2c is the switching model of the MOSFET. The most important parasitic components influencing switching performance are shown in this model. Their respective roles will be discussed in the next chapter which is dedicated to the switching procedure of the device.MOSFET Critical ParametersWhen switch mode operation of the MOSFET is considered, the goal is to switch between the lowest and highest resistance states of the device in the shortest possible time. Since the practical switching times of the MOSFETs (~10ns to 60ns) is at least two to three orders of magnitude longer than the theoretical switching time (~50ps to 200ps), it seems important to understand the discrepancy. Referring back to the MOSFET models in Figure 2, note that all models include three capacitors connected between the three terminals of the device. Ultimately, the switching performance of the MOSFET transistor is determined by how quickly the voltages can be changed across these capacitors.Therefore, in high speed switching applications, the most important parameters are the parasitic capacitances of the device. Two of these capacitors, the C GS and C GD capacitors correspond to the actual geometry of the device while the C DS capacitor is the capacitance of the base collector diode of the parasitic bipolar transistor (body diode).The C GS capacitor is formed by the overlap of the source and channel region by the gate electrode. Its value is defined by the actual geometry of the regions and stays constant (linear) under different operating conditions.The C GD capacitor is the result of two effects. Part of it is the overlap of the JFET region and the gate electrode in addition to the capacitance of the depletion region which is non-linear. The equivalent C GD capacitance is a function of the drain source voltage of the device approximated by the following formula:DS1GD,0GD V K 1C C ⋅+≈The C DS capacitor is also non-linear since it is the junction capacitance of the body diode. Its voltage dependence can be described as:DS 2DS,0DS V K C C ⋅≈Unfortunately, non of the above mentioned capacitance values are defined directly in the transistor data sheets. Their values are given indirectly by the C ISS , C RSS , and C OSS capacitor values and must be calculated as: RSSOSS DS RSS ISS GS RSSGD C C C C C C C C −=−== Further complication is caused by the C GD capacitor in switching applications because it is placed in the feedback path between the input and output of the device. Accordingly, its effective value in switching applications can be much larger depending on the drain source voltage of the MOSFET. This phenomenon is called the “Miller” effect and it can be expressed as:()GD L fs eqv GD,C R g 1C ⋅⋅+=Since the C GD and C DS capacitors are voltage dependent, the data sheet numbers are valid only at the test conditions listed. The relevant average capacitances for a certain application have to be calculated based on the required charge to establish the actual voltage change across the capacitors. For most power MOSFETs the following approximations can be useful: offDS,spec DS,spec OSS,ave OSS,off DS,spec DS,spec RSS,ave GD,V V C 2C V V C 2C ⋅⋅=⋅⋅=The next important parameter to mention is the gate mesh resistance, R G,I . This parasitic resistance describes the resistance associated by the gate signal distribution within the device. Its importance is very significant in high speed switching applications because it is in between the driver and the input capacitor of the device, directly impeding the switching times and thedv/dt immunity of the MOSFET. This effect is recognized in the industry, where real high speed devices like RF MOSFET transistors use metal gate electrodes instead of the higher resistance polysilicon gate mesh for gate signal distribution. The R G,I resistance is not specified in the data sheets, but in certain applications it can be a very important characteristic of the device. In the back of this paper, Appendix A4 shows a typical measurement setup to determine the internal gate resistor value with an impedance bridge.Obviously, the gate threshold voltage is also a critical characteristic. It is important to note that the data sheet V TH value is defined at 25°C and at a very low current, typically at 250μA. Therefore, it is not equal to the Miller plateau region of the commonly known gate switching waveform. Another rarely mentioned fact about V TH is its approximately –7mV/°C temperature coefficient. It has particular significance in gate drive circuits designed for logic level MOSFET where V TH is already low under the usual test conditions. Since MOSFETs usually operate at elevated temperatures, proper gate drive design must account for the lower V TH when turn-off time, and dv/dt immunity is calculated as shown in Appendix A and F.The transconductance of the MOSFET is its small signal gain in the linear region of its operation. It is important to point out that every time the MOSFET is turned-on or turned-off, it must go through its linear operating mode where the current is determined by the gate-to-source voltage. The transconductance, g fs , is the small signal relationship between drain current and gate-to-source voltage:GSD fs dV dI g =Accordingly, the maximum current of the MOSFET in the linear region is given by: ()fs th GS D g V V I ⋅−=Rearranging this equation for V GS yields the approximate value of the Miller plateau as a function of the drain current.fs D th Miller GS,g IV V +=Other important parameters like the source inductance (L S ) and drain inductance (L D ) exhibit significant restrictions in switching performance. Typical L S and L D values are listed in the data sheets, and they are mainly dependant on the package type of the transistor. Their effects can be investigated together with the external parasitic components usually associated with layout and with accompanying external circuit elements like leakage inductance, a current sense resistor, etc.For completeness, the external series gate resistor and the MOSFET driver’s output impedance must be mentioned as determining factors in high performance gate drive designs as they have a profound effect on switching speeds and consequently on switching losses.SWITCHING APPLICATIONSNow, that all the players are identified, let’s investigate the actual switching behavior of the MOSFET transistors. To gain a better understanding of the fundamental procedure, the parasitic inductances of the circuit will be neglected. Later their respective effects on the basic operation will be analyzed individually. Furthermore, the following descriptions relate to clamped inductive switching because most MOSFET transistors and high speed gate drive circuits used in switch mode power supplies work in that operating mode.Figure 3. Simplified clamped inductive switchingmodelThe simplest model of clamped inductive switching is shown in Figure 3, where the DC current source represents the inductor. Its current can be considered constant during the short switching interval. The diode provides a path for the current during the off time of the MOSFET and clamps the drain terminal of the device to the output voltage symbolized by the battery.Turn-On procedureThe turn-on event of the MOSFET transistor can be divided into four intervals as depicted in Figure 4.Figure 4. MOSFET turn-on time intervalsIn the first step the input capacitance of the device is charged from 0V to V TH. During this interval most of the gate current is charging the C GS capacitor. A small current is flowing through the C GD capacitor too. As the voltage increases at the gate terminal and the C GD capacitor’s voltage has to be slightly reduced. This period is called the turn-on delay, because both the drain current and the drain voltage of the device remain unchanged.Once the gate is charged to the threshold level, the MOSFET is ready to carry current. In the second interval the gate is rising from V TH to the Miller plateau level, V GS,Miller. This is the linear operation of the device when current is proportional to the gate voltage. On the gate side, current is flowing into the C GS and C GD capacitors just like in the first time interval and the V GS voltage is increasing. On the output side of the device, the drain current is increasing, while the drain-to-source voltage stays at the previous level (V DS,OFF). This can be understood looking at the schematic in Figure 3. Until all the current is transferred into the MOSFET and the diode is turned-off completely to be able to block reverse voltage across its pn junction, the drain voltage must stay at the output voltage level. Entering into the third period of the turn-on procedure the gate is already charged to the sufficient voltage (V GS,Miller) to carry the entire load current and the rectifier diode is turned off. That now allows the drain voltage to fall. While the drain voltage falls across the device, the gate-to-source voltage stays steady. This is the Miller plateau region in the gate voltage waveform. All the gate current available from the driver is diverted to discharge the C GD capacitor to facilitate the rapid voltage change across the drain-to-source terminals. The drain current of the device stays constant since it is now limited by the external circuitry, i.e. the DC current source.The last step of the turn-on is to fully enhance the conducting channel of the MOSFET by applying a higher gate drive voltage. The final amplitude of V GS determines the ultimate on-resistance of the device during its on-time. Therefore, in this fourth interval, V GS is increased from V GS,Miller to its final value, V DRV. This is accomplished by charging the C GS and C GD capacitors, thus gate current is now split between the two components. While these capacitors are being charged, the drain current is still constant, and the drain-to-source voltage is slightly decreasing as the on-resistance of the device is being reduced.Turn-Off procedureThe description of the turn-off procedure for the MOSFET transistor is basically back tracking the turn-on steps from the previous section. Start with V GS being equal to V DRV and the current in the device is the full load current represented by I DC in Figure 3. The drain-to-source voltage is being defined by I DC and the R DS(on) of the MOSFET. The four turn-off steps are shown in Figure 5. for completeness.Figure 5. MOSFET turn-off time intervals The first time interval is the turn-off delay which is required to discharge the C ISS capacitance from its initial value to the Miller plateau level. During this time the gate current is supplied by the C ISS capacitor itself and it is flowing through the C GS and C GD capacitors of the MOSFET. The drain voltage of the device is slightly increasing as the overdrive voltage is diminishing. The current in the drain is unchanged. In the second period, the drain-to-source voltage of the MOSFET rises from I D⋅R DS(on) to the final V DS(off) level, where it is clamped to the output voltage by the rectifier diode according to the simplified schematic of Figure 3. During this time period – which corresponds to the Miller plateau in the gate voltage waveform - the gate current is strictly the charging current of the C GD capacitor because the gate-to-source voltage is constant. This current is provided by the bypass capacitor of the power stage and it is subtracted from the drain current. The total drain current still equals the load current, i.e. the inductor current represented by the DC current source in Figure 3.The beginning of the third time interval is signified by the turn-on of the diode, thus providing an alternative route to the load current. The gate voltage resumes falling from V GS,Miller to V TH. The majority of the gate current is coming out of the C GS capacitor, because the C GD capacitor is virtually fully charged from the previous time interval. The MOSFET is in linear operation and the declining gate-to-source voltage causes the drain current to decrease and reach near zero by the end of this interval. Meanwhile the drain voltage is steady at V DS(off) due to the forward biased rectifier diode.The last step of the turn-off procedure is to fully discharge the input capacitors of the device. V GS is further reduced until it reaches 0V. The bigger portion of the gate current, similarly to the third turn-off time interval, supplied by the C GS capacitor. The drain current and the drain voltage in the device are unchanged.Summarizing the results, it can be concluded that the MOSFET transistor can be switched between its highest and lowest impedance states (either turn-on or turn-off) in four time intervals. The lengths of all four time intervals are a function of the parasitic capacitance values, the required voltage change across them and the available gate drive current. This emphasizes the importance of the proper component selection and optimum gate drive design for high speed, high frequency switching applications.Characteristic numbers for turn-on, turn-off delays, rise and fall times of the MOSFET switching waveforms are listed in the transistor data sheets. Unfortunately, these numbers correspond to the specific test conditions and to resistive load, making the comparison of different manufacturers’ products difficult. Also, switching performance in practical applications with clamped inductive load is significantly different from the numbers given in the data sheets.Power lossesThe switching action in the MOSFET transistorin power applications will result in some unavoidable losses, which can be divided into two categories.The simpler of the two loss mechanisms is the gate drive loss of the device. As described before, turning-on or off the MOSFET involves chargingor discharging the C ISS capacitor. When the voltage across a capacitor is changing, a certain amount of charge has to be transferred. The amount of charge required to change the gate voltage between 0V and the actual gate drive voltage V DRV, is characterized by the typical gate charge vs. gate-to-source voltage curve in the MOSFET datasheet. An example is shown in Figure 6.Figure 6. Typical gate charge vs. gate-to-sourcevoltage This graph gives a relatively accurate worst case estimate of the gate charge as a function of the gate drive voltage. The parameter used to generate the individual curves is the drain-to-source off state voltage of the device. V DS(off) influences the Miller charge – the area below the flat portion of the curves – thus also, the total gate charge required in a switching cycle. Once the total gate charge is obtained from Figure 6, the gate charge losses can be calculated as:DRVGDRVGATEfQVP⋅⋅=where V DRV is the amplitude of the gate drive waveform and f DRV is the gate drive frequency – which is in most cases equal to the switching frequency. It is interesting to notice that the Q G⋅f DRV term in the previous equation gives the average bias current required to drive the gate. The power lost to drive the gate of the MOSFET transistor is dissipated in the gate drive circuitry. Referring back to Figures 4 and 5, the dissipating components can be identified as the combination of the series ohmic impedances in the gate drive path. In every switching cycle the required gate charge has to pass through the driver output impedances, the external gate resistor, and the internal gate mesh resistance. As it turns out, the power dissipation is independent of how quickly the charge is delivered through the resistors. Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed as:OFFDRV,ONDRV,DRVIG,GATELODRVGDRVLOOFFDRV,IG,GATEHIDRVGDRVHIONDRV,PPPRRRfQVR21PRRRfQVR21P+=++⋅⋅⋅⋅=++⋅⋅⋅⋅=In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct answers. It is safe to assume that with low value gate resistors (<5Ω) most gate drive losses are dissipated in the driver. If R GATE is sufficiently large to limit I G below the outputcurrent capability of the bipolar driver, the majority of the gate drive power loss is then dissipated in R GATE .In addition to the gate drive power loss, the transistors accrue switching losses in the traditional sense due to high current and high voltage being present in the device simultaneously for a short period. In order to ensure the least amount of switching losses, the duration of this time interval must be minimized. Looking at the turn-on and turn-off procedures of the MOSFET, this condition is limited to intervals 2 and 3 of the switching transitions in both turn-on and turn-off operation. These time intervals correspond to the linear operation of the device when the gate voltage is between V TH and V GS,Miller , causing changes in the current of the device and to the Miller plateau region when the drain voltage goes through its switching transition.This is a very important realization to properly design high speed gate drive circuits. It highlights the fact that the most important characteristic of the gate driver is its source-sink current capability around the Miller plateau voltage level. Peak current capability, which is measured at full V DRV across the driver’s output impedance, has very little relevance to the actual switching performance of the MOSFET. What really determines the switching times of the device is the gate drive current capability when the gate-to-source voltage, i.e. the output of the driver is at ~5V (~2.5V for logic level MOSFETs).A crude estimate of the MOSFET switching losses can be calculated using simplified linear approximations of the gate drive current, drain current and drain voltage waveforms during periods 2 and 3 of the switching transitions. First the gate drive currents must be determined for the second and third time intervals respectively:()G.I GATE HI MillerGS,DRV G3G.IGATE HI TH Miller GS,DRVG2R R R V V I R R R V V 0.5V I ++−=+++⋅−=Assuming that I G2 charges the input capacitor of the device from V TH to V GS,Miller and I G3 is the discharge current of the C RSS capacitor while the drain voltage changes from V DS(off) to 0V, the approximate switching times are given as:G3offDS,RSS G2THMillerGS,ISS I V C t3I V V C t2⋅=−⋅=During t2 the drain voltage is V DS(off) and the current is ramping from 0A to the load current, I L while in t3 time interval the drain voltage is falling from V DS(off) to near 0V. Again, using linear approximations of the waveforms, the power loss components for the respective time intervals can be estimated:Loff DS,Loff DS,I 2V T t3P32I V T t2P2⋅⋅=⋅⋅=where T is the switching period. The total switching loss is the sum of the two loss components, which yields the following simplifed expression:Even though the switching transitions are well understood, calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components which will significantly alter the current and voltage waveforms, as well as the switching times during the switching procedures. Taking into account the effect of the different source and drain inductances of a real circuit would result in second order differential equations to describe the actual waveforms of the circuit. Since the variables, including gate threshold voltage, MOSFET capacitor values, driver output impedances, etc. have a very wide tolerance, the above described linear approximation seems to be a reasonable enough compromise to estimate switching losses in the MOSFET.Effects of parasitic componentsThe most profound effect on switching performance is exhibited by the source inductance. There are two sources for parasitic source inductance in a typical circuit, the sourceTt3t22I V P L DS(off)SW +⋅⋅=。

本征约瑟夫森结阵列的IV特性及应用

I-V characteristic of intrinsic Josephsonjunction arrays and its applications1Tiege Zhou Shaolin Yan Fengbin Song Xu Zhang Lang FangDepartment of Electronics, Nankai University, Tianjin, P. R. China 300071Email: zhoutiege@AbstractI-V characteristic of intrinsic Josephson junction arrays made of misalignedTl-2212 thin films with different shunt resistance was investigated. Constant-currentand negative-resistance phenomena were observed in the I-V characteristic curve.Taking advantage of these new characteristics, we put forward new type of constant-current devices and negative-resistance devices. Applications of both devices wereintroduced.Keywords: High-temperature superconductors, Josephson arrays, Josephson devicemeasurement applications, Negative resistance circuits.1IntroductionHigh-temperature superconductor (HTS) ceramics have a strong anisotropy in its lattice. For most HTS materials, the coherence length of Copper pairs along the c-axis is shorter than the spacing between the superconducting Cu-O planes. This will lead to intrinsic Josephson effects [1] [2]. For Tl-2212 thin films, Cu-O layers are separated by Ba-O and Tl-O layers. The Cu-O layers act as superconducting electrodes of the intrinsic Josephson junctions (IJJs) and the Ba-O and Tl-O layers act as insulator barriers. Much research has been done about misaligned Tl-2212 films IJJs (for details, see[3] [4]). It is of great value to investigate the characteristic of intrinsic Josephson junctions (IJJs), witha view to possible applications. We investigated I-V characteristic of Tl-2212 film IJJs shunted by gold layer resistors. For shunted IJJs with βc=1, the I-V characteristic shows an obvious constant current region. For IJJs with βc>1, the I-V characteristic shows an obvious negative resistance region. Taking advantage of these new characteristics, we put forward new type of constant current device and negative resistance device. Their applications were investigated. We will present our experimental results in this paper.2ExperimentalDevices were made of HTS Tl2Ba2CaCu2O x (Tl-2212) thin films grown on LaAlO3 single crystal substrates. The substrate surface was cut at an angle of 20o tilted to the LaAlO3 (001) plane. The Tl-2212 superconducting thin film was fabricated in two-step process: deposition of amorphous Tl-Ba-Ca-Cu-O precursor film and conversion of the precursor film into Tl-2212 superconducting phase by post annealing process [5]. Briefly, the Tl-Ba-Ca-Cu-O precursor film was deposited by1 Support by Specialized Research Fund for Doctoral Program of Higher Education in Chinaoff-axis magnetron sputtering from a pair of facing Tl-2212 targets in a mixture of Ar and O 2 gases (Ar/O 2=4/1) with a total pressure of about 1.5 Pa. For the second processing step, the precursor film was sealed in a crucible together with a pre-reacted Tl-Ba-Ca-Cu-O pellet and annealed at temperature of 760℃ in 1 atm pure argon. The resulting thin film was pure Tl-2212 phase and epitaxial growth on the slanting substrate surface, i.e., the Cu-O planes of the Tl-2212 film had an angle of 20o to the substrate surface [6]. In our experiments, all films were of 400 nm thickness, with T c >104K.The Tl-2212 thin film was patterned into microbridge by standard photolithography and wet chemical etching. The direction of the microbridge was along the slanting direction of the Cu-O plane to the substrate surface. Along the microbridge we get a stack of IJJs. The schematic structure of the stacked intrinsic junctions in the microbridge is shown in Figure 1. An 8 μm long microbridge has 1800intrinsic Josephson junctions in series.Figure 1. The schematic structure of the intrmicrobridgeFigure 2. Photograph of a 6 μm wide and 8 μm long microbridge.In order to investigate the influence of shunt resistance to the I-V characteristics of IJJs, we connected resistors in parallel with IJJs. The shunt resistor was made by sputtering a thin layer of gold on the film before photolithography. After photolithography, wet etching with KI+I 2 solution and dilute HCl acid was used to etch the gold layer and the superconducting film, respectively. The resistance can be controlled by the sputtering time. The longer the sputtering time is, the smaller the shunt resistance will be. The corresponding McCumber parameter βc was calculated by the I-V curve and junction’s parameters [7]. Figure 2 shows the photograph of a 6 μm wide and 8 μm long microbridge.I-V characteristics of the devices were measured using the standard four-probe technique. Two gold electrodes were deposited on each terminal of a device to reduce the contact resistance. An adjustable voltage source was used to plot I-V characteristic curves, which can eliminate the voltage jump across IJJs. The use of a voltage source is also the reason why we can get a negative resistance characteristic [8].3 Results and discussionsI-V characteristics of three devices with different thickness of gold layers are shown in Figure 3. To measure the I-V characteristics, an adjustable voltage source was applied. All of the samples were 6 μm wide and 8 μm long. Curve A shows the I-V characteristic of sample I. The sputtering time of the gold layer of this sample was 5 seconds, which resulted in a shunt resistance of 0.49 Ω for each intrinsic junction. The corresponding McCumber parameter βc is about0.52. The I-V curve demonstrates a typical I-V characteristic of RSJ mode.Curve B is the result of Sample II. The sputtering time of the gold layer was 2 seconds. The shunt resistance of each intrinsic junction is 1.07 Ω and βc ≈0.91 which is slightly smaller than 1. It can be find that the current is nearly stabilized at 5.8 mA when the voltage is in the range of 0.5－9 V. This promptsthe use of this sample as a constant-current device.Fig.3 I-V characteristics of three devices with (A)c β=0.52, (B)c β=0.91 and (C)c β =1.66,respectively.Figure 4. Load resistor dependence of the constant current when the voltage sources are 9 V (curve A),6 V (curve B) and 3 V (curve C), respectively. Curve C is the result of sample III. The sputtering time for its gold layer is 1 second. The shunt resistance is 2.54 Ω and βc ≈1.66. It is obvious that there is a negative resistance region which is caused by the use of voltage source and βc >1. If we use current source, the I-V curve will become hysteretic.4 Applications4.1 As constant current devicesWe can see from above that IJJs may work as constant-current devices when βc is close to 1. In order to test this application, we connected Sample II, a voltage source, and a load resistor in serial to see the load resistance dependence of the current. The current change with load resistance is plotted in Figure 4. In the experiment, we used different constant voltage source, i.e., 9V, 6V and 3V. Comparatively obvious turning points in the curves can be seen, 1.7 k Ω on curve A, 1.3 k Ω on curve B and 0.6 k Ω on curve C. Before the turning point the current is nearly constant, and it changes greatly after the turning point. At the turning point the whole voltage is applied across the load resistance and the device is in a zero-voltage state. It is obvious that, to provide a larger load resistance with a constant current, larger voltage source is needed. If using the device to provide bias current for a component in circuits, the current fluctuation will not exceed 1% as the load resistance has a change of 50 Ω.This new kind of device has great value in superconductive circuits, because Josephson junctions in superconductive circuits dissipate little itself, but the current bias resistors dissipate much power. In order to minimize the ohm dissipation, we must exploit new device. Using constant current device as bias can reduce the dissipation. Because it can give a constant current, while the working voltage can be very low. So it dissipates little power.It should be noticed that, according to AC Josephson effects, there is RF modulation on the constant current of the device and the frequency is proportional to the mean value of the voltage across the device. In this particular case, the Josephson oscillations may become a noise. Fortunately, because its frequency is very high, so the device can work very well in low frequency circuits. In the microwave range, because of bad impedance matching of the device, the AC current is so small that it will not impose severe limitations. In particular case, we can connect an inductor with the device to reduce the AC current.4.2 As negative resistance devicesA new microbridg of 2 μm wide and 2 μm long was made to investigate the negative-resistance characteristic. In order to obtain an obvious negative resistance curve, the microbridge has no gold layer on it. The same adjustable voltage source was used to plot its I-V curve.0.00.40.8 1.21.60.00.40.81.21.6C u r r e n t / m AVoltage / VFigure 5: I-V characteristic of a 2 μm wide and 2 μm long microbridge without gold layer Shown in Figure 3 is the I-V characteristic curve in which clear negative resistance region can be seen. We can get that the dynamic resistance is -1400Ω when the voltage is in the range of 0.1-0.7V, thepeak voltage is 0.09 V, the peak current is 1.44 mA, the valley point voltage is 0.75 V, and the valley point current is 1.05 mA.Using this device, we constructed a simple amplifying circuit to examine the possibility of its application. Shown is Figure 6 is the schematics of the circuit. T is a transformer for signal input. E is a 0.4V voltage source. R1 is a 100Ω resistor. R2 is the load resistor for which we adopt different value to make measurements. An oscilloscope was used to observe the voltage across R1 and R2, and then we get the value of current through R1 and R2. The ratio of I R2 and I R1 is the current gain. The signal is AC voltage with a peak-to-peak value of 0.1V and a frequency of 10 kHz. The device was immersed in LN2. Figure 7 shows the AC current gain versus the load resistance. The black spot is the experimental result and the curve is get from negative resistance theory. We can see that they agree with each other verywell.A m p l i f i c a t i o nload resistance (ohm)Figure 6: schematic diagram of the amplifying circuit Figure 7: amplification against load resistance This kind of device is active. It can amplify signals. So this kind of device is of great value for realizing fully superconducting circuits.It is also because of AC Josephson effect, this kind of device can not work at microwave frequency. But it can work in low frequency very well. Research is being done in our group to determine the maximum working frequency of this kind of device.5 ConclusionsWe investigated I-V characteristics of Tl-2212 thin film intrinsic Josephson Junctions by means of shunting resistance. New characteristics were observed. Using these new characteristics, we put forward new type of constant-current device and negative-resistance device. The applications of new devices were introduced. Both of the devices can work in low frequency range very well.Ref e re nc es[1] R. Kleiner and P. Muller, Intrinsic Josephson effects in high-Tc superconductors, Physical Review B, 49(1994),1327-1342[2] R. Kleiner P. Muller H. Kohlstedt N.F. Pedersen and S. Sakai, Dynamic behavior of Josephson-coupledlayered structures, Physical Review B, 50(1994), 3924-3936[3] O.S.Chana et al. Josephson effects in misaligned Tl-2212 films, Physica C 326-327(1999)[4] O.S.Chana et al. Properties of Tl2Ba2CaCuO8 thin film intrinsic Josephson junctions in an in-plane magneticfield, Physica C 362(2001) 265-268[5] S.L. Yan L. Fang Q.X. Song J. Yan, Formation of epitaxial Tl2Ba2CaCu2O8 thin films at low temperature inpure argon, Appl. Phys. Lett., 63(1993), 1845-1847[6] S.L. Yan L. Fang M.S. Si J. Wang J.M. Hao Q.X. Song, Intrinsic Josephson junctions of Tl2Ba2CaCu2O8 thinfilms, Physica C, 282-287(1997), 2433-2434[7] E.J. Tarte, G.A. Wagner, R.E. Somekh et al, The capacitance of bicrystal Josephson junctions deposited onSrTiO3 substrates, IEEE Trans. Appl. Supercond. 7(1997), 3662-3665[8] W. C. Stewart, CURRENT-VOLTAGE CHARACTERISTICS OF JOSEPHSON JUNCTIONS, AppliedPhysics Letters, 12(1968), 277-279。

计算机组织与系统结构第七章习题答案

习题1．给出以下概念的解释说明。

指令流水线（Instruction pipelining）流水线深度（Pipeline Depth）指令吞吐量（Instruction throughput）流水线冒险（Hazard）结构冒险（Structural hazard）控制冒险（Control hazard）数据冒险（Data hazard）流水线阻塞（Pipeline stall）气泡（Bubble）空操作（nop）分支条件满足（Branch taken）分支预测（Branch predict）静态分支预测（Static predict）动态分支预测（Dynamic predict）延迟分支（Delayed branch）分支延迟槽（Delayed branch slot）转发（Forwarding）旁路（Bypassing）流水段寄存器（Pipeline register）IPC（Instructions Per Cycle）静态多发射（Static multiple issue）动态多发射（Dynamic multiple issue）超流水线（Superpipelining）超长指令字VLIW超标量流水线（Superscalar）动态流水线（Dynamic pipelining）指令预取（Instruction prefetch）指令分发（Instruction dispatch）按序发射（in-order issue）无序发射（out-of-order issue）存储站（Reservation station）重排序缓冲（Reorder buffer）指令提交单元（Instruction commit unit）乱序执行（out-of-order execution）按序完成（in-order completion）无序完成（out-of-order completion）2. 简单回答下列问题。

Two-Dimensional Gas of Massless Dirac Fermions in Graphene

Two-Dimensional Gas of Massless Dirac Fermions in Graphene K.S. Novoselov1, A.K. Geim1, S.V. Morozov2, D. Jiang1, M.I. Katsnelson3, I.V. Grigorieva1, S.V. Dubonos2, A.A. Firsov21Manchester Centre for Mesoscience and Nanotechnology, University of Manchester, Manchester, M13 9PL, UK2Institute for Microelectronics Technology, 142432, Chernogolovka, Russia3Institute for Molecules and Materials, Radboud University of Nijmegen, Toernooiveld 1, 6525 ED Nijmegen, the NetherlandsElectronic properties of materials are commonly described by quasiparticles that behave as nonrelativistic electrons with a finite mass and obey the Schrödinger equation. Here we report a condensed matter system where electron transport is essentially governed by the Dirac equation and charge carriers mimic relativistic particles with zero mass and an effective “speed of light” c∗ ≈106m/s. Our studies of graphene – a single atomic layer of carbon – have revealed a variety of unusual phenomena characteristic of two-dimensional (2D) Dirac fermions. In particular, we have observed that a) the integer quantum Hall effect in graphene is anomalous in that it occurs at halfinteger filling factors; b) graphene’s conductivity never falls below a minimum value corresponding to the conductance quantum e2/h, even when carrier concentrations tend to zero; c) the cyclotron mass mc of massless carriers with energy E in graphene is described by equation E =mcc∗2; and d) Shubnikov-de Haas oscillations in graphene exhibit a phase shift of π due to Berry’s phase.Graphene is a monolayer of carbon atoms packed into a dense honeycomb crystal structure that can be viewed as either an individual atomic plane extracted from graphite or unrolled single-wall carbon nanotubes or as a giant flat fullerene molecule. This material was not studied experimentally before and, until recently [1,2], presumed not to exist. To obtain graphene samples, we used the original procedures described in [1], which involve micromechanical cleavage of graphite followed by identification and selection of monolayers using a combination of optical, scanning-electron and atomic-force microscopies. The selected graphene films were further processed into multi-terminal devices such as the one shown in Fig. 1, following standard microfabrication procedures [2]. Despite being only one atom thick and unprotected from the environment, our graphene devices remain stable under ambient conditions and exhibit high mobility of charge carriers. Below we focus on the physics of “ideal” (single-layer) graphene which has a different electronic structure and exhibits properties qualitatively different from those characteristic of either ultra-thin graphite films (which are semimetals and whose material properties were studied recently [2-5]) or even of our other devices consisting of just two layers of graphene (see further). Figure 1 shows the electric field effect [2-4] in graphene. Its conductivity σ increases linearly with increasing gate voltage Vg for both polarities and the Hall effect changes its sign at Vg ≈0. This behaviour shows that substantial concentrations of electrons (holes) are induced by positive (negative) gate voltages. Away from the transition region Vg ≈0, Hall coefficient RH = 1/ne varies as 1/Vg where n is the concentration of electrons or holes and e the electron charge. The linear dependence 1/RH ∝Vg yields n =α·Vg with α ≈7.3·1010cm-2/V, in agreement with the theoretical estimate n/Vg ≈7.2·1010cm-2/V for the surface charge density induced by the field effect (see Fig. 1’s caption). The agreement indicates that all the induced carriers are mobile and there are no trapped charges in graphene. From the linear dependence σ(Vg) we found carrier mobilities µ =σ/ne, whichreached up to 5,000 cm2/Vs for both electrons and holes, were independent of temperature T between 10 and 100K and probably still limited by defects in parent graphite. To characterise graphene further, we studied Shubnikov-de Haas oscillations (SdHO). Figure 2 shows examples of these oscillations for different magnetic fields B, gate voltages and temperatures. Unlike ultra-thin graphite [2], graphene exhibits only one set of SdHO for both electrons and holes. By using standard fan diagrams [2,3], we have determined the fundamental SdHO frequency BF for various Vg. The resulting dependence of BF as a function of n is plotted in Fig. 3a. Both carriers exhibit the same linear dependence BF = β·n with β ≈1.04·10-15 T·m2 (±2%). Theoretically, for any 2D system β is defined only by its degeneracy f so that BF =φ0n/f, where φ0 =4.14·10-15 T·m2 is the flux quantum. Comparison with the experiment yields f =4, in agreement with the double-spin and double-valley degeneracy expected for graphene [6,7] (cf. caption of Fig. 2). Note however an anomalous feature of SdHO in graphene, which is their phase. In contrast to conventional metals, graphene’s longitudinal resistance ρxx(B) exhibits maxima rather than minima at integer values of the Landau filling factor ν (Fig. 2a). Fig. 3b emphasizes this fact by comparing the phase of SdHO in graphene with that in a thin graphite film [2]. The origin of the “odd” phase is explained below. Another unusual feature of 2D transport in graphene clearly reveals itself in the T-dependence of SdHO (Fig. 2b). Indeed, with increasing T the oscillations at high Vg (high n) decay more rapidly. One can see that the last oscillation (Vg ≈100V) becomes practically invisible already at 80K whereas the first one (Vg <10V) clearly survives at 140K and, in fact, remains notable even at room temperature. To quantify this behaviour we measured the T-dependence of SdHO’s amplitude at various gate voltages and magnetic fields. The results could be fitted accurately (Fig. 3c) by the standard expression T/sinh(2π2kBTmc/heB), which yielded mc varying between ≈ 0.02 and 0.07m0 (m0 is the free electron mass). Changes in mc are well described by a square-root dependence mc ∝n1/2 (Fig. 3d). To explain the observed behaviour of mc, we refer to the semiclassical expressions BF = (h/2πe)S(E) and mc =(h2/2π)∂S(E)/∂E where S(E) =πk2 is the area in k-space of the orbits at the Fermi energy E(k) [8]. Combining these expressions with the experimentally-found dependences mc ∝n1/2 and BF =(h/4e)n it is straightforward to show that S must be proportional to E2 which yields E ∝k. Hence, the data in Fig. 3 unambiguously prove the linear dispersion E =hkc∗ for both electrons and holes with a common origin at E =0 [6,7]. Furthermore, the above equations also imply mc =E/c∗2 =(h2n/4πc∗2)1/2 and the best fit to our data yields c∗ ≈1⋅106 m/s, in agreement with band structure calculations [6,7]. The employed semiclassical model is fully justified by a recent theory for graphene [9], which shows that SdHO’s amplitude can indeed be described by the above expression T/sinh(2π2kBTmc/heB) with mc =E/c∗2. Note that, even though the linear spectrum of fermions in graphene (Fig. 3e) implies zero rest mass, their cyclotron mass is not zero. The unusual response of massless fermions to magnetic field is highlighted further by their behaviour in the high-field limit where SdHO evolve into the quantum Hall effect (QHE). Figure 4 shows Hall conductivity σxy of graphene plotted as a function of electron and hole concentrations in a constant field B. Pronounced QHE plateaux are clearly seen but, surprisingly, they do not occur in the expected sequence σxy =(4e2/h)N where N is integer. On the contrary, the plateaux correspond to half-integer ν so that the first plateau occurs at 2e2/h and the sequence is (4e2/h)(N + ½). Note that the transition from the lowest hole (ν =–½) to lowest electron (ν =+½) Landau level (LL) in graphene requires the same number of carriers (∆n =4B/φ0 ≈1.2·1012cm-2) as the transition between other nearest levels (cf. distances between minima in ρxx). This results in a ladder of equidistant steps in σxy which are not interrupted when passing through zero. To emphasize this highly unusual behaviour, Fig. 4 also shows σxy for a graphite film consisting of only two graphene layers where the sequence of plateaux returns to normal and the first plateau is at 4e2/h, as in the conventional QHE. We attribute this qualitative transition between graphene and its two-layer counterpart to the fact that fermions in the latter exhibit a finite mass near n ≈0 (as found experimentally; to be published elsewhere) and can no longer be described as massless Dirac particles. 2The half-integer QHE in graphene has recently been suggested by two theory groups [10,11], stimulated by our work on thin graphite films [2] but unaware of the present experiment. The effect is single-particle and intimately related to subtle properties of massless Dirac fermions, in particular, to the existence of both electron- and hole-like Landau states at exactly zero energy [912]. The latter can be viewed as a direct consequence of the Atiyah-Singer index theorem that plays an important role in quantum field theory and the theory of superstrings [13,14]. For the case of 2D massless Dirac fermions, the theorem guarantees the existence of Landau states at E=0 by relating the difference in the number of such states with opposite chiralities to the total flux through the system (note that magnetic field can also be inhomogeneous). To explain the half-integer QHE qualitatively, we invoke the formal expression [9-12] for the energy of massless relativistic fermions in quantized fields, EN =[2ehc∗2B(N +½ ±½)]1/2. In QED, sign ± describes two spins whereas in the case of graphene it refers to “pseudospins”. The latter have nothing to do with the real spin but are “built in” the Dirac-like spectrum of graphene, and their origin can be traced to the presence of two carbon sublattices. The above formula shows that the lowest LL (N =0) appears at E =0 (in agreement with the index theorem) and accommodates fermions with only one (minus) projection of the pseudospin. All other levels N ≥1 are occupied by fermions with both (±) pseudospins. This implies that for N =0 the degeneracy is half of that for any other N. Alternatively, one can say that all LL have the same “compound” degeneracy but zeroenergy LL is shared equally by electrons and holes. As a result the first Hall plateau occurs at half the normal filling and, oddly, both ν = –½ and +½ correspond to the same LL (N =0). All other levels have normal degeneracy 4B/φ0 and, therefore, remain shifted by the same ½ from the standard sequence. This explains the QHE at ν =N + ½ and, at the same time, the “odd” phase of SdHO (minima in ρxx correspond to plateaux in ρxy and, hence, occur at half-integer ν; see Figs. 2&3), in agreement with theory [9-12]. Note however that from another perspective the phase shift can be viewed as the direct manifestation of Berry’s phase acquired by Dirac fermions moving in magnetic field [15,16]. Finally, we return to zero-field behaviour and discuss another feature related to graphene’s relativistic-like spectrum. The spectrum implies vanishing concentrations of both carriers near the Dirac point E =0 (Fig. 3e), which suggests that low-T resistivity of the zero-gap semiconductor should diverge at Vg ≈0. However, neither of our devices showed such behaviour. On the contrary, in the transition region between holes and electrons graphene’s conductivity never falls below a well-defined value, practically independent of T between 4 and 100K. Fig. 1c plots values of the maximum resistivity ρmax(B =0) found in 15 different devices, which within an experimental error of ≈15% all exhibit ρmax ≈6.5kΩ, independent of their mobility that varies by a factor of 10. Given the quadruple degeneracy f, it is obvious to associate ρmax with h/fe2 =6.45kΩ where h/e2 is the resistance quantum. We emphasize that it is the resistivity (or conductivity) rather than resistance (or conductance), which is quantized in graphene (i.e., resistance R measured experimentally was not quantized but scaled in the usual manner as R =ρL/w with changing length L and width w of our devices). Thus, the effect is completely different from the conductance quantization observed previously in quantum transport experiments. However surprising, the minimum conductivity is an intrinsic property of electronic systems described by the Dirac equation [17-20]. It is due to the fact that, in the presence of disorder, localization effects in such systems are strongly suppressed and emerge only at exponentially large length scales. Assuming the absence of localization, the observed minimum conductivity can be explained qualitatively by invoking Mott’s argument [21] that mean-free-path l of charge carriers in a metal can never be shorter that their wavelength λF. Then, σ =neµ can be re-written as σ = (e2/h)kFl and, hence, σ cannot be smaller than ≈e2/h per each type of carriers. This argument is known to have failed for 2D systems with a parabolic spectrum where disorder leads to localization and eventually to insulating behaviour [17,18]. For the case of 2D Dirac fermions, no localization is expected [17-20] and, accordingly, Mott’s argument can be used. Although there is a broad theoretical consensus [18-23,10,11] that a 2D gas of Dirac fermions should exhibit a minimum 3conductivity of about e2/h, this quantization was not expected to be accurate and most theories suggest a value of ≈e2/πh, in disagreement with the experiment. In conclusion, graphene exhibits electronic properties distinctive for a 2D gas of particles described by the Dirac rather than Schrödinger equation. This 2D system is not only interesting in itself but also allows one to access – in a condensed matter experiment – the subtle and rich physics of quantum electrodynamics [24-27] and provides a bench-top setting for studies of phenomena relevant to cosmology and astrophysics [27,28].1. Novoselov, K.S. et al. PNAS 102, 10451 (2005). 2. Novoselov, K.S. et al. Science 306, 666 (2004); cond-mat/0505319. 3. Zhang, Y., Small, J.P., Amori, M.E.S. & Kim, P. Phys. Rev. Lett. 94, 176803 (2005). 4. Berger, C. et al. J. Phys. Chem. B, 108, 19912 (2004). 5. Bunch, J.S., Yaish, Y., Brink, M., Bolotin, K. & McEuen, P.L. Nanoletters 5, 287 (2005). 6. Dresselhaus, M.S. & Dresselhaus, G. Adv. Phys. 51, 1 (2002). 7. Brandt, N.B., Chudinov, S.M. & Ponomarev, Y.G. Semimetals 1: Graphite and Its Compounds (North-Holland, Amsterdam, 1988). 8. Vonsovsky, S.V. and Katsnelson, M.I. Quantum Solid State Physics (Springer, New York, 1989). 9. Gusynin, V.P. & Sharapov, S.G. Phys. Rev. B 71, 125124 (2005). 10. Gusynin, V.P. & Sharapov, S.G. cond-mat/0506575. 11. Peres, N.M.R., Guinea, F. & Castro Neto, A.H. cond-mat/0506709. 12. Zheng, Y. & Ando, T. Phys. Rev. B 65, 245420 (2002). 13. Kaku, M. Introduction to Superstrings (Springer, New York, 1988). 14. Nakahara, M. Geometry, Topology and Physics (IOP Publishing, Bristol, 1990). 15. Mikitik, G. P. & Sharlai, Yu.V. Phys. Rev. Lett. 82, 2147 (1999). 16. Luk’yanchuk, I.A. & Kopelevich, Y. Phys. Rev. Lett. 93, 166402 (2004). 17. Abrahams, E., Anderson, P.W., Licciardello, D.C. & Ramakrishnan, T.V. Phys. Rev. Lett. 42, 673 (1979). 18. Fradkin, E. Phys. Rev. B 33, 3263 (1986). 19. Lee, P.A. Phys. Rev. Lett. 71, 1887 (1993). 20. Ziegler, K. Phys. Rev. Lett. 80, 3113 (1998). 21. Mott, N.F. & Davis, E.A. Electron Processes in Non-Crystalline Materials (Clarendon Press, Oxford, 1979). 22. Morita, Y. & Hatsugai, Y. Phys. Rev. Lett. 79, 3728 (1997). 23. Nersesyan, A.A., Tsvelik, A.M. & Wenger, F. Phys. Rev. Lett. 72, 2628 (1997). 24. Rose, M.E. Relativistic Electron Theory (John Wiley, New York, 1961). 25. Berestetskii, V.B., Lifshitz, E.M. & Pitaevskii, L.P. Relativistic Quantum Theory (Pergamon Press, Oxford, 1971). 26. Lai, D. Rev. Mod. Phys. 73, 629 (2001). 27. Fradkin, E. Field Theories of Condensed Matter Systems (Westview Press, Oxford, 1997). 28. Volovik, G.E. The Universe in a Helium Droplet (Clarendon Press, Oxford, 2003).Acknowledgements This research was supported by the EPSRC (UK). We are most grateful to L. Glazman, V. Falko, S. Sharapov and A. Castro Netto for helpful discussions. K.S.N. was supported by Leverhulme Trust. S.V.M., S.V.D. and A.A.F. acknowledge support from the Russian Academy of Science and INTAS.43µ (m2/Vs)0.8c4P0.4 22 σ (1/kΩ)10K0 0 1/RH(T/kΩ) 1 2ρmax (h/4e2)1-5010 Vg (V) 50 -10ab 0 -100-500 Vg (V)50100Figure 1. Electric field effect in graphene. a, Scanning electron microscope image of one of our experimental devices (width of the central wire is 0.2µm). False colours are chosen to match real colours as seen in an optical microscope for larger areas of the same materials. Changes in graphene’s conductivity σ (main panel) and Hall coefficient RH (b) as a function of gate voltage Vg. σ and RH were measured in magnetic fields B =0 and 2T, respectively. The induced carrier concentrations n are described by [2] n/Vg =ε0ε/te where ε0 and ε are permittivities of free space and SiO2, respectively, and t ≈300 nm is the thickness of SiO2 on top of the Si wafer used as a substrate. RH = 1/ne is inverted to emphasize the linear dependence n ∝Vg. 1/RH diverges at small n because the Hall effect changes its sign around Vg =0 indicating a transition between electrons and holes. Note that the transition region (RH ≈ 0) was often shifted from zero Vg due to chemical doping [2] but annealing of our devices in vacuum normally allowed us to eliminate the shift. The extrapolation of the linear slopes σ(Vg) for electrons and holes results in their intersection at a value of σ indistinguishable from zero. c, Maximum values of resistivity ρ =1/σ (circles) exhibited by devices with different mobilites µ (left y-axis). The histogram (orange background) shows the number P of devices exhibiting ρmax within 10% intervals around the average value of ≈h/4e2. Several of the devices shown were made from 2 or 3 layers of graphene indicating that the quantized minimum conductivity is a robust effect and does not require “ideal” graphene.ρxx (kΩ)0.60 aVg = -60V4B (T)810K12∆σxx (1/kΩ)0.4 1ν=4 140K 80K B =12T0 b 0 25 50 Vg (V) 7520K100Figure 2. Quantum oscillations in graphene. SdHO at constant gate voltage Vg as a function of magnetic field B (a) and at constant B as a function of Vg (b). Because µ does not change much with Vg, the constant-B measurements (at a constant ωcτ =µB) were found more informative. Panel b illustrates that SdHO in graphene are more sensitive to T at high carrier concentrations. The ∆σxx-curves were obtained by subtracting a smooth (nearly linear) increase in σ with increasing Vg and are shifted for clarity. SdHO periodicity ∆Vg in a constant B is determined by the density of states at each Landau level (α∆Vg = fB/φ0) which for the observed periodicity of ≈15.8V at B =12T yields a quadruple degeneracy. Arrows in a indicate integer ν (e.g., ν =4 corresponds to 10.9T) as found from SdHO frequency BF ≈43.5T. Note the absence of any significant contribution of universal conductance fluctuations (see also Fig. 1) and weak localization magnetoresistance, which are normally intrinsic for 2D materials with so high resistivity.75 BF (T) 500.2 0.11/B (1/T)b5 10 N 1/2025 a 0 0.061dmc /m00.04∆0.02 0c0 0 T (K) 150n =0e-6-3036Figure 3. Dirac fermions of graphene. a, Dependence of BF on carrier concentration n (positive n correspond to electrons; negative to holes). b, Examples of fan diagrams used in our analysis [2] to find BF. N is the number associated with different minima of oscillations. Lower and upper curves are for graphene (sample of Fig. 2a) and a 5-nm-thick film of graphite with a similar value of BF, respectively. Note that the curves extrapolate to different origins; namely, to N = ½ and 0. In graphene, curves for all n extrapolate to N = ½ (cf. [2]). This indicates a phase shift of π with respect to the conventional Landau quantization in metals. The shift is due to Berry’s phase [9,15]. c, Examples of the behaviour of SdHO amplitude ∆ (symbols) as a function of T for mc ≈0.069 and 0.023m0; solid curves are best fits. d, Cyclotron mass mc of electrons and holes as a function of their concentration. Symbols are experimental data, solid curves the best fit to theory. e, Electronic spectrum of graphene, as inferred experimentally and in agreement with theory. This is the spectrum of a zero-gap 2D semiconductor that describes massless Dirac fermions with c∗ 300 times less than the speed of light.n (1012 cm-2)σxy (4e2/h)4 3 2 -2 1 -1 -2 -3 2 44Kn7/ 5/ 3/ 1/2 2 2 210 ρxx (kΩ)-4σxy (4e2/h)0-1/2 -3/2 -5/2514T0-7/2 -4 -2 0 2 4 n (1012 cm-2)Figure 4. Quantum Hall effect for massless Dirac fermions. Hall conductivity σxy and longitudinal resistivity ρxx of graphene as a function of their concentration at B =14T. σxy =(4e2/h)ν is calculated from the measured dependences of ρxy(Vg) and ρxx(Vg) as σxy = ρxy/(ρxy + ρxx)2. The behaviour of 1/ρxy is similar but exhibits a discontinuity at Vg ≈0, which is avoided by plotting σxy. Inset: σxy in “two-layer graphene” where the quantization sequence is normal and occurs at integer ν. The latter shows that the half-integer QHE is exclusive to “ideal” graphene.。

电信5G协优考试题库(含答案)

电信5G协优考试题库（含答案）单选题1.关于BWP的应用场景，说法正确的是A、选项全正确B、UE在大小BWP间进行切换，达到省电的效果C、应用于小带宽能力UE接入大带宽网络D、不同的BWP，配置不同的Numerology，承载不同的业务答案：A2.协议中5GNR毫米波单载波支持最大的频域带宽A、200MB、400MC、800MD、1000M答案：B3.5G系统中以()为最小粒度进行QoS管理。

A、E-RABbearerB、PDUSessionC、QoSflowD、以上都不是答案：C4.5G用于下行数据辅助解调的信号是哪项A、DMRSB、PT-RSC、ssD、CSI-RS答案：A5.56单站验证时，传输带宽的要求是？A、500MB、800MC、900MD、2G答案：B6.以下5GNRslotformat的说法对的有A、SCS=60KHz时，支持配置Periodic=0.625msB、Cell-specific的单周期配置中，单个配置周期内只支持一个转换点C、对DL/UL分配的修改以slot为单位答案：B7.在5G中，PUSCH支持的波形有A、DFT-S-OFDMB、DFT-a-OFDMC、DFT-OFDMD、S-OFDM答案：A8.电信选择的帧结构为()A、2ms单周期B、2.5ms单周期C、2.5ms双周期D、5ms单周期答案：C9.以下哪个参数用于指示对于SpCell,是否上报PHRtype2A、phr-Type2SpCellB、phr-Type2OtherCellC、phr-ModeOtherCGD、dualConnectivityPHR答案：A10.5G支持的新业务类型不包括A、eMBBB、URLLCC、eMTCD、mMTC答案：C11.你预计中国的5G将会在什么时候规模商用A、2018到2019.B、2020到2022C、2023到2025D、2025到2030答案：B12.一般情况下，NR基站的RSRP信号低于多少时，用户观看1080P视频开始出现缓冲和卡顿？A、-112dBmB、-107dBmC、-102dBmD、-117dBm答案：D13.IT服务台是一种：A、流程B、设备C、职能D、职称答案：C14.SN添加的事件为A、A2B、A3C、B1D、B2答案：C15.以下SSB的测量中，那些测量标识中只可以在连接态得到：A、SS-RSRPB、SS-RSRQC、SS-SINRD、SINR答案：C16.哪个docker镜像用于配置数据生效及查询？A、oambsB、nfoamC、brsD、ccm答案：B17.5G中，sub-6GHz频段能支持的最大带宽是A、60MHzB、80MHzC、100MHzD、200MHz答案：C18.eLTEeNB和gNB之间的接口称为()接口A、X1B、X2C、XnD、Xx答案：C19.ShortTTI子载波间隔为A、110KHzB、120KHzC、130KHzD、140KHz答案：B20.NR核心网中用于会话管理的模块是A、AMFB、SMFC、UDMD、PCF答案：B21.中移选择的帧结构为()A、2ms单周期B、2.5ms单周期C、2.5ms双周期D、5ms单周期答案：D22.ZXRAN室外宏站楼顶安装天线抱杆直径要求需满足？A、60mm~120mmB、40mm~60mmC、20mm~40mmD、10mm~20mm答案：A23.关于自包含帧说法错误的:A、同一子帧内包含DL、UL和GPB、同一子帧内包含对DL数据和相应的HARQ反馈C、采用自包含帧可以降低对发射机和接收机的硬件要求D、同一子帧内传输UL的调度信息和对应的数据信息答案：C24.属于LPWAN技术的是A、LTEB、EVDOC、CDMAD、NB-IOT答案：D25.5G天线下倾角调整的优先级是以下哪项？A、调整机械下倾＞调整可调电下倾一＞预置电下傾B、预置电下倾つ调整机械下傾－＞调整可调电下倾C、调整可调电下倾一＞预置电下倾→调整机械下傾D、预置电下倾一＞调整可调电下倾调整机械下倾答案：D26.5G的无线接入技术特性将（5GRATfeatures）会分阶段进行，即phase1和p hase2.请问5G的phase2是哪个版本？A、R13B、R14C、R15D、R16答案：D27.5GNR网管服务器时钟同步失败的可能原因有？A、网络连接不正常B、主备板数据库不一致C、EMS小区数目超限D、SBCX备板不在位答案：A28.以下对5GNR切换优化问题分析不正确的是？A、是否漏配邻区B、测试点覆盖是否合理C、小区上行是否存在干扰D、后台查询是否有用户答案：D29.5G系统中，1个CCE包含了多少个REG？A、2B、6C、4D、8答案：B30.NR网络中，PRACH信道不同的序列格式对应不同的小区半径，小区半径最大支持多少KMA、110B、89C、78D、100答案：D31.协议已经定义5G基站可支持CU和DU分离部署架构，在()之间分离A、RRC和PDCPB、PDCP和RLCC、RLC和MACD、MAC和PHY答案：B32.AAU倾角调整优先级正确描述为以下哪项？A、调整可调电下倾->调整机械下倾->数字下倾->设计合理的预置电下倾B、设计合理的预置电下倾->调整可调电下倾->调整机械下倾->数字下倾C、调整可调电下倾->调整机械下倾->设计合理的预置电下倾->数字下倾D、调整可调电下倾->设计合理的预置电下倾->调整机械下倾->数字下倾答案：B33.5G的基站和4G的基站的主要差异在A、RRUB、BBUC、CPRID、接口答案：B34.UE最多监听多少个不同的DCIFormatSizePerSlotA、2B、3C、4D、5答案：C35.仅支持FR1的UE在连接态下完成配置了TRS，TRS与SSB可能存在下面哪个QCL关系A、QCL-TypeAB、QCL-TypeBC、QCL-TypeCD、QCL-TypeD答案：C36.5G网络中，回传承载的是和之间的流量A、DU、CUB、AAU、DUC、CU、核心网D、AAU、CU答案：C37.不属于5G网络的信道或信号是()A、PDSCHB、PUSCHC、PDCCHD、PCFICH答案：D38.5G的愿景是A、一切皆有可能B、高速率，高可靠C、万物互联D、信息随心至，万物触手及答案：D39.关于MeasurementGap描述错误的是A、EN-DC下，网络可以配置Per-UEmeasurementgap，也可以配置Per-FRmeasur ementgap；B、EN-DC下，LTE服务小区和NR服务小区（FR1)的同属于perFR1measurementg ap;C、EN-DC下，gap4～gap11可以用于支持Per-FR1measurementgap的UE；D、EN-DC下，支持per-UEmeasurementgap的UE，若同时用于NR和非NR邻区测量，可以用gap0～11。

5G题库整理-单选题

1.5GNR下，DL Layer mapping的时候当layer数大于（），codeword才是双流A)2B)3C)4D)5参考答案：C2.5GNR下，SPS配置使用如下那种RNTI加扰的PDCCH进行资源调度（）A)SPS C-RNTIB)CS-RNTIC)C.C-RNTID)RA-RANTI参考答案：B3.5GNR下，一个SS/PBCH block包含（）个OFDM symbolsA)1B)2C)3D)4参考答案：D4.5G参数集包含哪些参数( )A)SCS+CPB)BWPC)BandwidthD)Slot format参考答案：A5.5G帧结构描述中，下面哪一项是错误的( )A)帧结构配置可以由SIB静态帧结构配置B)上下行资源比例可在1:4到2:3之间调整C)R15的协议中，RRC高层配置的tdd-UL-DL-ConfigurationDedicated定义了周期大小D)DCI format2-0用于动态指示帧结构参考答案：C6.5G只能在（）上去做RLMA)UL BWPB)active UL BWPC)DL BWPD)active DL BWP参考答案：D7.gNB可以通过哪种方式给UE发送Timing AdvanceCommand（）A)RRC专用信令B)MAC CEC)系统消息D)DCI参考答案：B8.LTE测量NR，测量的基本单位是（）A)小区B)BeamC)载波D)PLMN参考答案：B9.LTE测量NR的RS类型是（）A)SSBB)CSI-RS参考答案：A10.NR小区SA部署时，Initial DL BWP的BW、SCS和CP由下面哪个CORESET定义（）。

A)CORESET0B)CORESET1C)CORESET2D)CORESET3参考答案：A11.NR一共支持几种子载波间隔配置（）A)3B)4C)5D)6参考答案：C12.NR中Long Truncated/Long BSR的MAC CE包含几个bit（）A)2B)4C)6D)8参考答案：D13.NR中SR在下列哪个信道上发送？（）A)PUCCH format1/format 0B)PUCCH format1/1a/1bC)PUSCHD)PUCCH format3参考答案：A14.NR中下行HARQ最多可以配置多少个进程（）A)2B)4C)8D)16参考答案：D15.Release 14之后有几种PHR Type ( )A)1B)2C)3D)4参考答案：C16.SCG的主小区被称作( )A)Primary cellB)MCG Secondary cellC)SCG Secondary cellD)PSCell参考答案：D17.SCG失败时，下面哪项正确()A)UE悬挂所有的SCG无线承载的SCG传输并向MN上报SCG失败信息，触发RRC连接重建B)UE不维持当前MN和SN的测量配置C)UE不执行MN和SN配置的测量D)SN配置的测量通过MN路由时，在SCG失败时，UE继续上报SN配置测量形成的测量报告参考答案：D18.TRS的频域密度（density）为（）D)以上都对参考答案：C19.UE在每个NR serving小区下最多监听几个通过C-RNTI加扰的DCI Format（）。

lvs错误类型

Dracula LVS 错误类型用Dracula 做LVS时得到report的格式大致是schematic section : Layout sectio n。

当然本篇讨论的是LVS error types而不是教会大家如何阅读LVS report，只不过选用了Dracula作为基础来讨论检查LVS 时可能出现的错误类型。

Device type Terminals listedMOS Gate, source, drainBJT Collector, base, emitterRES/CAP/DIODE Terminals-1, terminal-2SMID/PMID Out1, out2, list of input nodesBOX Terminal-1, terminal-2, terminal-3, terminal-4SDW/SDWI/SUP/SUPI /PDW/PDWI/PUP/PUPI /AND/OR/Output, list of input nodesNADN/NOR/AOI/OAIINV Output, inputCELL Composite node 1 – pin name 1上表列出Dracula summary 中所识别器件的类型及节点显示顺序。

下图为上表中常见器件类型的举例说明。

PMID: Parallel Middle StructureSMID: Series Middle StructurePUP: Parallel Pull-Up StructureSUP: Series Pull-Up StructurePDW: Parallel Pull-Down StructureSDW: Series Pull-Down StructureLVS 中某个不匹配的点可能引出一个节点、一个组件或一个子集(一组节点和组件), 也就是说“错一点而动全身”。

LVS列出每个不对应的点，并且都会对应到某种错误类型，当然并不表示列出的每个节点都是有错的。

Scenario Reduction for Futures Market Trading in Electricity Markets

878IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 24, NO. 2, MAY 2009Scenario Reduction for Futures Market Trading in Electricity MarketsJuan M. Morales, Student Member, IEEE, Salvador Pineda, Student Member, IEEE, Antonio J. Conejo, Fellow, IEEE, and Miguel Carrión, Member, IEEEAbstract—To make informed decisions in futures markets of electric energy, stochastic programming models are commonly used. Such models treat stochastic processes via a set of scenarios, which are plausible realizations throughout the decision-making horizon of the stochastic processes. The number of scenarios needed to accurately represent the uncertainty involved is generally large, which may render the associated stochastic programming problem intractable. Hence, scenario reduction techniques are needed to trim down the number of scenarios while keeping most of the stochastic information embedded in such scenarios. This paper proposes a novel scenario reduction procedure that advantageously compares with existing ones for electricity-market problems tackled via two-stage stochastic programming. Index Terms—Decision making, electricity markets, scenario reduction, stochastic programming.I. INTRODUCTION O MAKE informed decisions in electricity markets, stochastic programming models are commonly used [1]–[10]. In particular, some of these models are used by producers to determine the sales of energy through forward contracts in futures markets and in the pool, and by retailers and consumers to decide purchases in futures markets through forward contracts and in the pool. Stochastic programming models [11] represent stochastic processes (e.g., electricity pool prices or electricity demands) via a set of scenarios, which are plausible realizations of the stochastic processes throughout the decision-making horizon. For example, if the decision-making horizon is one year, pool price uncertainty can be represented by a number of vectors (e.g., 1000), each one containing a possible realization of hourly pool prices throughout the year (i.e., 8760 values). The number of scenarios needed to accurately represent the most plausible realizations of the stochastic processes is generally very large, which may render the associated stochastic programming problem intractable. For instance, a decision-making problem considering 1000 scenarios, each one represented by a vector of 8760 values, may be intractable or may require an unreasonably long execution time. Therefore, scenario reductionTManuscript received March 06, 2008; revised November 04, 2008. First published March 16, 2009; current version published April 22, 2009. This work was supported by part by Junta de Comunidades de Castilla-La Mancha under project PCI-08-0102 and in part by the Ministry of Education and Science of Spain under CICYT project DPI2006-08001. Paper no. TPWRS-00179-2008. The authors are with the University of Castilla-La Mancha, Ciudad Real, Spain (e-mail: JuanMiguel.Morales@uclm.es; Salvador.Pineda@uclm.es; Antonio.Conejo@uclm.es; Miguel.Carrion@uclm.es). Digital Object Identiﬁer 10.1109/TPWRS.2009.2016072techniques are needed to trim down signiﬁcantly the number of scenarios while keeping as intact as possible the stochastic information embedded in such scenarios. This paper proposes a novel scenario reduction procedure that advantageously compares with existing ones for electricity-market problems. The proposed technique allows further reducing the number of scenarios determined by other techniques, while retaining the same level of stochastic information as the scenario set provided by alternative techniques. However, the proposed methodology lacks a theoretical background supporting and motivating its generalized use. Therefore, for the sake of consistency, the proposed technique should be understood as a heuristic which experimentally turns out to perform satisfactorily for electricity-market problems. There are available several methods to generate and reduce scenarios to be used in stochastic programming. A short overview of the most common methods is provided in [12]. An easy way to generate price scenarios is just the sampling method, proposed in [13]. In [14], the authors propose a moment matching method to generate a limited number of scenarios that satisfy speciﬁed statistical properties. Reference [15] describes an optimal discretization method that seeks to ﬁnd an approximation of the initial scenario set that minimizes an error based on the objective function. Speciﬁcally, scenario reduction techniques for two-stage stochastic programming problems are described in [16]–[19]. These methods seek to obtain a reduced number of scenarios that best retain the essential features of a given original scenario set according to a probability distance. The generation of scenarios for multistage stochastic problems is described in [20]. Scenario reduction for multistage stochastic problems is addressed in [21] according to the stability results provided in [22]. The contribution of this paper is providing an efﬁcacious scenario reduction technique for electricity-market problems tackled via a two-stage stochastic programming approach. Moderately increasing the computational burden required by other procedures, the proposed technique retains the same level of stochastic information but results in a signiﬁcantly smaller number of scenarios than the number provided by alternative procedures. The remaining of this paper is organized as follows. Section II describes, as motivating examples, the yearly decision-making problem of a power producer to decide optimally its sales through forward contracts and in the pool, and the yearly decision-making problem of a retailer to decide its purchases through forward contracts and the selling price to its clients. Section III describes the mathematical structure0885-8950/$25.00 © 2009 IEEEMORALES et al.: SCENARIO REDUCTION FOR FUTURES MARKET TRADING IN ELECTRICITY MARKETS879of decision-making problems pertaining to electric energy futures markets. Section IV describes a commonly used and the proposed scenario reduction techniques. Section V provides three realistic case studies that illustrate the proposed scenario reduction technique, and compare it with a commonly used technique. Section VI provides some relevant conclusions that can be drawn from the study reported. An Appendix describes the forward scenario reduction algorithm [16].B. Producer Problem We consider a producer that seeks to determine which forward contracts should be signed (forward contract portfolio) through the futures market and, also, the speciﬁc involvement in the pool for each price-scenario realization. Mathematically, the problem of a producer can be formulated as a two-stage stochastic programming problem whose aim is to maximize its expected proﬁt subject to: 1) forward contracting constraints; 2) operating constraints; 3) energy balance constraints. For a detailed description of the optimization problem to be solved, we refer the reader to [1]. C. Retailer Problem The problem that a retailer has to face consists in determining its forward contract portfolio and the selling price to be offered to its potential clients. The retailer must cope with uncertain pool prices and client demands, as well as the possibility that clients might choose a different supplier if the selling price offered by the retailer is not sufﬁciently competitive. For the sake of simplicity, the client demands are assumed to be perfectly known (deterministic). After deciding the futures market involvement and selecting the selling price, the retailer must determine its purchases and sales in the pool. Note that the selection of the selling price constitutes a ﬁrst-stage decision. Under an optimization framework, the problem of a retailer can be stated as a two-stage stochastic programming problem consisting in the maximization of its expected proﬁt subject to: 1) forward contracting constraints; 2) client constraints; 3) energy balance constraints; 4) revenue constraints. A detailed description of the mathematical formulation of this problem is provided in [2]. III. MATHEMATICAL STRUCTURE For the sake of simplicity, the following mathematical development is carried out for the previously deﬁned two-stage stochastic programming problem faced by a producer. However, other stochastic programming models, as the one described in [2] for the retailer problem, have a similar mathematical structure. represents the different scenario realizations of the vector of electricity pool prices (stochastic process). Variable represents the vector of here-and-now decisions (e.g., the energy sold in the futures market through forward contracts), and represents the variable vector of the wait-and-see decisions (operating decisions and the energy sold in the pool). Note that pool decisions depend on price scenario realizations while futures is the revenue associated with market decisions do not. is the revenue selling energy in the futures market, while associated with selling in the pool. is the total production is the expectation operator over the cost of the producer. stochastic processes represented by scenarios indexed by . Sets , , and represent, respectively, the feasibility region of forward contracting, the feasibility region of pool trading andII. MOTIVATING MODELS As motivating examples, we consider the producer and retailer problems described in [1] and [2], respectively. First, we outline the characteristics shared by both problems and next, we provide a brief description of each one.A. Common Features The objective in both problems is to determine the participation in the futures market to hedge against the volatility of pool prices. A decision horizon of one year is considered. Forward contracting decisions are made on a monthly or quarterly basis. Within a futures market framework, a forward contract consists in a constant-power quantity to be sold during a future time period (e.g., 100 MW during the second quarter) at a given energy price (e.g., 50 /MWh). The set of decisions pertaining to the pool are made throughout the year. The futures market decisions are made prior to the knowledge of which future pool price scenario materializes, and therefore, they are ﬁrst-stage decisions (also called here-and-now decisions). Decisions pertaining to pool involvement are deferred in time and are considered to be made when a given price scenario materializes; therefore, they are second-stage decisions (usually referred to as wait-and-see decisions). We consider that day-ahead pool decisions are made with perfect information. For the sake of simplicity, in this paper no risk metric is considered in the formulation of the producer and retailer problems. However, the proposed scenario reduction technique is equally applicable to problems that do include risk treatment. For instance, risk management can be incorporated into the producer and retailer problems by maximizing the CVaR of the proﬁt distribution [23] instead of the expected proﬁt. In this case, since the value of the CVaR just depends on the lowest proﬁt scenarios and their probabilities, the proposed scenario reduction technique can be easily modiﬁed so that those few scenarios required to determine the CVaR are selected ﬁrst. Preliminary results suggest an efﬁcient behavior of the algorithm for cases involving high or low risk aversion (conﬁdence level above 0.8 and below 0.5, respectively), and not that efﬁcient behavior for cases with medium risk aversion (conﬁdence level between 0.5 and 0.8). Likewise, for risk-constrained electricity-market problems, where risk management is implemented by means of constraints, an equivalent formulation in which risk control is transferred to the objective function should be used in order to apply successfully the proposed technique.880IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 24, NO. 2, MAY 2009the operating constraints of the producer. This problem is formulated as (1) (2) where(3)yields an optimal solution close in value to the solution to the original problem. In two-stage stochastic linear programming problems, it is possible to reduce a large scenario set to a simpler one that is close to the original one if measured by a so-called probability distance. Under mild conditions on the problem data, it can be shown that the optimal value of the simpler problem (considering the reduced scenario set) is close to the value of the solution to the original problem (considering the original scenario set) if the scenario sets are sufﬁciently close in terms of the probability distance [17]. The most common probability distance used in stochastic op, deﬁned between timization is the Kantorovich distance, by the problem two probability distributions and(4) Objective function (1) represents the expected proﬁt of the producer, which is the sum of the revenue from selling in the futures market and, as expressed by (3), the expected revenue from selling in the pool minus the expected production cost. Constraints (2) impose the feasibility conditions pertaining to the futures market, and constraints (4) enforce the feasibility conditions pertaining to the pool and the operating constraints of the producer. Under rather general assumptions [11], the maximization and expectation operators can be swapped in (3). Then, the twostage stochastic programming problem (1)–(4) is conveniently formulated as the deterministic equivalent problem stated as follows: (5)(9) Problem (9) is known as Monge–Kantorovich mass transportation problem. Further details on this problem are provided is a nonnegative, continuous, symmetric in [24]. In (9), function, often referred to as cost function, and the inﬁmum is . taken over all joint probability distributions deﬁned on can only be properly called Kantorovich disNote that tance if function is given by a norm. and are ﬁnite distributions correIn the case where , respectively, the sponding to the sets of scenarios and Kantorovich distance is obtained by solving (see [17])(6) If just one single scenario is considered, e.g., scenario , the problem above becomes (7) (10) (8) The single-scenario problem (7), (8) is much easier to solve than the multi-scenario problem (5), (6) as its number of variables and constraints is comparatively much smaller. IV. SCENARIO REDUCTION A scenario set that properly represents the uncertainty involved in a decision-making problem and that is obtained by running a random scenario-generation process is typically large, resulting in an optimization model that may be intractable. To attain tractability, we seek to reduce the number of scenarios while still retaining the essential features of the original scenario set. In other words, we seek a reduced scenario set that where and represent the probabilities of scenarios and in sets and , respectively. For a two-stage problem with stochasticity pertaining to prices and right-hand sides, with corresponding to an initial being a reduced set, , the set of scenarios and Kantorovich distance can be equivalently determined as [17](11) As outlined in [16], expression (11) can be used to derive several heuristics for generating reduced scenario sets that are closeMORALES et al.: SCENARIO REDUCTION FOR FUTURES MARKET TRADING IN ELECTRICITY MARKETS881to an original set. In this paper, we focus on the forward selection algorithm as described in [16]. This algorithm is an iterative greedy process starting with an empty set. In each iteration, from , the scenario which the set of nonselected scenarios minimizes the Kantorovich distance between the reduced and original sets is selected. Then, this scenario is included in the . The algorithm stops if either a speciﬁed number reduced set of scenarios or a certain Kantorovich distance is attained. Note that this scenario reduction technique is a heuristic, with no known performance guarantee. The reduced scenario set generated by the forward selection algorithm is not guaranteed to be the closest in the Kantorovich distance to the original set (over all reduced sets of the same cardinality). Moreover, we have no guarantee that the reduced set gives a good approximation to the optimal value of the original problem. Nevertheless, the empirical results reported in the literature (e.g., in [16]) indicate that the reduced sets deﬁned by the forward selection algorithm perform well in practice. Two scenario reduction techniques are explained in this section. The ﬁrst one is a well-established algorithm presented in [16], while the second one is the algorithm proposed in this paper. Both are based on the forward selection algorithm provided in [16], whose mathematical formulation is stated in the Appendix.B. Algorithm 2: Reduction Based on the Objective Function of a Single-Scenario Problem In this paper the scenario reduction technique based on the forward selection algorithm described in [16] is used from a different point of view. Let us consider a stochastic program, that includes the random vector ming problem, denoted by previously deﬁned. We also deﬁne as the deterministic expected-value problem associated with , i.e., is equal in which the random vector is replaced by to problem . its expected value, In the forward selection algorithm as described in [16] the is expressed by the distance between two scenarios and and is computed according to the difference function between pairs of random vectors. In contrast, the scenario reduction technique proposed in this paper seeks to account for in the impact of each single realization of the random vector . the objective function of problem as follows: For this purpose, we deﬁne the function(13) is the optimal value of the objective function of where if the random vector is replaced by its realizaproblem , and ﬁrst-stage variables are ﬁxed to the tion in scenario , . In other words, optimal values obtained from solving is the objective value of the expected-value solution (solution ) under scenario . The problem associated with sceof . In general, note that the family of nario is denoted by is much easier to solve than the source problem problems . Likewise, ﬁrst-stage variables are ﬁxed to the solution of , which constitutes a ﬁrst approximation of the problem optimal values of these variables, and allows us to evaluate easily each scenario in terms of the objective function value (the target measure) of the problem corresponding to that scenario. The rationale of this scenario reduction technique is as follows. , as1) Solve the deterministic expected-value problem, sociated with the original stochastic problem, . 2) Evaluate the solution from 1) under scenario , i.e., solve corresponding to each the single-scenario problem . The optimal objective function value of scenario this problem, , characterizes the scenario . 3) Select the scenario that if included in the reduced set of scenarios minimizes the distance (11) between this new reand the original one using the function duced set deﬁned in (13). 4) Repeat 3) until a sufﬁcient number of scenarios is selected. 5) Update the probability associated with the selected scenarios as stated in the Appendix. It should be noted that (13) characterizes the novel variant of the forward selection algorithm proposed in this paper. Finally, note that the proposed scenario-reduction strategy resembles a single subproblem iteration of a Benders’ decomposition scheme relying on solving single-scenario subproblems. However, the proposed scenario-reduction strategy has the important advantage of not requiring a convex subproblem, whichA. Algorithm 1: Reduction Based on the Norm of the Difference Between Pairs of Random Vectors Let us consider the vector of random variables . For instance, this random vector may correspond to a stochastic process representing pool prices or periods. We asdemands throughout a year divided into sume that this random vector is characterized by an initial set , . of scenarios According to [16], if(12) gives the Wasserstein metric of order , which can be shown to have some appealing properties for approximating stochastic optimization problems [15]. The rationale of the scenario reduction based on the difference between pairs of random vectors is as follows. 1) Select the scenario that if included in the reduced set of scenarios minimizes the distance (11) between this new reand the original one using the function duced set , deﬁned in (12) as the norm of the difference between each pair of random vectors. 2) Repeat 1) until a sufﬁcient number of scenarios is selected. 3) Update the probability associated with the selected scenarios as described in the Appendix. Finally, note that considering [16] and accounting for the fact that the problems addressed in this paper present only stochasticity in the objective function (see Section III), the value is selected to compute the value of the function in (12).882IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 24, NO. 2, MAY 2009is a convergence requirement of any Benders’ decomposition algorithm. Moreover, as opposed to Benders’ decomposition, the proposed procedure does not rely on an iterative mechanism. C. Theoretical Background Algorithm 1 is based on extensive qualitative and quantitative stability results for optimal values and optimal solutions of convex stochastic programming problems with respect to perturbations of the underlying probability distributions. These stability results are achieved by measuring those perturbations in terms of an appropriate probability metric [27]. Thus, under these stability criteria, the problem of optimal scenario reduction boils down to determining a scenario subset of prescribed cardinality or accuracy and assign new probabilities to the preserved scenarios such that the corresponding reduced probais the closest to the original distribution bility distribution in terms of a probability distance [18]. As previously mentioned, the Kantorovich distance deﬁned in (9) is commonly used for this purpose. The development of a similar stability analysis for Algorithm 2 is out of the scope of this paper. Nevertheless, it should be noted that this algorithm takes advantage of the good performance of the forward scenario selection described in [16] to reduce the Kantorovich distance between the probability distributhat naturally comes up if these are deﬁned on tions and the set of objective function values associated to the set of rethrough problems . In alizations of stochastic process this new context, in which the set of objective function values can be seen as the set of realizations of a random variable denoted by with probability distribution , some results of the stability analysis supporting Algorithm 1 can constitute the starting point of a potential theoretical support for Algorithm 2. D. Comparison The computational burden of Algorithm 1 is low as it requires just calculating an appropriate norm of the difference between each pair of random vector scenarios. On the other hand, Algorithm 2 requires the solution of the expected-value problem and the solution of one single-scenario optimization problem per scenario; thus, its computational burden is higher than that pertaining to Algorithm 1. Nevertheless, note that the single-scenario problems are computationally simple because, beyond having a comparatively low number of constraints and variables, their ﬁrst-stage variables are ﬁxed to the values obtained from solving the expected-value problem. Moreover, detailed numerical results show that the ability of Algorithm 2 to locate the key scenarios that stabilize the expected value of the objective function (as well as its standard deviation) is higher than that of Algorithm 1. The performances of both algorithms are comprehensively compared in the case studies below. Finally, it should be emphasized that the aim of reducing scenarios is to attain tractability rather than to improve the computational efﬁciency. V. CASE STUDIES In order to compare the two scenario reduction algorithms described above, the two different stochastic programming prob-Fig. 1. Pool price scenarios for the producer problem.lems described in Section II are used. The ﬁrst problem addresses the optimal involvement in a futures electricity market of a power producer [1]. The aim of the second one is to decide which forward contracts should be signed by a retailer and at which price it should sell electricity to its clients in order to maximize its expected proﬁt [2]. Two scenario-generation techniques are used for the sake of illustration in the case studies: ARIMA and heuristic. However, note that no attempt is made to compare these two scenariogeneration procedures. A. Power Producer The case study of the power producer reported below is carried out considering the data in [1]. Fig. 1 shows the 200 pool price scenarios generated according to the heuristic procedure explained in [1, Appendix A]. Each of these scenarios contains 72 values representing the pool price throughout one year. Fig. 2 provides the expected proﬁt evolution with the number of scenarios for Algorithms 1 and 2, while Fig. 3 provides the evolution of the standard deviation of the proﬁt with the number of scenarios for Algorithms 1 and 2. From Figs. 2 and 3, it can be concluded that Algorithm 2 stabilizes both the expected proﬁt and its standard deviation faster than Algorithm 1. Moreover, Algorithm 2 achieves a good solution in terms of expected proﬁt and proﬁt standard deviation with just a few scenarios (e.g., 30), and does not exhibit an oscillatory behavior. On the contrary, Algorithm 1 requires a rather high number of scenarios to achieve a good solution (e.g., 100) and suffers an unpredictable oscillatory behavior. Fig. 4 provides different probability mass functions (pmf) of the proﬁt for different number of scenarios and Algorithms 1 and 2. To represent the pmf, proﬁt intervals of 1/15 per unit are used. Each bar provides the sum of the probabilities of the scenarios yielding a proﬁt within the interval deﬁned by the base of the bar. The upper subplot provides the proﬁt pmf considering all 200 scenarios. The two central subplots are similar to the upper one but considering 35 and 100 scenarios, respectively, obtained using Algorithm 1. The two lower subplots provide analogousMORALES et al.: SCENARIO REDUCTION FOR FUTURES MARKET TRADING IN ELECTRICITY MARKETS883Fig. 2. Expected proﬁt as a function of the number of scenarios for the producer problem.Fig. 4. Probability mass function of the proﬁt for different number of scenarios for the producer problem. Fig. 3. Proﬁt standard deviation as a function of the number of scenarios for the producer problem.B. Retailer The data corresponding to the case study of the retailer are provided in [2]. In this case study the client demand is considered deterministic. Fig. 6 contains 200 pool price scenarios generated with the ARIMA model proposed in [2]. As in the case of the producer problem, these scenarios contain 72 values representing the pool price throughout one year. Similar plots to those presented for the producer problem are generated for the reduction of the pool price scenarios of the retailer. Figs. 7 and 8 represent the evolution of the expected proﬁt and the standard deviation of the proﬁt, respectively, as a function of the number of scenarios for each algorithm. It can be noted that the expected proﬁt stabilizes faster if the scenarios are selected by Algorithm 2 than if they are selected using Algorithm 1. As for the evolution of the proﬁt standard deviation, both algorithms present similar behavior. Nevertheless, this behavior is somewhat oscillatory for Algorithm 1. Fig. 9 is analogous to Fig. 4, but considering 30 and 60 scenarios for the central and lower subplots. Note that for 30 scenarios, Algorithm 2information as the central subplots but using Algorithm 2 to reduce the number of scenarios. Note that the superiority of Algorithm 2 with respect to Algorithm 1 in reproducing the shape of the proﬁt pmf is apparent. Note also that the scale of the vertical axis of all plots are identical. Fig. 5 shows the evolution of the distance, normalized with respect to the maximum distance, of the reduced scenario set to the original scenario set as a function of the number of scenarios for Algorithms 1 and 2 according to (11) by using cost functions (12) and (13), respectively. Algorithm 2 reaches 20% distance between the original and the reduced sets with fewer than ten scenarios and 10% with less than 20 scenarios, while Algorithm 1 requires more than 140 and 170 scenarios, respectively, to reach these distances. Nevertheless, caution should be exercised while comparing distances based on (12) with distances based on (13) as they come up from different approaches (see Section IV-C).。

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1 Introduction
Statistical data analysis has provided convincing evidence of long-tailed (subexponential) tra c characteristics in high-speed communication networks. Early indications of the long-range dependence of Ethernet tra c, attributed to long-tailed le size distributions, were reported in Leland et al. 21]. Long-tailed characteristics of the scene length distribution of MPEG video streams were explored in Heyman & Lakshman 15] and Jelenkovic et al. 18]. These empirical ndings have encouraged active theoretical developments in the modeling and queueing analysis of long-tailed tra c phenomena. We refer to Boxma & Dumas 9] for a comprehensive survey on uid queues with long-tailed arrival processes. See also Jelenkovic 16] for an extensive list of references on subexponential queueing models. Despite signi cant progress, however, the practical implications are not yet thoroughly understood, in particular issues relating to control and priority mechanisms in the network. To gain a better understanding of those issues, the present paper analyzes the queueing behavior of long-tailed tra c ows under the Generalized Processor Sharing (GPS) discipline. As a design paradigm, GPS is at the heart of commonly-used scheduling algorithms for high-speed switches, such as Weighted Fair Queueing, see for instance Parekh & Gallager 25, 26]. The impact of priority and scheduling mechanisms on long-tailed tra c phenomena has received relatively little attention. Some recent studies have investigated the e ect of the scheduling discipline on the waiting-time distribution in the classical M/G/1 queue, see for instance Anantharam 2]. For FCFS, it is well-known (see Cohen 13]) that the waiting-time tail is regularly varying of index 1 ? i the service time tail is regularly varying of index ? . For LCFS preemptive resume as well as for Processor Sharing, the waiting-time tail turns out to be regularly varying of the same index as the service time tail, see Boxma & Cohen 8], and Zwart & Boxma 32], although with di erent pre-factors. In the case of Processor Sharing with several customer classes, Zwart 29] showed that the sojourn time distribution of a class-i customer is regularly varying of index ? i i the service time distribution of that class is regularly varying of index ? i , regardless of the service time distributions of the other classes. In contrast, for two customer classes with ordinary non-preemptive priority, the tail behavior of the waitingand sojourn time distributions is determined by the heaviest of the (regularly-varying) service time distributions, see Abate & Whitt 1]. In the present paper, we consider the Generalized Processor Sharing (GPS) discipline. GPSbased scheduling algorithms, such as Weighted Fair Queueing, play a major role in achieving di erentiated quality-of-service in integrated-services networks. The queueing analysis of GPS is extremely di cult. Interesting partial results for exponential tra c models were obtained in Bertsimas et al. 3], Dupuis & Ramanan 14], Massoulie 22], Zhang 27], and Zhang et al. 28]. Here, we focus on non-exponential tra c models. We show that, in certain scenarios, a ow may be strongly a ected by the activity of `heavier'-tailed ows, and may inherit their traf2
Probability, Networks and Algorithms (PNA)
004 June 30, 2000
Report PNA-R0004 ISSN 1386-3711 CWI P.O. Box 94079 1090 GB Amsterdam The Netherlands
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Induced Burstiness in Generalized Processor Sharing Queues with Long-Tailed Tra c Flows
Sem Borst ; ;y, Onno Boxma ; , Predrag Jelenkovicz CWI P.O. Box 94079, 1090 GB Amsterdam, The Netherlands Department of Mathematics & Computing Science Eindhoven University of Technology P.O. Box 513, 5600 MB Eindhoven, The Netherlands y Bell Laboratories, Lucent Technologies P.O. Box 636, Murray Hill, NJ 07974, USA z Department of Electrical Engineering Columbia University New York, NY 10027, USA