RF3417;中文规格书,Datasheet资料

合集下载

集成运放组成的基本运算电路

K2
C 1μF
R2 1M
K1 +15V
vS
－
R1 100K
A
vO
＋
R′ 100K
-15V
vo
1 R1
t
0 vsdt
积分运算电路
4. 积分运算电路
将实验数据及波形填入下述表格中：
vs波形
vs幅度值
vo波形
vo频率
vo幅度值
5. 用积分电路转换方波为三角波
电路如下图所示。图中电阻R2的接入是为了抑制由 IIO、VIO所造成的积分漂移，从而稳定运放的输出零点。
A
vO
υS
＋
R′ 10K
-15V
v0
(1
RF R1
)vs
同相比例运算电路
2. 实现同相比例运算
将实验数据及波形填入下述表格中：
输入信号vs1 (V)
有效值
波形
输入信号vs2 (V)
有效值
波形
有效值
输出电压vo (V)
峰值
波形
注：上表针对正弦波输入，若是其他信号输入表作相应改变。
3. 减法器（差分放大电路）
减法器（差分放大电路）运算仿真电路
3. 减法器（差分放大电路）
减法器（差分放大电路）运算仿真电路
3. 减法器（差分放大电路）
将实验数据及波形填入下述表格中：
输入信号vs1 (V)
有效值
波形
输入信号vs2 (V)
ቤተ መጻሕፍቲ ባይዱ
有效值
波形
有效值
输出电压vo (V)
峰值
波形
注：上表针对正弦波输入，若是其他信号输入表作相应改变。
vs波形

MC34167MC33167中文资料

MC34167 MC331671简介该MC34167, MC33167系列单片电源开关可用于dc–to–dc优化调节器申请.这些器件的固定频率，电压模式稳压器包含了所有的积极作用需要直接和实施step–down以最小的转换数量voltage–inverting外部元件.它们也可以用于成本效益在step–up转换器应用.潜在市场包括汽车，计算机，工业和成本敏感的消费产品.每一个设备的部分介绍给下面与代表框图所示图13.2振荡器振荡器频率内部编程72 kHz的电容CT和修剪电流源.该充放电率控制在产生一个95%在开关输出的最大占空比.在CT的放电，振荡器产生内部消隐脉冲持有的反相输入与门高，禁用输出开关晶体管.标称振荡器峰值和山谷门槛4.1 V和2.3 V分别.3脉宽调制器脉宽调制器由一个比较器振荡器斜坡电压施加到非反相输入端，而误差放大器的输出应用到反相输入.输出开关导通时启动CT检查排放到振荡器峰谷电压.至于收费的CT电压超过误差放大器的输出，锁存复位，终止输出晶体管的导通时间振荡器的ramp–up时期.这PWM /锁存结合防止在给定的多输出脉冲振荡器时钟周期.数字6和14说明开关输出电压与占空比的补偿.4电流检测该系列采用MC34167当前cycle–by–cycle限制，作为保护手段输出开关晶体管从过度紧张.在每个周期视为一个单独的情况.电流限制是通过监测输出开关晶体管的电流传导期间建设，并经检测过流情况，请立即关闭为振荡器的ramp–up期内开关.集电极电流转换为电压由内部微调电阻和对一个参考比较由电流检测比较器.当电流限制达到阈值，比较器重置PWM 锁存.限流门限点往往设在6.5 A.图9说明开关与输出电流限制门槛温度.5误差放大器和参考一个误差放大器的高增益提供了访问反相输入和输出.该放大器具有典型dc电压增益80 dB,和单位增益带宽600 kHz与相边缘 70度（图3).同相输入偏置内部5.05 V参考并且不固定了.参考具有精度±2.0%在室温下.以提供负载5.0 V中，参考编程50以上mV 5.0 V补偿在电缆的电压降和1.0%从连接器转换器输出.如果转换器设计需要一个输出电压高于5.05 V,电阻更大R1必须加入形成一个分压网络的反馈输入中所示数字13和18.了确定输出方程与分压网络的电压为：Vout+5.05R2R1)1外部回路补偿所需的转换器稳定.一个简单的low–pass滤波器是由连接电阻(R2)从稳压输出到反相输入，以及一系列resistor–capacitor (RF, CF)之间Pins 1和5.补偿网络的元件值显示在电路的申请被选定为each在稳定工作条件下进行测试.该step–down转换器（图18)是最容易补偿稳定.该step–up（图20)和voltage–inverting（图22)配置运作，连续导反激式转换器，而且更难以弥补.该最简单的方法来优化网络是补偿观察输出电压的负载响应一步变化，而调整临界阻尼RF和CF.该最终电路应验证以下四个稳定边界条件.这些条件是最小和最大输入电压，最小和最大负载.通过箝位的电压误差放大器的输出（引脚5)不到150 mV,内部电路将放置到一个低功耗待机模式，从而将权力电源电流36µA与12 V电源电压.图10说明了备用电源电流与电源电压.误差放大器的输出有一个100µA电流源pull–up，可用于实现soft–start.图17显示充电电流源通过一个电容CSS系列二极管.该二极管断开从反馈CSS回路电阻时1.0 M操作它上面的收费销5.范围开关输出输出开关晶体管的设计最大的40 V,以最小的峰值集电极电流时5.5 A.配置为step–down或voltage–inverting应用，如在图18和22,电感会把偏置的输出整流开关关闭时.整流器与较高的正向电压降或长期拖延的时间应该打开不能使用.如果发射器被允许去充分负，集电极电流流过，造成额外的装置暖气，降低转换效率.图8显示到箝位的发射器0.5集电极电流V,在一系列的100µA温度过高.阿1N5825或肖特基势垒整流器相当于推荐履行这些要求.欠压分离欠压分离一直比较成立以保证完全集成电路在输出级的功能已启用.内部参考电压比较器的监测使输出阶段VCC超过5.9 V.为了防止不稳定的输出交叉切换的阈值，0.9 V迟滞.6摩托罗拉设备数据模拟ICMC34167 MC33167热保护内部热关断电路，以保护在事件集成电路的最大结温度超过.当被激活时，通常在170°C,是被迫的锁存成'复位'的状态，关闭输出开关.此功能防止灾难性故障提供偶然的设备过热.它的目的不是要作为一个适当的散热片的替代品.该MC34167包含在5–lead TO–220类型包装.该标签包装是很常见的中心引脚（引脚3)，通常连接到地.设计考虑不要试图建立一个转换器上wire–wrap或plug–in原型板.特别应注意分开的信号电流和接地接地通路从负载电流路径.所有高电流回路应尽可能短尽可能使用重型铜runs到尽量减少振荡和辐射EMI.为了获得最佳的操作，严密元件布局建议.电容器Cin, CO,和所有的反馈元件应尽可能靠近IC在身体可能.这也是必须的肖特基二极管连接到开关输出是尽可能靠近尽可能IC.图15.低功耗待机电路+100µA错误放大器1图16.过电压关断电路+100µA错误放大器1120补偿5120补偿R15R1I =待机模式VShutdown = VZener + 0.7图17. Soft–Start电路+100µA错误放大器1120补偿D2Vin1.0 MCss5D1R1tSoft–Start≈35,000 Css。

RF3147资料

Product DescriptionOrdering InformationTypical Applications FeaturesFunctional Block DiagramRF Micro Devices, Inc.7628 Thorndike RoadGreensboro, NC 27409, USATel (336) 664 1233Fax (336) 664 0454Optimum Technology Matching® AppliedSi BJT GaAs MESFET GaAs HBTSi Bi-CMOS SiGe HBTSi CMOSInGaP/HBTGaN HEMTSiGe Bi-CMOSDCS/PCS INBAND SELECT TX ENABLE VRAMP VBATT GSM IN VBATT TRI-BAND GSM900/DCS/PCSPOWER AMP MODULE•3V Tri-Band GSM Handsets •Commercial and Consumer Systems •Portable Battery-Powered Equipment •EGSM900/DCS/PCS Products •GPRS Class 12 Compatible •Power Star TM ModuleThe RF3147 is a high-power, high-efficiency power ampli-fier module with integrated power control that provides over 50dB of control range. The device is a self-contained 7mmx7mmx0.9mm lead frame module (LFM) with 50Ωinput and output terminals. The device is designed for use as the final RF amplifier in EGSM900, DCS and PCS handheld digital cellular equipment and other applications in the 880MHz to 915MHz, 1710MHz to 1785MHz and 1850MHz to 1910MHz bands. With the integration of a V RAMP limiting circuit, the RF3147 can regulate the V RAMP voltage to ensure minimum switching transients.The V RAMP limiter function is fully integrated into the CMOS controller and requires no additional inputs from the user.•Integrated V BATT Tracking Circuit •Complete Power Control Solution •+35dBm GSM Output Power at 3.5V•+33dBm DCS/PCS Output Power at 3.5V •60% GSM and 55% DCS/PCS EFF •7mmx7mmx0.9mm Package SizeRF3147Tri-Band GSM900/DCS/PCS Power Amp Module RF3147 SB Power Amp Module 5-Piece Sample Pack RF3147PCBA-41XFully Assembled Evaluation BoardShaded lead is pin 1.0.600.24Package Style: LFM, 48-Pin, 7mm x7mmx0.9mm99Absolute Maximum RatingsParameterRatingUnitSupply Voltage-0.3 to +6.0V DC Power Control Voltage (V RAMP )-0.3 to +1.8V Input RF Power +10dBm Max Duty Cycle50%Output Load VSWR10:1Operating Case Temperature -20 to +85°C Storage Temperature-55 to +150°CParameterSpecification Unit ConditionMin.Typ.Max.Overall Power Control V RAMPPower Control “ON” 2.1V Max. P OUT , Voltage supplied to the input Power Control “OFF”0.20.25V Min. P OUT , Voltage supplied to the input V RAMP Input Capacitance 1520pF DC to 2MHz V RAMP Input Current 10µA V RAMP =2.1VT urn On/Off Time 2µs V RAMP =0.2V to 2.1VTX Enable “ON” 1.9V TX Enable “OFF”0.5V GSM Band Enable0.5V DCS/PCS Band Enable1.9V Overall Power SupplyPower Supply Voltage 3.5V SpecificationsV Nominal operating limitsPower Supply Current1µA P IN <-30dBm, TX Enable=Low, Temp=-20°C to +85°CmAV RAMP =0.2V , TX Enable=HighOverall Control SignalsBand Select “Low”000.5V Band Select “High”1.92.03.0V Band Select “High” Current 2050µA TX Enable “Low”000.5V TX Enable “High”1.92.03.0V TX Enable “High” Current12µAESD sensitive device.RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).ParameterSpecificationUnit Condition Min.Typ.Max.Overall (GSM900 Mode)Temp=+25°C, V BATT=3.5V,V RAMP=2.1V, P IN=3dBm, Freq=880MHz to 915MHz,25% Duty Cycle, Pulse Width=1154µsOperating Frequency Range880 to 915MHzMaximum Output Power+34.2dBm Temp = 25°C, V BATT=3.5V,V RAMP=2.1V+32.0dBm Temp=+85°C, V BATT=3.0V,V RAMP =2.1VT otal Efficiency58%At P OUT MAX, V BATT=3.5VInput Power Range0+3+5dBm Maximum output power guaranteed at mini-mum drive levelOutput Noise Power-86dBm RBW=100kHz, 925MHz to 935MHz,P OUT > +5dBm-88dBm RBW=100kHz, 935MHz to 960MHz,P OUT > +5dBmForward Isolation 1-45-30dBm TXEnable=Low, P IN=+5dBmForward Isolation 2-30-15dBm TXEnable=High, V RAMP=0.2V, P IN=+5dBm Cross Band Isolation 2f0 -17dBm V RAMP=0.2V to V RAMP_R PSecond Harmonic-15-6dBm V RAMP=0.2V to V RAMP_R PThird Harmonic-25-9dBm V RAMP=0.2V to V RAMP_R PAll OtherNon-Harmonic Spurious-36dBm V RAMP=0.2V to 2.1VInput Impedance50ΩInput VSWR 2.5:1V RAMP=0.2V to 2.1VOutput Load VSWR Stability8:1Spurious<-36dBm, RBW=3MHzSet V RAMP where P OUT<34.2dBm into 50ΩloadOutput Load VSWR Ruggedness10:1Set V RAMP where P OUT<34.2dBm into 50Ωload. No damage or permanent degradationto part.Output Load Impedance50ΩLoad impedance presented at RF OUT pad Power Control V RAMPPower Control Range50dB V RAMP=0.2V to 2.1VNotes:V RAMP_R P=V RAMP set for 34.2dBm at nominal conditions.ParameterSpecificationUnit Condition Min.Typ.Max.Overall (DCS Mode)Temp=25°C, V BA TT=3.5V,V RAMP=2.1V, P IN=3dBm,Freq=1710MHz to 1785MHz,25% Duty Cycle, pulse width=1154µsOperating Frequency Range1710 to 1785MHzMaximum Output Power+32.0dBm Temp=25°C, V BA TT=3.5V,V RAMP =2.1V+30.0dBm Temp=+85°C, V BA TT=3.0V,V RAMP=2.1VT otal Efficiency50%At P OUT MAX, V BA TT=3.5VInput Power Range0+3+5dBm Maximum output power guaranteed at mini-mum drive levelOutput Noise Power-85dBm RBW=100kHz, 1805MHz to 1880MHz,P OUT > 0dBm,V BA TT=3.5VForward Isolation 1-50-30dBm TXEnable=Low, P IN=+5dBmForward Isolation 2-25-15dBm TXEnable=High, V RAMP=0.2V, P IN=+5dBm Second Harmonic-15-5dBm V RAMP=0.2V to V RAMP_R PThird Harmonic-20-10dBm V RAMP=0.2V to V RAMP_R PAll OtherNon-Harmonic Spurious-36dBm V RAMP=0.2V to 2.1VInput Impedance50ΩInput VSWR 2.5:1V RAMP=0.2V to 2.1VOutput Load VSWR Stability8:1Spurious<-36dBm, RBW=3MHzSet V RAMP where P OUT<32dBm into 50ΩloadOutput Load VSWR Ruggedness10:1Set V RAMP where P OUT<32dBm into 50Ωload. No damage or permanent degradationto part.Output Load Impedance50ΩLoad impedance presented at RF OUT pin Power Control V RAMPPower Control Range50dB V RAMP=0.2V to 2.1V, P IN=+5dBmNotes:V RAMP_R P=V RAMP set for 32dBm at nominal conditions.ParameterSpecificationUnit Condition Min.Typ.Max.Overall (PCS Mode)Temp=25°C, V BA TT=3.5V,V RAMP =2.1V, P IN=3dBm, Freq=1850MHz to 1910MHz,25% Duty Cycle, pulse width=1154µsOperating Frequency Range1850 to 1910MHzMaximum Output Power+32.0dBm Temp=25°C, V BA TT=3.5V,V RAMP=2.1V, 1850MHz to 1910MHz+30.0dBm Temp=+85°C, V BA TT=3.0V,V RAMP=2.1VT otal Efficiency52%At P OUT MAX, V BA TT=3.5VInput Power Range0+3+5dBm Full output power guaranteed at minimumdrive levelOutput Noise Power-85dBm RBW=100kHz, 1930MHz to 1990MHz,P OUT > 0dBm,V BA TT=3.5VForward Isolation 1-40-28dBm TX_ENABLE=Low, P IN=+5dBmForward Isolation 2-20-15dBm TXEnable=High, V RAMP=0.2V, P IN=+5dBm Second Harmonic-15-8dBm V RAMP=0.2V to V RAMP_R PThird Harmonic-20-10dBm V RAMP=0.2V to V RAMP_R PAll OtherNon-Harmonic Spurious-36dBm V RAMP=0.2V to 2.1VInput Impedance50ΩInput VSWR 2.5:1V RAMP=0.2V to 2.1VOutput Load VSWR Stability8:1Spurious<-36dBm, RBW=3MHzSet V RAMP where P OUT<32dBm into 50ΩloadOutput Load VSWR Ruggedness10:1Set V RAMP where P OUT<32dBm into 50Ωload. No damage or permanent degradationto part.Output Load Impedance50ΩLoad impedance presented at RF OUT pin Power Control V RAMPPower Control Range50dB V RAMP=0.2V to 2.1V, P IN=+5dBmNotes:V RAMP_R P=V RAMP set for 32dBm at nominal conditions.Pin Out123456789101112131415161718192021222324252627282930313233343536373839404142434445464748GSM900 OUT NC VCC2 GSM NC GND GND GND NC NC NC NC NC N CN CN CN CN CV C C 3 G S MV C C O U TV C C O U TV C C 3D C S /P C SN CN CN CNCNC NC NC NC NC GND GNDGND GND DCS/PCS OUT D C S /P C S I N VCC2 DCS/PCS G N DG N D 1 G S M B A N D S E LT X E N A B L EV B A T TV B A T TN CV R A M Pv c c 1 G S MG S M 900 I NV C C 1D C S /P C SApplication SchematicEvaluation Board SchematicEvaluation Board LayoutBoard Size 2.0” x 2.0”Board Thickness 0.032”, Board Material FR-4, Multi-LayerTheory of OperationOverviewThe RF3147 is a tri-band EGSM900, DCS1800, and PCS1900 power amplifier module that incorporates an indirect closed loop method of power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop appears as an open loop to the user and can be driven directly from the DAC output in the baseband circuit.Theory of OperationThe indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power con-trol systems in GSM sense either forward power or collector/drain current. The RF3147 does not use a power detector. A high-speed control loop is incorporated to regulate the collector voltage of the amplifier while the stage are held at a con-stant bias. The V RAMP signal is multiplied by a factor of 2.75 and the collector voltage for the second and third stages are regulated to the multiplied V RAMP voltage. The basic circuit is shown in the following diagram.By regulating the power, the stages are held in saturation across all power levels. As the required output power is decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3147 regu-lating collector voltage, the dominant mode of power fluctuations is eliminated.(Eq. 1)There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of them are:•Current draw and system efficiency •Power variation due to Supply Voltage •Power variation due to frequency •Power variation due to temperature •Input impedance variation •Noise power •Loop stability•Loop bandwidth variations across power levels •Burst timing and transient spectrum trade offs •HarmonicsVV P dBm102V CC V SAT –⋅()28R LOAD 103–⋅⋅-------------------------------------------log ⋅=Output power does not vary due to supply voltage under normal operating conditions if V RAMP is sufficiently lower than V BA TT . By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower power range the maximum output power from the PA will also drop slightly. In this case it is important to also decrease V RAMP to prevent the power control from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with V RAMP .The switching transients due to low battery conditions are regulated by the V RAMP limiter circuit. The V RAMP limiter, a new feature for the RF3147, consists of a feedback loop that detects FET saturation. As the FET approaches saturation,the limiter adjusts the V RAMP voltage in order to ensure minimum switching transients. The V RAMP limiter is integrated into the CMOS controller and requires no additional input from the user.Due to reactive output matches, there are output power variations across frequency. There are a number of components that can make the effects greater or less. Power variation straight out of the RF3147 is shown in the tables below.The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional cou-plers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3147 does not use a directional coupler with a diode detector, these variations do not occur.Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where C BE and C CB (C GS and C SG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations presented to the VCO.The RF3147 presents a very constant load to the VCO. This is because all stages of the RF3147 are run at constant bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier.Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 2),(Eq. 2)the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3147 is kept constantthe gain in the first stage is always high and the overall noise power is not increased when decreasing output power.Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing.In conventional architectures the PA gain (dB/V) varies across different power levels, and as a result the loop bandwidth also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope regions which often causes instability at high slope regions.The RF3147 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector voltage do not vary.F TOT F 1F 21–G 1---------------F 31–G 1G 2⋅-------------------++=An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3147 is insensitive to a change in input power and the burst timing is constant and requires no software compensation.Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If the control slope of a PA has an inflection point within the output power range or if the slope is simply too steep it is diffi-cult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly biased so inflection points are nonexistent.Harmonics are natural products of high efficiency power amplifier design. An ideal class “E” saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as well. With most power control methods a peak power diode detector is used to rectify and sense forward power. Through the rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF3147 address this by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent the maximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of the transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. Should a problem arise, these terminations should be explored.PCB Design RequirementsPCB Surface FinishThe PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. T ypical thickness is 3µinch to 8µinch gold over 180µinch nickel.PCB Land Pattern RecommendationPCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.PCB Metal Land PatternA = 0.64 x 0.28 (mm) Typ.B = 0.28 x 0.64 (mm) Typ.C = 5.65 (mm) Sq.Figure 1. PCB Metal Land Pattern (Top View)PCB Solder Mask PatternLiquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.A = 0.74 x 0.38 (mm) Typ.B = 0.38 x 0.74 (mm) Typ.C = 5.65 x 2.20 (mm)Figure 2. PCB Solder Mask Pattern (Top View)Thermal Pad and Via DesignThermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies.The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.。

IRMCF341TR;IRMCF341TY;中文规格书,Datasheet资料

Data Sheet No. PD60304IRMCF341 Sensorless Motor Control IC for AppliancesFeaturesMCE TM (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Supports both interior and surface permanent magnet motorsBuilt-in hardware peripheral for single shunt current feedback reconstructionNo external current or voltage sensing operational amplifier requiredThree/two-phase Space Vector PWMThree-channel analog output (PWM)Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine controlJTAG programming port for emulation/debugger Serial communication interface (UART)I2C/SPI serial interfaceWatchdog timer with independent analog clockThree general purpose timers/countersTwo special timers: periodic timer, capture timer External EEPROM and internal RAM facilitate debugging and code developmentPin compatible with IRMCK341, OTP-ROM version 1.8V/3.3V CMOS Product SummaryMaximum crystal frequency 60 MHz Maximum internal clock (SYSCLK) frequency 128 MHz Sensorless control computation time 11 μsec typ MCE TM computation data range 16 bit signed Program RAM loaded from external EEPROM 48K bytes Data RAM 8K bytes GateKill latency (digital filtered) 2 μsec PWM carrier frequency counter 16 bits/ SYSCLK A/D input channels 8 A/D converter resolution 12 bits A/D converter conversion speed 2 μsec 8051 instruction execution speed 2 SYSCLK Analog output (PWM) resolution 8 bits UART baud rate (typ) 57.6K bps Number of I/O (max) 24 Package (lead-free) QFP64DescriptionIRMCF341 is a high performance RAM based motion control IC designed primarily for appliance applications. IRMCF341 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCF341 contains two computation engines. One is Motion Control Engine (MCE TM) for sensorless control of permanent magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCE TM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle instruction execution (60MIPS at 120MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process signal monitoring and command input. An advanced graphic compiler for the MCE TM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments. IRMCF341 comes with a small QFP64 pin lead-free package.TABLE OF CONTENTS1 Overview (4)2 IRMCF341 Block Diagram and Main Functions (5)3 Pinout (7)4 Input/Output of IRMCF341 (8)4.1 8051 Peripheral Interface Group (8)4.2 Motion Peripheral Interface Group (10)4.3 Analog Interface Group (10)4.4 Power Interface Group (11)4.5 Test Interface Group (11)5 Application Connections (12)6 DC Characteristics (13)6.1 Absolute Maximum Ratings (13)6.2 System Clock Frequency and Power Consumption (13)6.3 Digital I/O DC Characteristics (14)6.4 PLL and Oscillator DC characteristics (15)6.5 Analog I/O DC Characteristics (15)6.6 Under Voltage Lockout DC characteristics (16)6.7 CMEXT and AREF Characteristics (16)7 AC Characteristics (17)7.1 PLL AC Characteristics (17)7.2 Analog to Digital Converter AC Characteristics (18)7.3 Op amp AC Characteristics (19)7.4 SYNC to SVPWM and A/D Conversion AC Timing (20)7.5 GATEKILL to SVPWM AC Timing (21)7.6 Interrupt AC Timing (21)7.7 I2C AC Timing (22)7.8 SPI AC Timing (23)7.8.1 SPI Write AC timing (23)7.8.2 SPI Read AC Timing (24)7.9 UART AC Timing (25)7.10 CAPTURE Input AC Timing (26)7.11 JTAG AC Timing (27)8 Pin List (28)9 Package Dimensions (31)10 Part Marking Information (32)TABLE OF FIGURESFigure 1. Typical Application Block Diagram Using IRMCF341 (4)Figure 2. IRMCF341 Internal Block Diagram (5)Figure 3. IRMCF341 Pin Configuration (7)Figure 4. Input/Output of IRMCF341 (8)Figure 5. Application Connection of IRMCF341 (12)Figure 6. Clock Frequency vs. Power Consumption (13)TABLE OF TABLESTable 1. Absolute Maximum Ratings (13)Table 2. System Clock Frequency (13)Table 3. Digital I/O DC Characteristics (14)Table 4. PLL DC Characteristics (15)Table 5. Analog I/O DC Characteristics (15)Table 6. UVcc DC Characteristics (16)Table 7. CMEXT and AREF DC Characteristics (16)Table 8. PLL AC Characteristics (17)Table 9. A/D Converter AC Characteristics (18)Table 10. Current Sensing OP Amp AC Characteristics (19)Table 11. SYNC AC Characteristics (20)Table 12. GATEKILL to SVPWM AC Timing (21)Table 13. Interrupt AC Timing (21)Table 14. I2C AC Timing (22)Table 15. SPI Write AC Timing (23)Table 16. SPI Read AC Timing (24)Table 17. UART AC Timing (25)Table 18. CAPTURE AC Timing (26)Table 19. JTAG AC Timing (27)Table 20. Pin List (30)1 OverviewIRMCF341 is a new International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCF341 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE TM) for permanent magnet motors. The MCE TM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF341 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/Simulink TM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCF341.IRMCF341 is intended for development purpose and contains 48K bytes of RAM, which can be loaded from external EEPROM for 8051 program execution. For high volume production, IRMCK341 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCF341 and IRMCK341 come in the same 64-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass productionFigure 1. Typical Application Block Diagram Using IRMCF3412 IRMCF341 Block Diagram and Main Functions IRMCF341 block diagram is shown in Figure 2.Figure 2. IRMCF341 Internal Block DiagramIRMCF341 contains the following functions for sensorless AC motor control applications: •Motion Control Engine (MCE TM)o Proportional plus Integral blocko Low pass filtero Differentiator and lag (high pass filter)o Rampo Limito Angle estimate (sensorless control)o Inverse Clark transformationo Vector rotatoro Bit latcho Peak detecto Transitiono Multiply-divide (signed and unsigned)o Divide (signed and unsigned)o Addero Subtractoro Comparatoro Countero Accumulatoro Switcho Shifto ATAN (arc tangent)o Function block (any curve fitting, nonlinear function)o16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)o MCE TM program and data memory (6K byte). Note 1o MCE TM control sequencer• 8051 microcontrollero Three 16-bit timer/counterso16-bit periodic timero16-bit analog watchdog timero16-bit capture timero Up to 24 discrete I/Oso Eight-channel 12-bit A/DOne buffered channel for current sensing (0 – 1.2V input)Seven unbuffered channels (0 – 1.2V input)o JTAG port (4 pins)o Up to three channels of analog output (8-bit PWM)o UARTo I2C/SPI porto48K byte program RAM loaded from external EEPROMo2K byte data RAM. Note 1Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051data. Different sizes can be allocated depending on applications.3 PinoutFigure 3. IRMCF341 Pin Configuration4 Input/Output of IRMCF341All I/O signals of IRMCF341 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins.PWM gate signalInterfaceA/D InterfaceDiscrete I/OJTAG portUART Interface Crystal D/A Interface (PWM output)System ResetDigital power/ground Test ModePLL power/groundI2C InterfaceAnalog power/groundFigure 4. Input/Output of IRMCF3414.1 8051 Peripheral Interface GroupUART InterfaceTXD Output, Transmit data from IRMCF341 RXD Input, Receive data to IRMCF341Discrete I/O InterfaceP1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 input P1.1/RXD Input/output port 1.1, can be configured as RXD input P1.2/TXD Input/output port 1.2, can be configured as TXD outputoutput, needs to be pulled up to VDD1 in order to boot from I2CEEPROMP1.4/CAP Input/output port 1.4, can be configured as Capture Timer inputP1.5 Input/output port 1.5P1.6 Input/output port 1.6P1.7 Input/output port 1.7P2.0/NMI Input/output port 2.0, can be configured as non-maskable interrupt input P2.1 Input/output port 2.1P2.2 Input/output port 2.2P2.3 Input/output port 2.3P2.4 Input/output port 2.4P2.5 Input/output port 2.5P2.6/AOPWM0 Input/output port 2.6, can be configured as AOPWM0 outputP2.7/AOPWM1 Input/output port 2.7, can be configured as AOPWM1 outputP3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1P3.1/AOPWM2 Input/output port 3.1, can be configured as AOPWM2 outputP3.2/NINT0 Input/output port 3.2, can be configured as INT0 inputP3.3/NINT1 Input/output port 3.3, can be configured as INT1 inputP3.5/T1 Input/output port 3.5, can be configured as Timer/Counter 1 inputP5.1/TSM Input/output port 5.1, configured as JTAG port by defaultP5.2/TDO Input/output port 5.2, configured as JTAG port by defaultP5.3/TDI Input/output port 5.3, configured as JTAG port by defaultAnalog Output InterfaceP2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 withprogrammable carrier frequencyP2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 withprogrammable carrier frequencyP3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 withprogrammable carrier frequencyCrystal InterfaceXTAL0 Input, connected to crystalXTAL1 Output, connected to crystalReset InterfaceRESET Inout, system reset, needs to be pulled up to VDD1 but doesn’t require external RC time constantI2C InterfaceI2C clock output, or SPI dataSCL/SO-SI Output,I2C Data line or SPI chip select 0SDA/CS0 Input/output,I2C/SPI InterfaceI2C clock output, or SPI dataSCL/SO-SI Output,I2C data line or SPI chip select 0SDA/CS0 Input/output,output, needs to be pulled up to VDD1 in order to boot from I2CEEPROMP3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 14.2 Motion Peripheral Interface GroupPWMPWMUH Output, PWM phase U high side gate signalPWMUL Output, PWM phase U low side gate signalPWMVH Output, PWM phase V high side gate signalPWMVL Output, PWM phase V low side gate signalPWMWH Output, PWM phase W high side gate signalPWMWL Output, PWM phase W low side gate signalFaultGATEKILL Input, upon assertion, this negates all six PWM signals, programmable logic sense4.3 Analog Interface GroupAVDD Analog power (1.8V)AVSS Analog power returnAREF 0.6V buffered outputCMEXT Unbuffered 0.6V, input to the AREF buffer, capacitor needs to beconnected.IFB+ Input, Operational amplifier positive input for shunt resistor currentsensingIFB- Input, Operational amplifier negative input for shunt resistor currentsensingIFBO Output, Operational amplifier output for shunt resistor current sensing AIN0 Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage inputAIN1 Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down toAVSS if unusedAIN2 Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down toAVSS if unusedAIN3 Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down toAVSS if unusedAIN4 Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down toAVSS if unusedAIN5 Input, Analog input channel 5 (0 – 1.2V), needs to be pulled down toAVSS if unusedAIN6 Input, Analog input channel 6 (0 – 1.2V), needs to be pulled down toAVSS if unused分销商库存信息:IRIRMCF341TR IRMCF341TY。

PA341DF,PA341CE,PA341DW, 规格书,Datasheet 资料

F < 60Hz
PA341CE RESISTANCE, junction to air
Full Temperature Range
PA341DF RESISTANCE,
Full Tempera-
junction to air (Note 7) ture Range
5/50 50/200
BIAS CURRENT, vs. supply
0.2/2
OFFSET CURRENT, initial (Note 6)
2.5/50 50/200
INPUT IMPEDANCE, DC
1011
INPUT CAPACITANCE
3
COMMON MODE, voltage range
-40
125
Units V mA mA W
V V °C °C °C °C
SPECIFICATIONS
Parameter
Test Conditions
(Note 1)
PA341CE, PA341DF Min Typ Max
INPUT
OFFSET VOLTAGE, initial
12
40
OFFSET VOLTAGE, vs. temperature (Note 3)
The PA341CE is packaged in a hermetically sealed 8-pin TO-3 package. The metal case of the PA341CE is isolated in excess of full supply voltage.
The PA341DF is packaged in a 24 pin PSOP (JEDEC MO-166) package. The metal heat slug of the PA341DF is isolated in excess of full supply voltage. The PA341DW is packaged in Apex Precision Power’s hermetic ceramic SIP package. The alumina ceramic isolates the die in excess of full supply voltage.

SR341中文资料

Total Device Dissipation 500 Watts Junction to Case Thermal Resistance o 0.30 C/W Maximum Junction Temperature o 200 C Storage Temperature o o -65 C to 150 C DC Drain Current Drain to Gate Voltage 125 V Drain to Source Voltage 125 V Gate to Source Voltage 20 V
POLYFET RF DEVICES
REVISION 07/10/2001
1110 Avenida Acaso, Camarillo, Ca 93012 Tel:(805) 484-4210 FAX: (805) 484-3393 EMAIL:Sales@ URL:
Id
Id in amps; Gm in mhos
10.00
1.00
gM
0.10
0
2
4
6
8 10 Vgs in Volts
12
14
16
18
Zin Zout
PACKAGE DIMENSIONS IN INCHES
Tolerance .XX +/-0.01
.XXX +/-.005 inches
POLYFET RF DEVICES
元器件交易网
SR341
POUT VS PIN GRAPH
SR341 Pin vs Pout Freq=175Mhz; Idq=1A; Vds=50V
500 450 400 350 300 250 200 150 100 50 0 0 5 10 Pin in Watts 15 20 13

VLF4012AT-4R7M1R1;VLF4012AT-100MR79;VLF4012AT-3R3M1R3;VLF4012AT-2R2M1R5;中文规格书,Datasheet资料

Inductance tolerance(%) ±30 ±20 ±20 ±20 ±20 ±20 ±20
Test frequency (kHz) 100 100 100 100 100 100 100
DC resistance( ) max. 0.054 0.1 0.15 0.2 0.31 0.46 1.20 typ. 0.047 0.091 0.13 0.1R7
2.8±0.2
1.4max. Dimensions in mm
RECOMMENDED PC BOARD PATTERN
1.2 2.1 3.4 Dimensions in mm
Inductance [at 1/2 Idc1]3 (µH) 1 2.2 3.3 4.7 6.8 10 22
• All specifications are subject to change without notice.
/
001-04 / 20120310 / e531_vlf
(3/17)
Inductors for Power Circuits Wound/STD • Magnetic Shielded
Part No. VLF3014AT-1R0N1R7 VLF3014AT-2R2M1R2 VLF3014AT-3R3M1R0 VLF3014AT-4R7MR90 VLF3014AT-6R8MR72 VLF3014AT-100MR59 VLF3014AT-220MR37
1
SHAPES AND DIMENSIONS
VLF-MT Series VLF302510MT
With the VLF302510MT Series, a DC to DC converter with topclass voltage conversion efficiency for similar size products was achieved by optimizing the magnetic material and configuration. These products are optimal for use as choke coils in switching power supplies such as those in mobile devices requiring spacesaving design. FEATURES • Miniature size Mount area: 3.02.5mm Low profile: 1.0mm max. height • Generic use for portable DC to DC converter line. • High magnetic shield construction should actualize high resolution for EMC protection. • The products contain no lead and also support lead-free soldering. • The products is halogen-free. • It is a product conforming to RoHS directive. APPLICATIONS Smartphones, cellular phones, DSCs, DVCs, HDDs, LCD displays, compact power supply modules, etc. SHAPES AND DIMENSIONS

NCP3418BDR2G;NCP3418BMNR2G;中文规格书,Datasheet资料

NCP3418BMOSFET Driver with Dual Outputs for Synchronous Buck ConvertersThe NCP3418B is a single Phase 12 V MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. The high−side and low−side driver is capable of driving a 3000 pF load with a 25 ns propagation delay and a 20 ns transition time.With a wide operating voltage range, high or low side MOSFET gate drive voltage can be optimized for the best efficiency. Internal adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs.The floating top driver design can accommodate VBST voltages as high as 30 V , with transient voltages as high as 35 V . Both gate outputs can be driven low by applying a low logic level to the Output Disable (OD) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection.The NCP3418B is pin−to−pin compatible with Analog Devices ADP3418 with the following advantages:Features•Faster Rise and Fall Times•Thermal Shutdown for System Protection•Internal Pulldown Resistor Suppresses Transient Turn On of Either MOSFET•Anti Cross−Conduction Protection Circuitry•Floating Top Driver Accommodates Boost V oltages of up to 30 V •One Input Signal Controls Both the Upper and Lower Gate Outputs •Output Disable Control Turns Off Both MOSFETs •Complies with VRM10.x and VRM11.x Specifications •Undervoltage Lockout •Thermal Shutdown•Thermally Enhanced Package Available •These are Pb−Free DevicesDevice Package Shipping †ORDERING INFORMATIONSO−8(Pb−Free)2500 Tape & Reel NCP3418BDR2G†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.DFN−10(Pb−Free)3000 Tape & ReelNCP3418BMNR2GFigure 1. Block DiagramV CC DRVH BSTSWNDRVL PGNDODINPIN DESCRIPTIONSO−8DFN−10Symbol Description11BSTUpper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between 100 nF and 1.0 m F. An external diode is required with the NCP3418B.22IN Logic−Level Input. This pin has primary control of the drive outputs.33OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.44V CC Input Supply. A 1.0 m F ceramic capacitor should be connected from this pin to PGND.−5V CC Input Supply. A 1.0 m F ceramic capacitor should be connected from this pin to PGND.56DRVL Output drive for the lower MOSFET.67PGND Power Ground. Should be closely connected to the source of the lower MOSFET.−8PGND Power Ground. Should be closely connected to the source of the lower MOSFET.79SWN Switch Node. Connect to the source of the upper MOSFET.810DRVHOutput drive for the upper MOSFET.MAXIMUM RATINGSRating Value Unit Operating Ambient Temperature, T A0 to 85°C Operating Junction Temperature, T J (Note 1)0 to 150°CPackage Thermal Resistance: SO−8Junction−to−Case, R q JCJunction−to−Ambient, R q JA (2−Layer Board) Package Thermal Resistance: DFN−10 (Note 2) Junction−to−Case, R q JC (From die to exposed pad) Junction−to−Ambient, R q JA451237.555°C/W°C/W°C/W°C/WStorage Temperature Range, T S−65 to 150°C Lead Temperature Soldering (10 sec): Reflow (SMD styles only)Pb−Free (Note 3)260 peak°C JEDEC Moisture Sensitivity Level SO−8 (260 peak profile)1−Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.1.Internally limited by thermal shutdown, 150°C min.2. 2 layer board, 1 in2 Cu, 1 oz thickness.3.60−180 seconds minimum above 237°C.NOTE:This device is ESD sensitive. Use standard ESD precautions when handling.MAXIMUM RATINGSPin Symbol Pin Name V MAX V MIN V CC Main Supply Voltage Input15 V−0.3 VBST Bootstrap Supply Voltage Input30 V wrt/PGND35 V v 50 ns wrt/PGND15 V wrt/SW−0.3 V wrt/SWSW Switching Node(Bootstrap Supply Return)30 V−1.0 V DC−10 V< 200 nsDRVH High−Side Driver Output BST + 0.3 V35 V v 50 ns wrt/PGND15 V wrt/SW−0.3 V wrt/SWDRVL Low−Side Driver Output V CC + 0.3 V−0.3 V DC−2.0 V < 200 ns IN DRVH and DRVL Control Input V CC + 0.3 V−0.3 V OD Output Disable V CC + 0.3 V−0.3 V PGND Ground0 V0 V NOTE:All voltages are with respect to PGND except where noted.ELECTRICAL CHARACTERISTICS (Note 4)(V CC = 12 V, T A = 0°C to +85°C, T J = 0°C to +125°C unless otherwise noted.) Characteristic Symbol Condition Min Typ Max Unit SupplySupply Voltage Range V CC− 4.6−13.2V Supply Current I SYS BST = 12 V, IN = 0 V− 2.0 6.0mA OD InputInput Voltage High−− 2.0−−V Input Voltage Low−−−−0.8V Hysteresis−−−500−mV Input Current−No internal pull−up or pull−down resistors−1.0−+1.0m APropagation Delay Time (Note 5)t pdlODt pdhOD −303050506060nsnsPWM InputInput Voltage High−− 2.0−−V Input Voltage Low−−−−0.8V Hysteresis−−−500−mV Input Current−No internal pull−up or pull−down resistors−1.0−+1.0m A High−Side DriverOutput Resistance, Sourcing Current−V BST − V SW = 12 V (Note 7)− 1.8 3.0W Output Resistance, Sinking Current−V BST − V SW = 12 V (Note 7)− 1.0 2.5WTransition Times (Note 5)t rDRVHt fDRVH V BST − V SW = 12 V, C LOAD = 3.0 nF(See Figure 3)−−16112515nsnsPropagation Delay (Notes 5 & 6)t pdhDRVHt pdlDRVH V BST − V SW = 12 V−−30256045nsnsLow−Side DriverOutput Resistance, Sourcing Current−V CC = 12 V (Note 7)− 1.8 3.0W Output Resistance, Sinking Current−V CC − V SW = 12 V (Note 7)− 1.0 2.5W Timeout Delay−DRVH−SW = 0−85−nsTransition Times t rDRVLt fDRVL C LOAD = 3.0 nF(See Figure 3)−−16112515nsnsPropagation Delay t pdhDRVLt pdlDRVL (See Figure 3)−−30206030nsnsUndervoltage LockoutUVLO Startup−− 3.7 3.9 4.4V UVLO Shutdown−− 3.2 3.5 3.9V Hysteresis−−0.30.40.7V Thermal ShutdownOver Temperature Protection−(Note 7)150170−°C Hysteresis(Note 7)−20−°C4.All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).5.AC specifications are guaranteed by characterization, but not production tested.6.For propagation delays, “t pdh’’ refers to the specified signal going high; “t pdl’’ refers to it going low.7.GBD: Guaranteed by design; not tested in production.Specifications subject to change without notice.Figure 2. Output Disable Timing DiagramDRVH or DRVLODFigure 3. Nonoverlap Timing DiagramDRVH−SWSWAPPLICATIONS INFORMATIONTheory of OperationThe NCP3418B is a single phase MOSFET driver designed for driving two N−channel MOSFETs in a synchronous buck converter topology. The NCP3418B will operate from 5 V or 12 V , but it has been optimized for high current multi−phase buck regulators that convert 12 V olt rail directly to the core voltage required by complex logic chips. A single PWM input signal is all that is required to properly drive the high−side and the low−side MOSFETs. Each driver is capable of driving a 3.3 nF load at frequencies up to 500 kHz.Low−Side DriverThe low−side driver is designed to drive a ground−referenced low R DS(on) N−Channel MOSFET. The voltage rail for the low−side driver is internally connected to the V CC supply and PGND.High−Side DriverThe high−side driver is designed to drive a floating low R DS(on) N−channel MOSFET. The gate voltage for the high side driver is developed by a bootstrap circuit referenced to Switch Node (SW) pin.The bootstrap circuit is comprised of an external diode,and an external bootstrap capacitor. When the NCP3418B is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to V CC through the bootstrap diode See Figure 4. When the PWM input goes high, the high−side driver will begin to turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the SW pin will rise. When the high−side MOSFET is fully on, the switch node will be at 12 volts, and the BST pin will be at 12 volts plus the charge of the bootstrap capacitor (approaching 24 volts).The bootstrap capacitor is recharged when the switch node goes low during the next cycle.Safety Timer and Overlap Protection CircuitIt is very important that MOSFETs in a synchronous buck regulator do not both conduct at the same time. Excessive shoot−through or cross conduction can damage the MOSFETs, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. The NCP3418B prevents cross conduction by monitoring the status of the external mosfets and applying the appropriate amount of “dead−time” or the time between the turn off of one MOSFET and the turn on of the other MOSFET.When the PWM input pin goes high, DRVL will go low after a propagation delay (tpdlDRVL). The time it takes for the low−side MOSFET to turn off (tfDRVL) is dependent on the total charge on the low−side MOSFET gate. The NCP3418B monitors the gate voltage of both MOSFETs and the switchnode voltage to determine the conduction status of the MOSFETs. Once the low−side MOSFET is turned off an internal timer will delay (tpdhDRVH) the turn on of the high−side MOSFETLikewise, when the PWM input pin goes low, DRVH will go low after the propagation delay (tpdDRVH). The time to turn off the high−side MOSFET (tfDRVH) is dependent on the total gate charge of the high−side MOSFET. A timer will be triggered once the high−side mosfet has stopped conducting, to delay (tpdhDRVL) the turn on of the low−side MOSFETPower Supply DecouplingThe NCP3418B can source and sink relatively large currents to the gate pins of the external MOSFETs. In order to maintain a constant and stable supply voltage (Vcc) a low ESR capacitor should be placed near the power and ground pins. A 1 m F to 4.7 m F multi layer ceramic capacitor (MLCC) is usually sufficient.Input PinsThe PWM input and the Output Disable pins of the NCP3418B have internal protection for Electro Static Discharge (ESD), but in normal operation they present a relatively high input impedance. If the PWM controller does not have internal pull−down resistors, they should be added externally to ensure that the driver outputs do not go high before the controller has reached its under voltage lockout threshold. The NCP5381 controller does include a passive internal pull−down resistor on the drive−on output pin. Bootstrap CircuitThe bootstrap circuit uses a charge storage capacitor (C BST) and the internal (or an external) diode. Selection of these components can be done after the high−side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation:C BST+Q GATED V BSTwhere Q GATE is the total gate charge of the high−side MOSFET, and D V BST is the voltage droop allowed on the high−side MOSFET drive. For example, a NTD60N03 has a total gate charge of about 30 nC. For an allowed droop of 300 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used.The bootstrap diode must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on SW. The average forward current can be estimated by:I F(AVG)+Q GATE f MAXwhere f MAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in−circuit, since this is dependent on the source impedance of the 12 V supply and the ESR of C BST.Vout Output EnablePWM inFigure 4. NCP3418 Example Circuit10 PIN DFNMN SUFFIXCASE 485C−01ISSUE ADIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.SOIC−8D SUFFIX CASE 751−07ISSUE AGǒmm inchesǓSCALE 6:1*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.6.751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.DIM A MIN MAX MIN MAX INCHES4.805.000.1890.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S5.806.200.2280.244YM0.25 (0.010)Z SXS____ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION分销商库存信息:ONSEMINCP3418BDR2G NCP3418BMNR2G。

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Electrical Characteristics CharacteristicSymNotesMinimumTypicalMaximumUnitsCenter Frequency at 25°C Absolute Frequency f c 1, 2314.92315.00315.080MHz Tolerance from 315.0 MHz∆fc ±80dB Insertion Loss IL 1 1.73.0dB 3 dB Bandwidth BW 31, 2500700800kHz Rejectionat f c - 21.4 MHz (Image)14050dBat f c - 10.7 MHz (LO)1540Ultimate80TemperatureOperating Case Temp.T C 3, 4-40+85°C Turnover Temperature T O 223752°C Turnover Frequency f O f c MHz Freq. Temp. CoefficientFTC 0.032ppm/°C 2Frequency Aging Absolute Value during the First Year |fA|5≤10ppm/yrExternal ImpedanceSeries Inductance L 186 nH (Pin 1), 82 nH (Pin 2)Shunt CapacitanceC9pFLid Symbolization (in addition to Lot and/or Date Codes)RFM RF3417TO39-3 Case•Ideal Front-End Filter for USA Automotive Wireless Receivers •Low-Loss, Coupled-Resonator Quartz Design •Simple External Impedance Matching •Rugged TO39 Hermetic Package•Complies with Directive 2002/95/EC (RoHS)The RF3417 is a low-loss, compact, and economical surface-acoustic-wave (SAW) filter designed to provide front-end selectivity in 315.0 MHz receivers. Receiver designs using this filter include superhet with 10.7MHz or 500kHz IF, direct conversion and superregen. Typical applications of these receivers are wireless remote-control and security devices (especially for automotive keyless entry) operating in the USA under FCC Part 15, in Canada under DOC RSS-210, and in Italy.This coupled-resonator filter (CRF) uses selective null placement to provide suppression, typically greater than 40dB, of the LO and image spurious responses of superhet receivers with 10.7MHz IF. RFM’s advanced SAW design and fabrication technology is utilized to achieve high performance and very low loss with simple external impedance matching (not included). Quartz construction provides excellent frequency stability over a wide temperature range.315.0 MHzSAW FilterRF3417CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.Notes:1.Unless noted otherwise, all measurements are made with the filter installed in the specified test fixture which is connected to a 50 Ω test system with VSWR ≤ 1.2:1. The test fixture L and C are adjusted for minimum insertion loss at the filter center frequency, f c . Note that insertion loss, bandwidth, and passband shape are dependent on the impedance matching component values and quality. 2.The frequency f c is defined as the midpoint between the 3dB frequencies.3.Unless noted otherwise, specifications apply over the entire specified operating temperature range.4.The turnover temperature, T O , is the temperature of maximum (or turnover) frequency, f o . The nominal frequency at any case temperature, T c , may be calculated from: f =f o [1-FTC (T o -T c )2].5.Frequency aging is the change in fc with time and is specified at +65°C or less. Aging may exceed the specification for prolonged temperatures above +65°C. Typically, aging is greatest the first year after manufacture, decreasing significantly in subsequent years.6.The design, manufacturing process, and specifications of this device are subject to change without notice.7.One or more of the following U.S. Patents apply: 4,54,488, 4,616,197, and others pending.8.All equipment designs utilizing this product must be approved by the appropriate government agency prior to manufacture or sale.PbAbsolute Maximum Ratings Typical Filter ResponseTypical filter responses are shown below. The actual response is dependent on external impedance matching and circuit layout. Illustrated frequencies and minimum rejection for LO and IMAGE are shown only for superhet receivers with 10.7MHz IF.RatingValueUnitsIncident RF Power+13dBm DC Voltage Between Any Two Pins (Observe ESD Precautions)±30VDC Case Temperature 5-40 to +85°C Soldering Temperature (10 seconds/5 cycles Max)260°C.Electrical ConnectionsTypical Test CircuitCase DesignPinConnection1Input or Output 2Output or Input 3Case GroundDimensionsMillimeters Inches MinMaxMinMaxA 9.400.370B 3.180.125C 2.503.500.0980.138D 0.46 Nominal 0.018 NominalE 5.08 Nominal 0.200 NominalF 2.54 Nominal 0.100 NominalG 2.54 Nominal0.100 NominalH 1.020.040J1.400.055分销商库存信息: RFMRF3417。