DESIGN OF NARROWBAND INTERFERENCE CANCELLER IN GPS RECEIVER USING FFT TECHNIQUE

Far East Journal of Electronics and CommunicationsVolume 2, Number 3, December 2008, Pages 195-213Published online: March 20, 2009This paper is available online at © 2008 Pushpa Publishing House:phrasesandKeywords global positioning system (GPS), narrowband interference canceller (NIC), fast Fourier transform (FFT) and excision threshold.Received October 14, 2008DESIGN OF NARROWBAND INTERFERENCECANCELLER IN GPS RECEIVER USING FFTTECHNIQUEWEI-LUNG MAO, TSANG-HUNG SU∗,JYH SHEEN and W. H. LIUDepartment of Electronic EngineeringNational Formosa UniversityNo. 64, Wunhua Rd.Huwei Township, Yunlin County63210 Taiwan, R.O.C.e-mail: wlmao@.twwlmao123@jsheen@.twwhliu@.tw∗Taiwan Semiconductor Manufacturing CompanyTaiwan, R.O.C.e-mail: r91921042@.twAbstractGPS is an accurate navigation system and generally used in civilian ormilitary applications. The performance of GPS receiver is usuallydegraded by intentional or unintentional RF interference. The jammingsignal may cause the navigation error and even saturate the receiver.This paper focuses on the cancellation of narrowband jamming signals infrequency domain. The fast Fourier transform (FFT) translates thereceived sequence into frequency domain and the excision processing isutilized to remove the jamming signal in the spectrum. The inverse fastW.-L. MAO, T.-H. SU, J. SHEEN and W. H. LIU196Fourier transform (IFFT) can reconstruct the time sequence after thejamming excision. The experimental results show that the frequencydomain excision is a powerful approach to reject the narrowbandinterference. After anti-jamming processing, the SNR is improved andnavigation data can be obtained successfully. The three main blocks (i.e.,FFT, excision and IFFT parts) are implemented effectively on AlteraStratix FPGA EP1S25 F780C5 to accomplish the continuous waveinterference (CWI) cancellation.1. IntroductionThe globe position system (GPS) is a direct sequence spread spectrum (DSSS) structure. Using Gold codes, it can cope with wideband noise (such as thermal noise and channel noise) or low power narrowband noise by its processing gain. In order to deal with intentional jamming noise, additional architecture is developed before despreading the received signal. There are different types of anti-jamming architectures such as adaptive transversal filters [2], overlap fast Fourier transform [1] and filter bank methods [2]. FFT is a powerful method in serious jamming environment. Especially, when multi-tones jamming signals are added in the channel, FFT can achieve better signal to noise ratio (SNR) than adaptive transversal filter [1]. However, power consumption becomes a key consideration in practical using especially in mobile system. Data resolution in frequency domain depends on the length of fast Fourier transform (FFT). Larger number FFT is complex implemented by VLSI or FPGA but also needs more power consumption. This paper will focus on analyzing the performance of different length FFT under the jamming of single tone and multi-tones.In this paper, the frequency-domain implementation of narrowband canceller in GPS receiver is proposed. The FFT scheme translates the received signal into frequency, an excisor block modified the spectrum to eliminate narrowband interference, and an inverse FFT transforms the modified spectrum back to the time domain. The excision algorithm with the white noise statistical property is employed to excise a variable of number of frequency bins from each FFT block as its magnitude is above the threshold. Better resolution in frequency domain depends on the larger length of FFT/IFFT architecture. The FPGA realization of 1024-point FFT/IFFT processors with world length of 18-bits is developed.DESIGN OF NARROWBAND INTERFERENCE CANCELLER … 197 It is shown that the proposed frequency-domain canceller can provide excellent protection against single/multi-tone narrowband interference in GPS receiver.The remainder of this paper is organized as follows: Section 2 describes the GPS received signal model. In Section 3, the jamming excision scheme in frequency domain is introduced and the FFT architecture is described. Section 4 proposes the circuit realization of narrowband interference canceller in FPGA platform to accomplish the jamming suppression. Simulation results are demonstrated in Section 5. Some conclusions are stated in the last section.2. System ModelsGPS satellite transmits navigation data using channel L 1. The transmitted spread spectrum signal is()()()[](),2cos 1θ+π⊕=t f t CA t D t S L (1)where ()t D is the data sequence representing the navigation data from the satellite and ()t CA is the PRN code sequence representing GPS C/A-code with a chip rate of ()1c .MHz 023.1R L f = and θ are the L 1 carrier frequency and phase delay. Receiving signal consisted of several components: GPS signal, white noise and intentional jamming signal. It can be modeled as()()()(),t j t w t S t r ++= (2)where ()t w is additive white Gaussian noise (AWGN) and ()t j is the jamming source. Figure 1 shows the architecture of anti-jamming GPS system. The received signal is bandpass filtered, amplified and down converted. To simply the analysis, we assume that the received signal then passes through a filter matched to the chip waveform and is sampled synchronously once during each chip interval resulting in the observation()()()(),n j n w n S n r ++= (3)where ()()()n j n w n S ,, are discrete time waveforms. They are assumed to be mutually independent. Two kinds of narrowband interferences will be considered:W.-L. MAO, T.-H. SU, J. SHEEN and W. H. LIU198 (1) Single tone continuous wave interference (CWI)()(),cos 1θ+ω=Δc nT J n j (4a)where J is the amplitude, Δω is the frequency offset from the carrier frequency and c T is the chip duration and θ is a random phase uniformly distributed over the interval [).2,0π(2) Multi-tone CWI()(),cos 12∑=Δθ+ω=I i i c i i nT Jn j (4b)where ,i J i θ and i Δω represent the amplitude, random phase and frequency offset, respectively, of the i th interferer and I is the number of narrowband interferers.(3) Periodically swept (linear FM) CWI()[()()](),15.01cos 23lK n K l nT nT l J n j c c <≤−θ+∗ξ∗+ω−−=Δ...,,3,2,1=l (4c) where J and θ are the amplitude and random phase of the swept CWI. Δω represents the offset from the GPS carrier frequency, Ω is the sweep bandwidth, K Ω=ξ is the sweep rate and K is the sweep period.After anti-jamming system, ()n S and ()n w sequence which are wideband signals, cannot be estimated from the receiving data, but the interference ()n j can be removed at the frequency domain. The error signal ()n z is()()()()()()(),~~n w n S n j n j n w n S n z +=−++= (5)where ()n z can be considered as almost interference-free signal and is then fed into code correlator.DESIGN OF NARROWBAND INTERFERENCE CANCELLER (199)(a)(b)Figure 1. GPS spread spectrum system (a) Transmitter,(b) Anti-jamming receiver.3. Excision Algorithm in Frequency DomainThe GPS signals arrive at receiver at a low-power level, typically 20-30 below the ambient thermal noise level. If the received data is translated to frequency domain via FFT method, the magnitude observed in spectrum is flat. But if the narrowband jamming is added to the channel, some frequency bins will stand out. These bins will be easily found in the spectrum. When they are set to zero, the jamming can be rejected. A simplified block diagram of an anti-jamming GPS model is shown in Figure 2. The anti-jamming architecture in frequency domain is composed of four function blocks, i.e., (1) windowing, (2) forward FFT, (3) interference excision algorithm and (4) inverse FFT.Figure 2. The block diagram of narrowband interference canceller.W.-L. MAO, T.-H. SU, J. SHEEN and W. H. LIU200 A. WindowingThe windowing applied to the received data is a weighting function and it can smooth the discontinuities at the boundary of the data block and decrease the spectral leakage. In our system, every block of 1024 datum will be applied with FFT algorithm to transfer the data from time domain to frequency domain. When the frequency of the signal is not exactly belonging to one of the FFT frequency bins, the signal energy will be spread across the spectrum proportional to the main lobe and the highest side lobe. The window function of the minimum 4 samples Blackman Harris is applied here()⎟⎠⎞⎜⎝⎛π+⎟⎠⎞⎜⎝⎛π−=n N n N n w 22cos 14128.02cos 48829.035875.0 .1...,,2,1,02cos 01168.0−=⎟⎠⎞⎜⎝⎛π−N n n N (6) For observing the effects of rectangular and Blackman Harris windows, it is assumed that the received data are constructed by AWGN and single tone interference (INR is 50dB). Figure 3 is the result of the received data through a minimum 4 sample Blackman Harris window. It can be easily distinguished between AWGN and interference signal from it.Figure 3. The spectrum of received signal through a minimum4 sample Blackman Harris window.DESIGN OF NARROWBAND INTERFERENCE CANCELLER (201)B. Forward FFTThe decimation-in-frequency FFT algorithm is formed by separating outputs into smaller and smaller parts in frequency domain. In order to construct decimation-in-frequency FFT algorithm, the FFT equation is expressed as[][]()..1...,,1,0,102∑−=π−=−==N n N nk j nk N nk N e W N k W n x k X (7)In this equation, even-number frequency outputs can be rewritten as[][]()[]()()∑∑−=−===10120222N n N n r n N r n N W n x Wn x r X []()()∑−=−=+122.1...,,1,0N N n r n N N r W n x (8)The dummy variable of equation (8) can be rearranged as[][]()()[]()[]()()().22120120222∑∑−=−=+++=N n N n r N n N r n N W N n x W n x r X (9) Because of the periodicity property, equation (9) can be expressed as [][]()[]()()()∑−=−=++=12021...,,1,022N n rn N N r W N n x n x r X (10) with ()[]()rn NrN N rn N r N n N W W W W 2222=+=+ and .22N N W W = This implies that the first half and the second half input sequences will be added to construct the N points DFT. The odd-number frequency outputs can be rewritten as[][]()()∑−=+−==+1012.12...,,1,012N n r n N N r W n x r X (11)W.-L. MAO, T.-H. SU, J. SHEEN and W. H. LIU202 By the similar procedures above, equation (11) can be expressed as [][]()[]()()()()∑−=+−=+−=+12012.12...,,1,0212N n r n N N r W N n x n x r X (12)Using equations (10) and (12) as the basis, the N points DFT are separated into two parts and represented as[][](),21202∑−==N n rn N W n g r X (13.1) [][](),12120∑−==+N n rn N n N W W n h r X (13.2)with [][]()[]2N n x n x n g ++= and [][]()[].2N n x n x n h +−=If we keep on decomposing the equations, N points FFT algorithm can be established.C. Excision thresholdAfter the windowing and FFT algorithm, the received data is represented on the frequency spectrum. If the intentional interference is processed by this anti-jam system, the jamming will occupy some frequency bins on the spectrum. The detection and removing method must be utilized such that the interference does not pass through this block. Otherwise, interference still feeds into the receiver after IFFT and causes the navigation error. Figure 4 shows the received signal spectrum with five jamming tones. If the frequency bins surpass the threshold, these bins will be set to zero. This action can remove the jamming power, and the GPS signal is also loss in these frequency bins. For this reason, we must set the threshold carefully to avoid decreasing the GPS signal power. In our architecture, the threshold from a statistical property of AWGN is chosen. When one million data of interference-free waveform (−20dBw) is translated to frequency spectrum after windowing and FFT, the excision threshold is set to the value such that fifty points are beyond the threshold among one million points.DESIGN OF NARROWBAND INTERFERENCE CANCELLER (203)Figure 4. The received signal spectrum with five CWI tones.D. Inverse FFTThe formulation of inverse FFT is similar to the forward FFT, so only the basic equation of IFFT is depicted in this section. Because the forward FFT is the decimation-in-frequency architecture, decimation-in-frequency inverse FFT would be a better scheme to develop for our structure. Bit reversing can be discarded and it can significantly reduce the hardware complexity and cost on implementation. The decimation-in-frequency IFFT algorithm is based on DFT by separating inputs into smaller and smaller parts. The basic IFFT equation is shown as[][],1...,,1,0110∑−=−−==N n nk N N n W k Y Nn z (14) with (),2N nk j nk N e W π−= where []k Y is the data sequence after the excision algorithm and []n z is the IFFT form of [].k Y4. The FPGA Realization of NICThis section will introduce the realization architecture of NIC and demonstrate the hardware simulation and implementation in FPGA platform.W.-L. MAO, T.-H. SU, J. SHEEN and W. H. LIU204A. FFT/IFFT architectureThe FFT/IFFT contains a significant portion of the computational resource of the NIC circuit and costs most logic elements in the Quartus II. The FFT/IFFT implementation contains (1) data address generator (DAG), (2) coefficient address generator (CAG) and (3) butterfly processor [6, 11]. There is a particular explanatory chart of the framework in Figure 5. The 1024 points FFT is developed in our circuit realization. The data length and its coefficient length are set to 18 bits.Figure 5. The particularized forwed FFT architecture.B. Butterfly processorThe FFT algorithm described in equation (13) represents the formulation of the even and odd parts, which can be regarded as the outputs in each stage. Figure 6 shows a radix-2 butterfly architecture for FFT/IFFT operation. The output signal []rX2 only needs complex adder, which can be separated as a real part adder and an imaginary part adder. However, []1X needs not only complex subtractor but also2+rcomplex multiplier. We introduce an efficient complex twiddle-factor multiplication, which can work with the adder and subtractor to build a butterfly. ()YjC+ are two complex numbers to perform the X+ and ()Sjmultiplication. The direct method is computing the two operations asRe=CX−SYCY+= (15) Im SXmethod.direct...(a)(b)Figure 6. (a) The radix-2 butterfly architecture for FFT, (b) radix-2butterfly architecture for IFFT.There are four multiplications, one addition and one subtraction inthe direct computation. If the original input SjC+ is pre-computed andstored in a table as C, ()SSC+ the complex twiddle-factorC− and (),multiplication can be rewritten as()()Y−=+ReXCYSC−()()method.C−−= (16)simplifiedS+XIm Y...CXThis structure consists of three multiplications, i.e., (),YC−S()YSC−+− and twoYSCC− and (),XXXC+ one addition, i.e., ()()Ysubtractions, i.e., YC−−+ One multiplierSYX− and ()().XCXoperation in the complex twiddle-factor multiplication is simplified to save the computing complexity. In circuit design, a subtractor costs lower power and fewer circuits than multiplier. In IFFT implementation, the only difference is the complex multiplier computed first, complex adder and subtractor computed later. Except this imparity, the outputs of this butterfly must divide by two according to the IFFT equations.Original sequenceDAG output sequence 11−i X X " i S Y Y −"1 1Z →11−i X X "1Z i S Y Y −"1(a) ()0000000→()0000000→ ()0000000→ ()4100001→()2010001→ ()1001001→ ()1001010→()1001010→ ()2010010→ ()5101011→()3011011→ ()3011011→ ()2010100→()4100100→ ()4100100→ ()6110101→()6110101→ ()5101101→ ()3011110→()5101110→ ()6110110→ ()7111111→ ()7111111→ ()7111111→first stage ()1=i second stage ()2=i third stage()3=i (b)Figure 7. (a) Data address generator outputs, (b) forward DAG outputs.C. Data address generator (DAG )The purpose of DAG of FFT/IFFT is to provide the desired address sequences for the RAMs. The data address needs to change with different stages and ensure the correct data entering butterfly block. Figure 7 shows the original outputs and switching results for the FFT. S is the total stage in FFT circuit, i is the current computing stage. In order to simply the steps, the highest ()1−i bits are named part “X ”(),11−i X X "the next ()i S − bits are named part “Y ”()i S Y Y −"1 and 1Z is just the last bit named “Z ”. The eight-point FFT is used as an example here. So, S is the number of 3, i is changed from ‘‘1” to ‘‘3” at different stages and the counter circuit will produce repeated sequence from 000 to 111. The results after forward DAG are shown in Figure 7 (b). At the first stage, []0x and []4x are computed by butterfly first, []1x and []5x will be the next computing elements. At the second stage, []0x and []2x are the leader components to enter the butterfly block. However, []0x and []1x are the first two addresses which insert to the butterfly block at third stage. According to the decimation in time architecture for FFT above, the stage of IFFT in contract to FFT is a down counting number.D. Coefficient address generator (CAG )The realization steps of CAG are shown in Figure 8. When the counter is exporting the outputs (),111000from → the last bit ()02 is removed and the other two bits ()212and 2 are selected to be S 1. Then two zero bits ()00 are united to S 1 such as the left side. There are four groups of coefficients for each stage in 8-point FFT algorithm. S 1 are the first stage factors, S 2 are the second and S 3 are the third stage coefficients in this FFT algorithm. As the analogous result in DAG for IFFT, the only replacement in CAG for IFFT is down counting the stage number in FFT. By utilizing the outputs of CAG and DAG, the decimation in frequency FFT/IFFT architectures can be easily built.1S 3SStage 1 Stage 2 Stage 3 00 0000 00 00 01 00→ 01 10 00 10 0010 00 00 11 00 11 10 002SFigure 8. The realization of CAG for FFT.E. Excision circuitThe narrowband excisor is used to suppress the interference signals on the spectrum generated by the FFT block. Figure 9 shows the block diagram of excisor. It includes absolute value block, magnitude block, logarithm block and comparator block. Those spectrum signals stored in RAM include the real (re) and imaginary (im) portions. By changing the singed bit in data stream, the absolute value can be obtained. To simplify the complex computation, the magnitude of spectrum signal is approximated as follows: ()()()()()()().4,min ,max im re im re ⎦⎤⎢⎣⎡+≈k X k X k X k X k X (17) This approximation achieves the 0.6% accuracy on average with a maximum error of 11.6% at 5,43,4πππ and 47π radians [1]. After the magnitude block, the next operation is to describe the logarithm expression. The logarithm outputs will be fed into comparator and compared with the threshold to reject the interference. If the spectrum magnitude is above the threshold, the excision is applied and set the zeros to the real/imaginary part of these frequency bins. The excision processes are then accomplished and can be reconstructed to the time domain via IFFT operation.Figure 9. The block diagram of excision.5. Simulation ResultsIn this paper, several narrowband interference signals are considered to test the proposed FFT method. The System View tool is utilized to evaluate the performances. The power of AWGN is assumed to be−20dBw and the power of C/A code with carrier is –43dBw. Hence, the signal to noise ratio (SNR) is –23dB. The maximum jamming power is limited by 30dBw, and the interference to signal ratio (ISR) is set to 73dB. Three kinds of narrowband interferences such as single tone CW, multi-tone CW and swept signal are selected in the channel model. The sampling rate is 5MHz and a 14 bits A/D converter is used to translate analog signals into digital ones. After windowing, we increase the data width to 18 bits to avoid the overflow in FFT. The 18 bits in fractional part are used to construct the twiddle factors in FFT. In order to verify our method, the SNR after dispreading process is applied to confirm the performance. The SNR is defined as,log 10log 10SNR total ⎥⎦⎤⎢⎣⎡−=⎥⎦⎤⎢⎣⎡=s s n s P P P P P (18) with [][](),11∑==N n s n c n z N P[](),112total ∑==Nn n z N P where s P is the signal power, total P is the total power, n P is the noise power. []k z is the signal component after narrowband canceller, []n c is the C/A code waveform and N is the number of samples to be integrated.A. System view simulationsFigure 10 shows the improved SNR in single CWI tone environment. The jamming power increases from 0dBw to 30dBw. The proposed NIC can achieve the SNR performance of –22.723dB. The single tone, two tones, five tones, ten tones and twenty tones CWI are also simulated to test our NIC method. The power of jamming signal is set to 30dBw. It is shown in Figure 11 that the proposed architecture can also achieve better performance in multi-tone conditions. The frequency of swept CWI is started from 0.25MHz to 2.25MHz with sweep rate of 50Hz/s, 100Hz/s, 500Hz/s and 1KHz/s, respectively. The jamming power in the simulation is set as 30dBw and Figure 12 shows the simulation results. On average, the proposed NIC can provide the better performance of –23.05dB under swept CWI conditions.Figure 10. The SNR after NIC under single tone CWI.Figure 11. The SNR after NIC under multi-tone CWI.Figure 12. The SNR after NIC under swept CWI condition.(a)(b)Figure 13. (a) The received signal spectrum with single tone CWI,(b) the output signal spectrum after the NIC operation.B. Circuit implementationThe single CWI channel is utilized to demonstrate the proposed anti-jamming architecture. Figure 13 (a) shows the received signal spectrum when the single tone jamming is encountered. It is shown in Figure 13 (b) that the excision algorithm is utilized and the zeros are inserted at the frequency bins. The FFT circuit costs 548 logic cells to build and 24 DSP blocks. The DSP blocks are supportive functions in Stratix FPGA and can reduce the complex computations such as multiplications. The critical path is the computation of butterfly (24ns). The 1024 points FFT needs 5120 operations of butterfly and its latency is122.88us ().245120∗ The excision circuit costs 430 logic elements. Thensmaximum operational frequency is about 70MHz, so the 15ns clock is chosen to fit this circuit. Besides, this circuit needs 1024 clocks to excise the jamming signal and the latency is 15.36us ().151024∗ The IFFTnscircuit costs 613 logic elements and 24 DSP blocks. The memory frequency is higher than the butterfly in IFFT, so the critical path is the computation of butterfly (36ns). The IFFT needs 5120 operations of butterfly and its latency is 184.32 us ().ns5120∗366. SummaryIn this paper, an FFT-based narrowband interference cancellation architecture of GPS receiver is proposed. Once the time sequences are transformed into frequency domain, the AWGN and interference can be separated significantly. The excision algorithm is employed to discard those frequency bins with jamming power. After the operation of inverse FFT, the rebuilt time sequences can be processed to obtain the navigation data. The NIC is developed in Startix FPGA EP1S25F780C5. The fully NIC system has a latency of 322.56us and contains 1591 logic elements. The experimental results demonstrate that our implementation indeed provides better SNR improvement under single/multi-tone/swept tone narrowband interference environments.References[1] P. T. Capozza, B. J. Holland, T. M. Hopkinson and R. L. Landrau, A single-chipnarrow-band frequency-domain excisor for a Global Positioning System (GPS) receiver, IEEE J. Solid-State Circuits 35 (2000), 401-411.[2] P. T. Capozza, B. J. Holland, T. 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