ANSI-ESDSTM5.2-1999

for Electrostatic DischargeSensitivity Testing –Charged Device Model (CDM)Component Level™Electrostatic Discharge Association7900 Turin Road, Bldg.3, Suite 2Rome, NY 13440-2069An American National StandardApproved May 2, 2001ESD-STM5.3.1-1999ESD Association Standard Test Methodfor Electrostatic DischargeSensitivity TestingCharged Device Model (CDM) -Component Level Approved September 26, 1999ESD Association™ESD Association standards and publications are designed to serve the public interest by eliminating misunderstandings between manufacturers andpurchasers, facilitating the interchangeability and improvement of products and assisting the purchaser in selecting and obtaining the proper product for his particular needs. The existence of such standards and publications shall not in any respect preclude any member or non-member of the Association from manufacturing or selling products not conforming to such standards andpublications. Nor shall the fact that a standard or publication is published by the Association preclude its voluntary use by non-members of the Association whether the document is to be used either domestically or internationally.Recommended standards and publications are adopted by the ESD Association in accordance with the ANSI Patent policy.Interpretation of ESD Association Standards: The interpretation of standards in-so-far as it may relate to a specific product or manufacturer is a proper matter for the individual company concerned and cannot be undertaken by any person acting for the ESD Association. The ESD Association Standards Chairman may make comments limited to an explanation or clarification of the technicallanguage or provisions in a standard, but not related to its application to specific products and manufacturers. No other person is authorized to comment on behalf of the ESD Association on any ESD Association Standard.Published by:Electrostatic Discharge Association 7900 Turin Road, Building 3, Suite 2Rome, NY 13440-2069Copyright © 1999 by ESD Association All rights reservedNo part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher.Printed in the United States of AmericaISBN: 1-58537-011-8Caution Notice(This foreword is not part of ESD Association Standard Test Method STM5.3.1-1999)iForewordExisting electrostatic discharge (ESD) test models and standards model a charged object approaching acomponent and discharging through the component. However, with the increasing use of automated component handling systems another potentially destructive discharge mechanism, the Charged Device Model (CDM), becomes increasingly important. In the charged device model the component itself becomes charged - usually by sliding on a surface - and is rapidly discharged by (an ESD event) as it approaches a conductive object.Accurately quantifying the CDM discharge event is very difficult, if not impossible, due to the limitations of the measuring equipment and its influence on the discharge itself. The CDM discharge is generally completed in a few nanoseconds, and peak currents of tens of amperes have been observed. The peak current into thecomponent will vary considerably depending on a large number of factors such as: package type and parasitics. The typical failure mechanism for the CDM model, observed in MOS components, is dielectric damage, although other damage has been noted.The CDM sensitivity of a given component is very package dependent. The same integrated circuit (IC) chip in a small outline package (SOP) may be more susceptible to CDM damage than it is in a dual-in-line (DIL) package. ICs in thin small outline packages (TSOP), or a pin grid array (PGA) packages usually have the lowest CDM withstand voltage.Based on results obtained with early CDM testers, which did not necessarily meet the waveforms specified in this standard, components with CDM sensitivities of 500 volts or less proved difficult to handle without damage. Components with CDM sensitivities of 1,500 volts or more did not experience major field problems using proper handling techniques.This document does not apply to the so-called SDM testers: socketed discharge model. Waveform parameters for the 30 pF verification module should be used for guidance only. They may be subject to change in future revisions of this document.This Standard Test Method was processed and approved for submittal to the ESD Association Standards Committee and the Association Board of Directors by the Device Testing Working Group, 5.0.At the time this standard was approved the Working Group had the following members:Koen Verhaege, Chair Sarnoff CorporationJon Barth Barth Electronics Mike Chaine Micron Technology Lou DeChairo Lucent TechnologiesTom Diep Texas InstrumentsLeo G. HenryORYX Instruments CorporationIra Cohen IntelMarti FarrisIntelHugh Hyatt Hyger Physics Bob CareyLucent TechnologiesMark KellyDelphi Delco Electronics SystemsThomas MeuseKeytek Ian Morgan AMDScott JohnsonAMDIn addition the following people made significant contributions to this document:Satoshi IsofukuTokyo Electronics Trading Joseph VeltriFordTerry Welsher Lucent TechnologiesLes AverySarnoff CorporationKarlheinz BockIMECTable of Contents1. SCOPE AND PURPOSE (1)1.1 S COPE (1)1.2 P URPOSE (1)2. REFERENCES (1)3. DEFINITIONS (1)3.1 C HARGED D EVICE M ODEL (1)3.2 CDM ESD TESTER (1)3.3C ONTACT-MODE DISCHARGE (1)3.4 N ON-CONTACT MODE DISCHARGE (1)3.5 C OMPONENT (1)3.6 C OMPONENT FAILURE (1)3.7 E LECTROSTATIC DISCHARGE SENSITIVITY (ESDS) (1)3.8 ESD WITHSTAND VOLTAGE (1)4. ESD COMPONENT CLASSIFICATIONS (1)5. COMPONENT CHARGING AND DISCHARGING METHODS (2)5.1 D IRECT C HARGING M ETHOD (2)5.2 F IELD-INDUCED M ETHOD (2)5.3 D ISCHARGING M ETHODS (2)6. REQUIRED EQUIPMENT (3)6.1 CDM ESD T ESTER (3)6.2 W AVEFORM V ERIFICATION E QUIPMENT (3)6.2.1 Equipment for 3.5 Gigahertz Waveform Measurement (3)6.2.2 Equipment for 1 Gigahertz Waveform Measurement (3)6.2.3 Verification Standard Test Modules for CDM Testing (3)6.2.4 Capacitance Meter (3)7. PERIODIC EQUIPMENT CALIBRATION, TESTER QUALIFICATION, WAVEFORM RECORDS, AND WAVEFORM VERIFICATION REQUIREMENTS (3)7.1 E QUIPMENT C ALIBRATION (3)7.1.1 Verification Modules (4)7.2 T ESTER Q UALIFICATION (4)7.3 T ESTER W AVEFORM R ECORDS - N EW E QUIPMENT (4)7.4 T ESTER W AVEFORM V ERIFICATION (4)8. QUALIFICATION AND VERIFICATION PROCEDURES (4)8.1 CDM ESD T ESTER Q UALIFICATION P ROCEDURE (4)8.2 W AVEFORM VERIFICATION PROCEDURE (5)9. CDM ESDS TESTING TEQUIREMENTS AND PROCEDURES (6)9.1 T EST REQUIREMENTS (6)9.1.1 Handling of Components (6)9.1.2 ESD Stress Test Temperature (6)9.1.3 Recommended Waveform Check (6)9.1.4 Component Static and Dynamic Tests (6)9.2 CDM C OMPONENT C LASSIFICATION T ESTING P ROCEDURE (6)10. CLASSIFICATION CRITERIA (7)11. APPENDIX 1: VERIFICATION MODULES FOR CDM TESTING (11)ii12. APPENDIX 2: DISCHARGE TEST METHOD GUIDANCE (12)12.1 N ON-CONTACT M ODE D ISCHARGE (12)12.2C ONTACT M ODE D ISCHARGE (11)13. APPENDIX 3: RECOMMENDED COMPONENT, VERIFICATION MODULE AND TESTER CLEANING METHOD (13)Table of FiguresF IGURE 1:CDM ESD WAVEFORM FOR THE VERIFICATION MODULES, USING A 3.5 GIGAHERTZ BANDWIDTH MEASUREMENTSYSTEM (8)F IGURE 2:CDM ESD WAVEFORM FOR THE STANDARD VERIFICATION MODULES USING THE ONE GIGAHERTZ BANDWIDTHMEASUREMENT SYSTEM (9)F IGURE 3:30 P F VERIFICATION MODULE WITH 26 MM DISK (11)F IGURE 4:4 P F VERIFICATION MODULE WITH 9 MM DISK (11)Table of TablesT ABLE 1 - CDM ESD C LASSIFICATION L EVELS (2)T ABLE 2 - ESD S TEP S TRESS L EVELS (5)iiiESD Association Standard Test Method ESD-STM5.3.1-1999 ESD Association Standard TestMethod for Electrostatic DischargeSensitivity Testing -CHARGED DEVICE MODEL (CDM), COMPONENT LEVEL1. Scope and purpose1.1 ScopeThis standard establishes the procedure for testing, evaluating and classifying the electrostatic discharge (ESD) sensitivity of components to the defined charged device model (CDM).1.2 PurposeTo establish a correlatable test method that simulates CDM failures and provides reliable and repeatable results from tester to tester. This will allow accurate comparisons of component CDM ESD sensitivity levels.2. ReferencesEOS/ESD-ADV1.0, Glossary of Terms13. DefinitionsFor the purposes of this standard the following definitions shall apply in addition to those specified in the ESD Association Glossary of Terms.3.1 Charged Device ModelA model that approximates the discharge event that occurs as a charged component discharges to another object at a different electrostatic potential.3.2 CDM ESD testerEquipment (referred to as "tester" in this standard) that simulates the component level Charged Device Model ESD event using thenon-socketed test method.1 ESD Association, 7900 Turin Road, Bldg 3, Ste 2, Rome, NY, 13440-2069, 315-339-6937 3.3 Contact-mode dischargeAn ESD event initiated within a relay. The relay is connected to the component pin via a probe, and the component is not in a socket.3.4 Non-contact mode dischargeAn ESD event that is initiated by a probe tip approaching a component pin and the component is not placed in a socket.3.5 ComponentAn item such as a resistor, diode, transistor, integrated circuit or hybrid3.6 Component failureA condition in which a component fails to meet one or more specified static or dynamic data sheet parameters.1. Static parameters are those measured withthe component in a non-operating (standby)condition. These parameters may include,but are not limited to: input leakage current,input breakdown voltage, output high and low voltages, output drive current, and supplycurrent.2. Dynamic parameters are those measuredwith the component in a functioning(operating) condition. These parameters may include, but are not limited to: fullfunctionality, output rise and fall times undera specified load condition, and dynamiccurrent draw.3.7 Electrostatic discharge sensitivity (ESDS) The ESD level that causes component failure. 3.8 ESD withstand voltageThe maximum ESD level that does not cause component failure.4. ESD Component ClassificationsESD sensitive components are classified according to their ESD withstand voltage using the test procedure described in this standard. The CDM ESD component classification levels are shown in Table 1.1ESD-STM5.3.1-1999 2Table 1 - CDM ESD Classification Levels Class Voltage range C1 <125 vC2 125 v to <=250 v C3 250 v to <=500 v C4 500 v to <=1000 v C5 1000 v to <=1500 v C6 1500 v to <=2000 v C7 =>2000 vNote 1: Use the "C" prefix to indicate a CDM classification.Note 2: Add the following Suffix codes:c = contact moden = non-contact mode For example:C4n: CDM, class 4, non-contact mode5. Component Charging and Discharging MethodsEither of the following two methods may be used to raise the component potential for the subsequent CDM discharge.5.1 Direct Charging MethodThe component to be tested is placed on the ground plate and charged through the pin which best provides an ohmic connection to thesubstrate or bulk material of the component, or through all pins simultaneously. The total charging resistance shall be at least 100 megohms. To prevent component damage,precautions shall be taken to ensure the charging mechanism and component are at groundpotential prior to the initial connection. At least one megohm of the charging resistance shall be physically placed close to the charging pin to isolate the effect of any residual charge on the charge up line. Contact to the charging pin(s) must be established before the voltage is raised. Each pin is discharged, one at a time (including power supply pins and ground pins), except the pins connected to the substrate. Re-charge the component after each pin has been discharged. It is permissible to leave the charging probe on the charging pin during the discharge cycleprovided the waveform requirements of Section 7 are satisfied.Note 3: The substrate, or bulk material, is typically called Vss, or ground, for NMOS or for n-well (p-substrate) CMOStechnologies; and Vcc, or Vdd, for p-well (n-substrate) CMOS technologies. For a charge-pumped substrate (where there is no direct access through an external pin), the Vss or ground pin is still appropriate to use.5.1.1 Multi-chip modules or other specialcomponents (e.g., Silicon on Sapphire, Silicon on insulator, and hybrids) must be charged through a common power supply pin or simultaneously through multiple pins to ensure the entire component reaches the charging potential.5.1.2 If the process technology is unknown,charge the component through the Vss or ground pin, or through all pinssimultaneously. Make note of the charging pins when reporting the results. Vpp pins shall never be used as charging pins, unless all device pins are simultaneously contacted and charged.5.2 Field-induced MethodPlace the component to be tested on the charging plate. Raise the potential of the component by energizing the field charging plate. Discharge through all pins, including Vcc and Vss, one at a time. The size of the field charging plate, at least 7 times larger in area than the size of the component under test, shall be such that the waveform qualification meets the requirement of Section 7. The total source resistance of the charging plate shall be at least 100 megohm. The thickness of the dielectriccovering the charge plate shall have a maximum thickness of 130 microns as the presence of the dielectric reduces the package capacitance between the component and the charging plate which affects the discharge current. Take precautions to ensure components are not charged prior to testing.5.3 Discharging MethodsBackground information on discharging methods is given in Appendix 2.ESD-STM5.3.1-199936. Required Equipment6.1 CDM ESD TesterEquipment meeting the requirements of this standard, producing pulses meeting thewaveform characteristics specified in figure 1 and figure 2.Note 4: Minimize parasitics in the charge and discharge paths whenconstructing test equipment. Parasitics greatly influence test results.6.2 Waveform Verification Equipment6.2.1 Equipment for 3.5 Gigahertz Waveform Measurement6.2.1.1 Oscilloscope - An oscilloscope ortransient digitizer with a single shot 3 dB-bandwidth of at least 3.5 gigahertz (e.g., an Tektronix SCD 5000 or equivalent) with a nominal 50 ohm input impedance.6.2.1.2 Attenuator - with a precision of 0.1 dB at3.5 gigahertz a DC precision of the attenuation factor of 5% and an impedance of 50 ±3 ohms.6.2.1.3 Probe - An inductive current transduceror coaxial resistive probe of at least 5 gigahertz bandwidth.6.2.1.4 Cable assemblies - Cable assemblieswith no more than 0.4 dB loss at frequencies up to 3.5 gigahertz and impedance of 50 ±2 ohms. 6.2.2 Equipment for 1 Gigahertz Waveform Measurement6.2.2.1 Oscilloscope - An oscilloscope ortransient digitizer with a single shotbandwidth of at least one gigahertz.(e.g., a Tektronix SCD 1000, or Tektronix 7104, or equivalent) with a nominal 50 ohm input impedance.6.2.2.2 Attenuator - Attenuator with a precisionof ±0.1 dB at 1.0 gigahertz, a DCprecision of the attenuation factor of 5% and an impedance of 50 ±3 ohms.6.2.2.3 Probe - An inductive current transduceror coaxial resistive probe of at least 5 gigahertz bandwidth.6.2.2.4 Cable Assemblies - Cable assemblieswith no more than 0.1 dB loss at frequencies up to 1.0 gigahertz and impedance of 50 ±2 ohms.6.2.3 Verification Standard Test Modules for CDM TestingTwo gold-plated or nickel-plated etched copper disks on single sided 0.8 millimeter thick FR-4 circuit board material. Each disk shall be etched in the center of a square of material at least 30 millimeters by 30 millimeters. The larger disk shall have a capacitance of 30 pF ±5% at 1 megahertz (approximately 26 millimeters in diameter). The smaller disk shall have a capacitance of 4 pF ±5% at 1 megahertz(approximately 9 millimeters in diameter). The capacitance is measured with the non-metallized non-disc side of the verification modules in intimate contact with the metal surface of a ground plane. The verification modules are shown in Figures 3 and 4 (see Appendix 1).Note 5: I t is very important that the verification standard test modules are compliant with the specifications in section 6.2.3. Therefore, one must measure the capacitance at 1MHz as specified. If the modules do not comply, they can not be used.6.2.4 Capacitance MeterCapacitance meter with a resolution of 0.2 pF, a measurement accuracy of 3%, and ameasurement frequency of one megahertz.Note 6: The sampling rate of a digitized sampling oscilloscope may affect the waveform.7. Periodic Equipment Calibration,Tester Qualification, Waveform Records, and Waveform Verification Requirements7.1 Equipment CalibrationCalibrate all equipment used for tester or waveform verification in accordance with the manufacturers' recommendations, with aESD-STM5.3.1-1999 4maximum of one year between calibrations. This equipment list includes oscilloscope, attenuator, current transducer, coaxial resistive probe, capacitance meter, and calibration module(s) conforming to the requirements of 6.2. Calibration shall be traceable to national standards, such as National Institute ofStandards and Technology (NIST) in the United States, or international standards.7.1.1 Verification Modules7.1.1.1 Place the non-metallized non-disc sideof the 4 pF verification module inintimate contact with the metal surface of a ground plane. Ensure there is no air space between the module and the ground plane.7.1.1.2 Measure the capacitance of the moduleto the ground plane using thecapacitance meter. The capacitance value of the verification module shall be within the value specified in 6.2.3.7.1.1.3 Repeat from 7.1.1.1 using the 30 pFverification module on the ground plane.7.1.1.4 Measure the capacitance of the moduleto the ground plane using thecapacitance meter. The capacitance value of the verification module shall be within the value specified in 6.2.3.7.2 Tester QualificationPerform the CDM ESD tester qualification as part of the initial acceptance testing and routinely as suggested by the manufacturer. Themaximum period between full qualification tests shall be one year. In addition, repeat qualification testing whenever the equipment is serviced in a manner which the manufacturer or user defines as having the potential for modifying discharge current waveforms. The CDM ESD tester qualification procedure is specified in 8.1. Periodic waveform verification shall be performed in accordance with 7.4.Note 7: Due to the high cost of the waveform monitoring equipment,manufacturer certified discharge heads may be used and waveform verification performed using a lower bandwidth monitor as specified in 6.2.2.7.3 Tester Waveform Records - New EquipmentRecord positive and negative waveforms (using either photographs or digitized waveforms)during the tester initial qualification procedures. Waveform records are required for charge levels as defined in the tester qualification procedure. Retain the waveform records until the next calibration or for the duration specified by the internal record keeping procedures.7.4 Tester Waveform VerificationVerify and record the ESD tester waveforms periodically, using the verification modules defined in 6.2.3. The maximum time between verifications shall be one month for equipment that is in use for at least 30 hours per week, or up to three months for testers used lessfrequently. Verification shall include waveform observations and comparison to waveformrecords for both positive and negative polarities. The waveform verification procedure is given in 8.2.Dielectric layers and discharge contacts (e.g., pogo pins) are key elements of the testerconstruction. Any change to these requires tester waveform verification.8. Qualification and Verification ProceduresFor the purpose of both equipment qualification and waveform verification, the standardverification modules are treated as components.8.1 CDM ESD Tester Qualification ProcedureCDM ESD tester qualification shall ensure waveform integrity of the discharge current for both positive and negative polarities, and each verification module specified in 6.2.3. Monitor the waveform using the full bandwidthoscilloscope, attenuator, current probe or coaxial resistive probe described in 6.2.1. Do not use the one-gigahertz monitoring equipment for tester qualification.8.1.1 Clean the verification modules. Avoid skincontact with the modules prior to andduring testing. A recommended procedure is described in Appendix 3.8.1.2 Clean tester components to remove anysurface contamination that could result incharge loss. Pay particular attention to thedischarge probe, charging probe, and theground plane on which the device isplaced. A recommended procedure isdescribed in Appendix 3.8.1.3 Place the 30 picofarad (pF) verificationmodule on the ground plane or chargingplate, ensuring intimate contact (no airspace) between the module and theground plane. When a dielectric layer isused for component testing, it must meetthe requirements specified in section 5and be present during the calibrationprocedure.8.1.4 Set the horizontal time scale of theoscilloscope to 0.5 nanoseconds perdivision. Set the oscilloscope verticalsensitivity and offset, using attenuators ifnecessary, to cover the center 80% of thefull scale deflection.8.1.5 Raise the potential of the module, orcharging plate, to positive 500 volts.8.1.6 Discharge the module with the dischargeprobe close to the center of the verificationmodule and record the discharge currentwaveform. All parameters shall be withinthe limits specified in figure 1. Record thewaveform.8.1.7 Repeat the procedure given in 8.1.5 and8.1.6 at least two more times. Save therecord for future verifications. (Record alland save the one closest to the mean forfuture verification.)8.1.8 Repeat the procedure given in 8.1.5through 8.1.7 using a negative 500 voltcharging potential.8.1.9 For the 4 picofarad verification module,repeat 8.1.4 through 8.1.8 using all thevoltage levels in table 2. If the maximumpotential of the tester is lower than 2000volts, use that as the maximum. Set theoscilloscope vertical sensitivity and offset,using attenuators if necessary, to coverthe center 80% of the full-scale deflectionfor each voltage level. All parameters shallbe within the limits specified in figure 1.Save these records for future verifications. 8.1.10 I t is recommended that all waveformrecords be supplied with the tester forfuture waveform verification purposes. Table 2 - ESD Step Stress LevelsLevel Charging Voltage1 125 v2 250 v3 500 v4 1000 v5 1500 v6 2000 v8.2 Waveform verification procedureWaveform verification shall ensure waveform integrity of the discharge current, as specified in this standard, for both positive and negative polarities, using the small 4 pF verification module specified in 6.2.3.If the one-gigahertz bandwidth monitoring equipment will be used for future waveform verification, repeat the CDM ESD tester qualification procedure using the one-gigahertz bandwidth oscilloscope. Record the waveforms for future comparison purposes during waveform verification.8.2.1 Clean the 4 pF verification module. Avoidfurther skin contact with the module priorto and during testing. A recommendedprocedure is described in Appendix 3.8.2.2 Clean the tester to remove any surfacecontamination that could result in chargeloss. Pay particular attention to thedischarge probe, charging probe, theground plane on which the device isplaced. A recommended procedure isdescribed in Appendix 3.8.2.3 Place the 4 pF verification module on theground plane or charging plate, ensuringintimate contact (no air space) betweenthe module and the ground plane. When adielectric layer is used for componenttesting, it must meet the requirementsspecified in section 5 and be presentduring the calibration procedure.8.2.4 Set the horizontal time scale of theoscilloscope to 0.5 nanoseconds perdivision, and set the vertical sensitivity toallow for approximately ten amperes fullscale deflection.8.2.5 Raise the potential of the module, orcharging plate, to positive 500 volts.8.2.6 Discharge the module and observe thecurrent waveform. All parameters shall bewithin the limits specified in figure 1 if the3.5 gigahertz waveform monitoringequipment is used. If the narrowerbandwidth waveform monitoringequipment is used, ensure that allparameters are within the limits specifiedin figure 2. It is recommended that thewaveform parameters be compared to theprevious satisfactory verification record.Changes in the shape of the dischargepulse, even though they are withinspecification, may indicate degradation ofthe discharge path.8.2.7 Repeat the procedure given in 8.2.5through 8.2.6 using a negative 500 voltcharging potential and evaluate thewaveform.8.2.8 Remove the verification module.9. CDM ESDS Testing Requirements and Procedures9.1 Test requirements9.1.1 Handling of ComponentsUse ESD prevention procedures before, during and after testing.9.1.2 ESD Stress Test Temperature Stabilize the component to room temperature prior to and during the ESD stress testing period.9.1.3 Recommended Waveform CheckAt the beginning and end of each shift during which testing is performed, ensure waveform integrity for the discharge head for the 500 volt level of table 2, for positive and negative polarities, using the 4 pF verification module. If the waveforms no longer meet the specified limits (see figure 1 or figure 2), all test results subsequent to the previous satisfactory check shall be considered invalid. If testing is performed in consecutive shifts, waveform checks at the end of one shift may also serve as the initial checks for the following shift. 9.1.4 Component Static and Dynamic TestsPerform, full static and dynamic testing to specified component data sheet parameters prior to and following ESD stress testing to determine whether components have failed.Note 8: While pin leakage current may beused as a guide in determining the ESDwithstand voltage, it is not an adequatecriterion of component failure for complexintegrated circuits.Note 9: Static and dynamic testingimmediately following the ESD stressingprovides worst-case test data results. Withsome components, static and dynamiccharacteristics may be out of specified datasheet limits when tested immediatelyfollowing ESD stressing, but drift towardsacceptable levels with time. If static anddynamic testing is delayed, the componentmay be improperly classified at a higher ESD withstand voltage.Note 10: If static and dynamic testing is tobe performed at several temperatures,perform the tests first at the lowesttemperature, followed by the increasingtemperatures in sequence.9.2 CDM Component Classification Testing ProcedureClassify components according to their CDM ESD withstand voltage as shown in table 1. Stress test the components according to the procedure below. Testing may be initiated at any level desired. If the component fails, continue testing at a lower voltage until the withstand voltage is found. If the component passes at the initial level, continue testing following the voltage levels specified in table 2 until the component fails or the maximum charge voltage is reached. CDM ESD classification testing shall be considered destructive, even if the component does not fail during testing. Smaller voltage level increments may be used to determine withstand voltage if desired.Note11: A change in componentpackage, manufacturing processes,design, or materials may requirecomponent reclassification according tothis standard. Even if the same chip isused in a different package it should berequalified; no generic qualificationsshould be allowed.。