VHDL花样彩灯_实验报告

aj:in std_logic;-------------频率选择 30
Light:out std_logic_vector(7 downto 0);------ 点 阵 列 -----
（82-73）
hang:out std_logic_vector(7 downto 0) -------------（90-83）
if cnt1=20000 then cnt1:=0; if cnt2=10000 then cnt2:=0; clk_1s<=not clk_1s; else cnt2:=cnt2+1; end if; else cnt1:=cnt1+1;
end if; end if; end process; process(rst,clk_hz) begin
二、设计方案： （1）、采用状态机的方式，用点阵在硬件上实现各种花形彩
灯，并使用复位键 (2)、用 0.25s 和 0.5s 两种频率的选择，并采用按键控制输出 （3）、对于点阵的扫描是采用了 1s
三、 程序语言：
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ห้องสมุดไป่ตู้
USE IEEE.std_logic_ARITH.ALL;
when others=>light<="00000000"; end case; when s3=> if cnt4="100" then
cnt4<="000"; else cnt4<= cnt4+1; end if; case cnt4 is when "000"=>light<="01110111"; when "001"=>light<="00110011"; when "010"=>light<="00010001"; when "011"=>light<="00000000"; when "100"=>light<="11111111"; when others=>light<="00000000"; end case; when s4=> if cnt5="1111" then cnt5<="0000"; else cnt5<=cnt5+1; end if; case cnt5 is when "0000"=>light<="10000000";
if(rst='0')then state<=s0;
elsif(clk_1s'EVENT AND clk_1s='1')then case state is when s0 => state <=s1; when s1 => state <=s2; when s2 => state <=s3;
when s3 => state <=s4; when s4 => state <=s0; end case; end if; end process; ---------------------------------------------------------process(state,clk_hz) begin if rst='0' then light<="00000000"; else if(clk_hz'EVENT AND clk_hz='1')then case state is when s0=> if cnt1="1111" then cnt1<="0000"; else cnt1<= cnt1+1; end if; case cnt1 is when "0000"=>light<="01111111"; when "0001"=>light<="00111111";
USE IEEE.std_logic_UNSIGNED.ALL;
----------------------------------------------------
ENTITY caideng IS
port
(
clk,rst:INstd_logic;
---------------12--------------
BEGIN
hang<="11111111";
--------------------频率选择-----------------
process(clk)
variable cnt1:integer range 0 to 6250000;------------4hz
即 0.25s
variable
cnt2:integer
cnt3<="000"; else cnt3<=cnt3+1; end if; case cnt3 is when "000"=>light<="01110111"; when "001"=>light<="00110011"; when "010"=>light<="00010001"; when "011"=>light<="00000000"; when "100"=>light<="10000001"; when "101"=>light<="11000011"; when "110"=>light<="11100111"; when "111"=>light<="11111111";
if cnt2=12500000 then cnt2:=0; clk_hz <=not clk_hz; else cnt2:=cnt2+1; end if; when others =>null; end case; end if; end process; --------------------------------------------------------process(clk) variable cnt1: integer range 0 to 20000; variable cnt2: integer range 0 to 10000; begin if clk'event and clk='1' then
);
end caideng;
architecture one of caideng is
type states is(s0,s1,s2,s3,s4);------表示状态------
signal state: states;
signal clk_hz,clk_1s:std_logic:='0';
signal cnt1:std_logic_vector(3 downto 0):="0000";
when "001"=>light<="11000011"; when "010"=>light<="10000001"; when "011"=>light<="00000000"; when "100"=>light<="00000000"; when "101"=>light<="10000001"; when "110"=>light<="11000011"; when others=>light<="11100111"; end case; when s2=> if cnt3="111" then
signal cnt2:std_logic_vector(2 downto 0):="000";
signal cnt3:std_logic_vector(2 downto 0):="000";
signal cnt4:std_logic_vector(2 downto 0):="000";
signal cnt5:std_logic_vector(3 downto 0):="0000";
可编程逻辑器件应用
项 目 报 告 书
项目名称： 指导老师： 姓 名： 学 号： 班 级：
花样彩灯 龚兰芳 林晓新 100212126 10 电子 1 班
广东水利电力职业技术学院
一、设计要求-------------------------------------------------------------------------------二、设计目的-------------------------------------------------------------------------------三、设计方案-------------------------------------------------------------------------------四、设计程序--------------------------------------------------------------------------------五、管脚分配--------------------------------------------------------------------------------六、硬件下载实现现象描述-----------------------------------------七、体会、对设计工作的总结与展-------------------------------------------