模拟集成电路设计英文课件：Semi-conductor Device Physics
CMOS模拟集成电路设计教学课件(英文版)共33章25
Measurement:
This circuit probably will not work unless the op amp gain is very low.
CMOS Analog Circuit Design
© P.E. Allen - 2016
Lecture 25 – Measurement and Simulation of Op amps (6/25/14)
CL RL
VSS
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region. Divide (subtract dB) the result into the open-loop gain to get CMRR.
VSS
2.) The gain in the linear range 3.) The output limits
Fig. 240-01
4.) The systematic input offset voltage
5.) DC operating conditions, power dissipation
Page 25-4
A More Robust Method of Measuring the Open-Loop Frequency Response Circuit:
VDD
vIN
vOUT
CR
CL RL
Resulting Closed-Loop Frequency Response:
dB Av(0)
Simulation:
vIN +VOS-
This circuit will give the voltage transferould identify:
英文版模拟电子技术课件第一章
Introduction of The Course
• Program of the course About 2-8th weeks：analog section About 9-15th weeks：digital section
Intrinsic materials are those semiconductors that have been carefully refined to reduce the impurities to a very low levelessentially as pure as can be made available through modern technology.
the main object in this course
SEMICONDUCTOR MATERIALS
Semiconductors are a special class having a conductivity between that of a good conductor and that of an insulator.the three semiconductors used most frequently in the construction of electronic devices are germanium-Ge,silicon-Si and gallium arsenide-GaAs.
si
GGee
silicon
germanium
Chapter 1 Semiconductor Diodes
1.2 Semiconductor Materials 1.3 intrinsic Semiconductor 1.4 Extrinsic Semiconductor 1.5 Semiconductor Diode 1.7 Resistance Levels 1.8 Diode Equivalent Circuits
CMOS模拟集成电路设计教学课件(英文版)共33章20
VNBias2
vOUT M2
VNBias2 Rin1
vOUT M2
VNBias2 Rin2
vIN
VNBias1 M1
vIN
VNBias1 M1 vIN
VNBias1
VDD M3
vOUT M2
M1 vIN
VPBias1 VPBias2
VNBias2 Rin3
VNBias1
VDD M4 M3 vOUT M2
VDD M3vOUT
VNBias2 M2
M1 vIN
060609-05
Advantages of the cascode amplifier: • Increases the output resistance and gain (if M3 is cascoded also) • Eliminates the Miller effect when the input source resistance is large
Rin1
=
rds2 1+gm2rds2
≈
1 gm2
Rin2
=
rds2+rds3 1+ gm2rds2
≈
2 gm2
Rin3
=
rds2+rds4gm3rds3 1+ gm2rds2
≈
rds!!!
The input resistance of the common gate configuration depends on the load at the drain.
IBias vIN
vOUT VDD
VNBias1 M1
060609-01
VON3
VON1+VON2 VON1
模拟电路分析与设计英文pptch1
Ch1. Semiconductor Materials and Diodes
1.1 Semiconductor Materials and Properties 1.2 The PN Junction 1.3 Diode Circuits DC Analysis and Models 1.4 Diode Circuits AC Equivalent Circuit 1.5 Other Diode Types 1.6 Design Application: Diode Thermometer 1.7 Summary
+4
+4
+4
+4
Each Si atom shares one electron with each of its four closest neighbors so that its valence band will have a full 8 electrons.
模拟集成电路设计流程PPT课件
2020/11/14
共88页
1
模拟集成电路的设计流程
1.交互式电路图输入
全定制
2.电路仿真（spectre）
3.版图设计 （virtuoso）
4.版图的验证（DRC LVS） （calibre）
5.寄生参数提取（calibre）
6.后仿真 （spectre）
RF器件模型文件，我们实验只用到普通器件，因此只需要前 者，电路仿真时Spectre会自动加载这几个文件
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6
相关工艺参数可以在ms018_v1p7_spe.mdl文件中查到：
N18：
Tox=3.87n (可由此算出Cox)
vth0=0.39(无衬偏效应)
u0=34m
P18：
Tox=3.74n
Vth0=-0.402
u0=8.6m
lambda的选取可以参照razavi书上的lambda与L成反比，
其中L＝0.5um时 lambdaN＝0.1,lmabdaP=0.2
2模020型/11中/14各工艺参数定义可参考bsimset.pdf文件共8。8页
7
建立新库、新单元以及新视图
按照如上方法添加所需要的 NMOS与PMOS以及电阻元件以及pin
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10
mos管的主要参数
multiplier 表示几个管子并联数 Length 表示沟道长度 ，设计时我们按照长沟道设
计L取值>＝1um Total Width 表示总的沟道宽度 Finger Width 表示一个finger的宽度 Fingers 表示finger的个数 Total width ＝ Finger witdth × Fingers 设计时尽量使mos管接近方形，而不是长条形
拉扎维《模拟集成电路设计》第二版课件 Ch13..
2
General Considerations
• In equivalent circuit of Fig. (b), we can write
• Hence,
• Closed-loop gain is inaccurate compared to when Rout =0
Copyright © 2017 McGraw-Hill Education. All rights reserved. No reproduction or distribution without the prior written consent of McGraw-Hill Education.
Copyright © 2017 McGraw-Hill Education. All rights reserved. No reproduction or distribution without the prior written consent of McGraw-Hill Education.
• Ddd
only if
Copyright © 2017 McGraw-Hill Education. All rights reserved. No reproduction or distribution without the prior written consent of McGraw-Hill Education.
Copyright © 2017 McGraw-Hill Education. All rights reserved. No reproduction or distribution without the prior written consent of McGraw-Hill Education.
格雷：模拟集成电路课件3-4
Chapter3Single-Transistor and Multiple-Transistor Amplifiers---Single-Transistor Amplifiers---Two-Transistor BJT Amplifier---Two-Transistor MOSFET Amplifier---Differential Amplifiers (Mismatch)DEVICE MISMATCH IN DIFEERENTIALAMPLIFIERSOutline---The general approach to analyzing mismatches ---Input voltage and current offset of BJTdifferential amplifiers---Input voltage offsets of MOS differential amplifiers---Small-Signal Characteristics of Unbalanced Diff.Amp.General MethodSuppose performance parameters p 1and p 2can be written as),,,(),,,(22221111L L z y x f p andz y x f p ==Ideally, x 1=x 2, y 1=y 2, z 1=z 2…,→p 1=p 2. But, in practice, they are not and an error exists:),,,,,,,(),(22211121L L z y x z y x f p p e Error ==where x1,y1,z1,…and x2,y2,z2,…can be expressed in terms of their difference and average values, For example,22121x x x andx x x +=−=∆MISMATCH ANALYSIS METHODS22121x x x andx x x +=−=∆xx x andxx x ∆−=∆+=⇒5.05.021thus,);5.0,5.0;5.0,5.0(),(21L y y y y x x x x f p p e ∆−∆+∆−∆+=Generally:x x <<∆, the following approximations canεεεε−≈++≈−111111orneglecting high power values of ).,.(2εεe i be concluded:INPUT VOLTAGE AND CURRENT OFFSET OF THE BJT DIFF. AMPLIFIERModel for Input Offset Voltage and CurrentBase width, base & collector doping level, effective emitter area, collector load resistance.•V OS :If v in =0)()(OS C TCOS C m C V R V I V R g v ∆=∆=∆If an offset exists in:21&C C R R )/(/)/()(_C C T m C C R OS C C C R R V g R v V R i v C ∆=∆=→∆=∆→If an offset exists in area or doping level, in I S)/(/)/(_/S S T m C I OS S C S V V S C I I V g i V I I I eI i S TBE ∆=∆=→∆=∆=∆→mOS C C C g V i i i =−=∆21•I OS :If an offset exists in i C ,→β/C OS i I ∆=)/)(/(/)()/)(/(/)/(__ββββββββC B OS C C C C C C R OS i i I i R R R R i I C ∆=∆=∆=∆=⇒RMS-sum (polarity of error is not important):2_2_2_2_&βOS R OS OS I OS R OS OS III VVV CSC+=+=DC performance:⎟⎟⎠⎞⎜⎜⎝⎛=⎟⎟⎠⎞⎜⎜⎝⎛−⎟⎟⎠⎞⎜⎜⎝⎛=⇒12212211ln ln ln S S C C T S C T S C T IDI I I I V I I V I I V V 22222221121121)()()()(A V Q D qn A V W N D qn I A V Q D qn A V W N D qn I CB B n i CB B A n i S CB B niCB B A n iS ====where W B (V CB )is the base width as a function of V CB , N A is theacceptor density in the base and A is the emitter area.122122110C C C C C C C C OD R R I I R I R I V =⇒=⇐=⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛=⇒)()(ln 211212CB B CB B C C T OSV Q V Q A A R R V V 021=+−BE BE ID V V VNow, define:222&212121CC C C C C C C C C C C R R R and R R R R R R R R R ∆−=∆+=⇒+=−=∆222&212121AA A and A A A A A A A A A ∆−=∆+=⇒+=−=∆222&212121BB B B B B B B B B B B Q Q Q and Q Q Q Q Q Q Q Q Q ∆−=∆+=⇒+=−=∆Substituting these values into the expression for V OS gives⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛∆−⎟⎠⎞⎜⎝⎛∆−⎟⎟⎠⎞⎜⎜⎝⎛∆−≈⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎣⎡⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛∆+∆−⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛∆+∆−⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛∆+∆−=B B C C T BB BB C C C C T OSQ Q A A R R V Q Q Q Q A A A A R R R R V V 111ln 222222ln BB C C Q Q and A A R R <<∆<<∆<<∆,Expanding the logarithm and neglecting higher order terms gives⎟⎟⎠⎞⎜⎜⎝⎛∆−∆−=⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−∆−≈S S C C T B B C C T OSI I R R V Q Q A A R R V V whereBBS S Q Q A A I I ∆−∆=∆Example:05.0&01.0//==∆∆SSI IR R σσmV mV I I R R V V S S C C T OS 5.1)05.001.0)(26(−=+=⎟⎟⎠⎞⎜⎜⎝⎛∆−∆−≈mVmV V V SS CC I I R R T OS 3.1)05.0()01.0()26(22/2/2=+=+=∆∆σσCalculation of dV OS /dT:Assuming V OS (270C)=2mV,K V KmVT T V T V or I I R R T V T V OS OS S S C C T OS /67.63002)(µ=≈=∂∂⎟⎟⎠⎞⎜⎜⎝⎛∆+∆=∂∂Offset voltage can be cancelled using external circuitrybut to cancel the temperature drift, the external circuitry must have the temperature dependence.Temperature Dependence of the Input Offset VoltageThe input offset current of the BJT Differential Amplifier can be written as :112212215.0&5.0F C F C B B OS OS B B OS B B I I I I I I I I I I I ββ−=−=⇒−=+=Define:222&222&212112212112FF F F F F F F F F F F CC C C C C C C C C C C and I I I and I I I I I I I I I ββββββββββββ∆+=∆−=⇒+=−=∆∆+=∆−=⇒+=−=∆Input Offset Current of the BJT Differential AmplifierqCombining the previous expressions into the function for I OS gives:FF C C F F CC F C F FC C F F C C OS I I when I I I I I I I I βββββββββ<<∆<<∆⎟⎟⎠⎞⎜⎜⎝⎛∆−∆≈⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛∆−∆−−∆+∆+=,2222, then,CCC C CC CCC C C C R R I I R R R R I I I I ∆=∆−⇒∆+∆−=∆+∆−21212121122122110C C C C C C C C OD R R I I R I R I V =⇒=⇐=Therefore,⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−=FFC C F C OSR R I I βββINPUT VOLTAGE OFFSET OF THE MOSFETDIFF. AMPLIFIERModel for Input Offset Voltage•V OS : If v in =0mOS D D D g V i i i =−=∆21If an offset exists in:2/))(/(2/)/(_t GS D D D D D R OS V V R R I R v V D −∆=∆=→β21&D D R R LW k '=βDD D D D D R v i orR i v /)(∆=∆∆=∆→If),,('k L W or ∆∆∆∆β2/))(/(2/)/(2/)/(/_t GS D D D m D OS V V I I I g i V −∆=∆=∆=∆=βββββββββ),()(/)]}(2[2{/22_t tt tt GS t GS t t m D V OS V Vt small is V if V V V V V V V g i V t ∆<<∆∆∆≈−−∆+∆=∆=ββIf exists:•I OS =0tV ∆2'21'1212'221'1121)/(2)/(2)/(2)/(20L W k I L W k I V V L W k I V L W k I V V V V V D D t t D t D t ID GS GS ID −+−=−−+=⇒=+−122122110D D D D D D D D OD R R I I R I R I V =⇒=⇐=DC performance:Define:222&212121DD D D D D D D D D D D R R R and R R R R R R R R R ∆−=∆+=⇒+=−=∆222&212121ββββββββββββ∆−=∆+=⇒+=−=∆and 222&212121DD D D D D D D D D D D I I I and I I I I I I I I I ∆−=∆+=⇒+=−=∆222&212121tt t t t t t t t t t t V V V and V V V V V V V V V ∆−=∆+=⇒+=−=∆Substituting these values into the expression for V OS givestD D D t D D D D D t D D D D D tt t t D D D D OSV I I I V I I I I I V I I I I I V V V V I I I I V ∆+⎥⎦⎤⎢⎣⎡∆−∆=∆+⎥⎦⎤⎢⎣⎡∆+∆−−∆−∆+=∆+⎥⎦⎤⎢⎣⎡∆+∆−−∆−∆+=∆−−∆++⎟⎟⎠⎞⎜⎜⎝⎛∆−∆−−⎟⎟⎠⎞⎜⎜⎝⎛∆+∆+=βββββββββββββββββ222)221()221(2)21)(21()21)(21(2)2()2(5.05.025.05.02where,tt D D D D V V and I I R R <<∆<<∆<<∆<<∆,,,ββWhen the variation in 3 parameters are uncorrelated:mV V V R R V V V V t GS D D t GS t OS1072)(2)(22222=⎟⎟⎠⎞⎜⎜⎝⎛∆−+⎟⎟⎠⎞⎜⎜⎝⎛∆−+∆=ββVV V mV V R R t GS t D D 5.1&100%,5/%,1/=−=∆=∆=∆ββFor the correlated case:mV R R V V V V D D t GS t OS5522)(=⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−−∆=ββ⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−∆≈⇒∆−=∆βββ222D D D t OS D D D D R R I V V R R I I tGS DV V I −=β2⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−−∆=⇒ββ22)(D D t GS t OSR R V V V VTemperature Dependence of the MOS InputOffset Voltage⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−∆=βββ222D D D t OS R R I V V TT T T T T dT d T T T L WT k T )(5.1)/)((5.1)()()(5.1005.100'βββββ−=−=⇒⎟⎟⎠⎞⎜⎜⎝⎛==−−⎟⎟⎠⎞⎜⎜⎝⎛+∂∂⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−=⎟⎟⎠⎞⎜⎜⎝⎛∂∂−∂∂⎟⎟⎠⎞⎜⎜⎝⎛∆+∆−=2/12/342322122 22122122βββββββββT I T I I R R T I T I I R R dT dV DD D D D D D D D D OSepredictabl T V T ∝epredictabl so not T T I D ∂∂∂∂β&R D , ,V tR C , (A, Q B ) →I SV OSV OS , I OS MOSFETBJT ↓⇒↑OS dm V A SUMMARYβ22221121221121R i R i v v v R i R i v v v c d +=+=−=−=2/)(,&,2/)(,21212121R R R R R R i i i i i i c d +=−=∆+=−=21R R ≠if:Definite:4)(2)2)(2()2)(2()()2)(2()2)(2(R i R i R R i i RR i i v R i R i RR i i RR i i v d cd c dc c cd d c dc d ∆+=∆−−+∆++=∆+=∆−−−∆++=Half circuitSMALL-SIGNAL CHARACTERISTICS ofUNBALANCED DIFF. AMP.2/)(,&,2/)(,21212121m m m m m m c d g g g g g g v v v v v v +=−=∆+=−=42)2)(2()2)(2( 22 )2)(2()2)(2( 221121221121d m c m d c mm d c m m m m c cm d m dc m md c m m m m d v g v g v v g g v v g g v g v g i i i v g v g v v g g v v g g v g v g i i i ∆+=−∆−++∆+=+=+=∆+=−∆−−+∆+=−=−=⇒21m m g g ≠Definite:if:22&0222=+∆+=∆++Rc idm m mid m Rd i v g v g v g v g i tail Rc ic tail ic r i v v v v 2+=−=)212()212(22tailm m tail m m ic tail m mtailm m id Rd r g g r g g v r g g r g g v i +∆+∆−++∆∆+−=tailm idm ic m Rc r g v g v g i 2122+∆+−=⇒⎟⎟⎠⎞⎜⎜⎝⎛+∆+∆−==+∆−∆∆+−====tail m m m v icoddmcm tailm m m tailm m v idod dmr g R g R g v v A r g Rg R g r g R g v v A id ic 21212220_0R i R i v RdRc od 222+∆=icdm cm id dm od v A v A v _+=Ri R i v Rc Rd oc +∆=22iccm id cm dm oc v A v A v +=_⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛+∆∆+−==⎥⎥⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎢⎢⎣⎡+⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛∆∆−∆+∆−====tail m m m v ic oc cm tail m m m tail m m m m v id oc cm dm r g R g R g v v A r g g g r g R g R g R g v v A id ic2122212241020_SUMMARY•Differential Mode and Common Mode •Characteristics of Differential Amplifier •CMRR•ICMR•Offset Voltage•Mismatch。
模拟集成电路(课件)
−3
Φ B = Φ F (p ) − Φ F (n ) = 0.53 − (− 0.35) = 0.88V
P-N结耗尽区
耗尽区宽度：
⎤ ⎡ 2ε 0ε si Φ B NA xn = ⎢ ⎥ q N D (N A + N D )⎦ ⎣
1 2
⎤ ⎡ 2ε 0ε si Φ B ND xp = ⎢ ⎥ q N A (N A + N D )⎦ ⎣
– CAD
• 难以利用自动设计工具
模拟集成电路设计步骤
模拟集成电路设计步骤
电路设计
物理版图设计
根据工艺版图设计规则设计器件、器件之间的互联、 电源和时钟线的分布、与外部的连接。
电路测试
电路制备后对电路功能和性能参数的测试验证。
层次设计
描述格式 设计 电路层次 系统 系统说明/仿真 Matlab、ADMS… 电路性能 netlist /simulation 版图布局 layout 参数化模块/单元 layout 行为模型 物理 模型
P-N结
• 讨论P-N结反偏和耗尽区电容对了解寄生电容是 十分重要的
– 假定P是重掺杂，N是轻掺杂。
E
P+
Xp Xn
N−
耗尽区
– 空穴从P扩散到N区，留下固定的负电荷。在N区同样 会留下固定的正电荷，在界面处建立了电场。 扩散电流 = 漂移电流
P-N结耗尽区
PN结内建势
kT N A N D Φ B = Φ F (p ) − Φ F (n ) = ln q n i2
半导体器件和模型
• 半导体PN结 • MOS器件
– 基本概念 – 阈值电压 – I/V特性 – 二级效应 – 器件模型
本征半导体
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Ch5 Current Source
6
1. Device Physics
• 1.1 Basic
– 1.1.1 Structure of MOSFET
（NFห้องสมุดไป่ตู้T）
• 栅（G: gate）、源（S: source）、漏（D: drain）、衬底（B: bulk）
ΦMS is the difference between the work functions of polysilicon gate and the sillicon substrate；
q is electron charge, Nsubis the doping concentration, Qdepis the charge in the depletion, Cox is the gate oxide capacitance per unit area;
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• MOSFET: 4-terminals device
• CMOS process
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N阱
8
– 1.1.2 MOS symbol
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• 1.2 I/V characteristic of MOS
– 1.1.1 Threshold voltage
Over-drive VDSAT＝VGS-VTH
VGS
• Cut-off (VGS<VTH) ID＝0
When VGS≥VTH,
• Triode（linear region）（VDS<VGS-VTH）
• Saturation region（VDS≥VGS-VTH）
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PMOS
Actual direction
（NFET）
耗尽depletion (b); 反型开始onset of inversion (c)； 反型inversion（d）
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• Threshold （VTH）
The VTH of an NFET is usually defined as the gate voltage for which the interface is “as much n-type as the substrate is p-type.” ( NFET的VTH通常定义为界面 的电子浓度等于P型衬底的多子浓度时的栅压。)
2
Why Analog Integrated Circuits?
Eggshell Analogy of Analog IC Design (Paul Gray)
Why CMOS Analog Integrated Circuits?
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• 0.2 Design Flow of Analog IC
其中，γ为体效应系数
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VTH 0
VTH
15
– 1.3.2 Channel-length modulation
The actual length of the inverted channel gradually decreases as the potential difference of VDS increases. i.e. L’ is in fact a function of VDS.
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• 0.3 Analog and Mixed-signal IC
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0.4 structure of the course
AD/DA
PLL
Systems complex
Ch12 Switch capacitor
Ch14 oscillator
Ch9 opamp
Ch10 stability and freq. compensation
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εsi denotes the dielectric constant. 11
• “native” VTH
The native threshold value obtained from above equation may not be suited to circuit design, typically VTH=0±0.1V.
Design of Analog Integrated Circuits
Introduction Semi-conductor Device Physics
and Model
Outline
• 0. Introduction • 1. MOS Device Physics and Model
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ID reference direction
• Cutoff region ID＝0 • Triode（linear region）
• Saturation region
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• 1.3 Second-order effects
– 1.3.1 Body effect
For NMOS, when VB<VS, As VB becomes more negative, Qd increases before an inversion layer is formed, thus VTH also increases. This is called the “body effect” or the “backgate effect”.
It is typically adjusted bye implantation of dopants into the channel area during device fabrication.
For NMOS，typically adjusted to 0.7V.
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– 1.1.2 I/V of MOS device NMOS
Ch13 nonlinear and mismatch
Ch11 Band-gap Reference
Ch6 frequency response
Ch7 Noise
Ch8 Feedback
Ch3 single-stage amp. simple Circuits
Devices
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Ch4 differential amp.