Clock Gating Methodology for Power and CTS QoR

– Overview – RTL synthesis
±Methodology ±Clock gating considerations
– Physical synthesis – Clock tree synthesis – Summary of recommendations
• Sample results • Planned enhancements • Summary
less than 3
RTL Synthesis
12
Insert Clock Gating During RTL Synthesis
• Use the insert_clock_gating command
The -global option looks across hierarchical boundaries
• Easy to implement
– No RTL code change is required – Clock gating is automatically inserted by the tool – Technology independent
7
Agenda
• Objective • Introduction to clock gating • Clock gating methodology
Clock Gating Methodology for
Power and CTS QoR
2
Agenda
• Objective • Introduction to clock gating • Clock gating methodology
– Overview – RTL synthesis – Physical synthesis – Clock tree synthesis – Summary of recommendations
10
Clock Gating Methodology During RTL
Synthesis
Input RTL
RTL Synthesis
SSeettththeecclolocckkggaatitninggsstytylele sseett__cclloocckk__ggaattiinngg__ssttyyllee
13
Measure the Quality of Inserted Clock
Gating: Report Power and Clock Gating
• Use the report_power command
Cell Internal Power Net Switching Power
Total Dynamic Power
14
Agenda
• Objective • Introduction to clock gating • Clock gating methodology
– Overview – RTL synthesis
±Methodology ±Clock gating considerations
– Physical synthesis – Clock tree synthesis – Summary of recommendations
• Sample results • Planned enhancements • Summary
3
Objective
• Describe the clock gating methodology to meet target
– Skew – Insertion delay – Power
• Discuss recommendations during
– Gated by the enable signal, the clock network has less switching activity and consumes less switching power
• Area savings
– Eliminating multiplexers saves area
MMeergrgeecclolocckkggaatetess
MMeergrgeecclolocckkggaatetess
PPlalacceemmeennt taannddpplalacceemmeennt t oopptitmimizizaatitoionn
PPlalacceemmeennt taannddpplalacceemmeennt t oopptitmimizizaatitoionn
• Impact of clock gate fanout on
– Power and enable pin timing – Clock tree structure
RTL Synthesis
16
Clock Gate Styles
• Integrated, latch-based, clock gate (ICG) is recommended
Design Compiler X-2005.09
DDeetataililrorouutitningg
IC Compiler v1.1
Physical Compiler X-2005.09
Astro X-2005.09
Unified Flow in IC Compiler
9
Agenda
• Objective • Introduction to clock gating • Clock gating methodology
– Overview – RTL synthesis – Physical synthesis – Clock tree synthesis – Summary of recommendations
• Sample results • Planned enhancements • Summary
8
Clock Gating Methodology Overview
Input RTL
DDeessigignnCCoommppilielerr
InInsseertrtcclolocckkggaatitningg CCoommppiliele
ICICCCoommppilielerr
PPhhyyssicicaal lCCoommppilielerr
RReeaaddininVVeerriliologg rreeaadd__vveerriilloogg
DDeefifnineeththeecclolocckkss ccrreeaattee__cclloocckk
InInsseerrttcclolocckkggaatitningg iinnsseerrtt__cclloocckk__ggaattiinngg
CCoommppiliele ccoommppiillee
11
Specify Clock Gating Options
• Use the set_clock_gating_style command
• Maximum fanout
– This value is the maximum fanout of each clock gating element
• Sample results • Planned enhancements • Summary
5
What is Clock Gating?
• Register banks disabled during some clock cycles
– Typical implementation uses multiplexers – Clock gating cell replaces multiplexers
------------------------------------------------------------
| Number of Clock gating elements |
222
|
|
|
|
| Number of Gated registers
| 167512 (99.92%) |
|
|
• Discrete, latch-based or latch-free (simple AND or OR-AND gate) clock gates are also supported
– Discrete clock gates are not recommended (details on next slide)
= 160.6544 mW = 102.5581 mW
--------= 263.2125 mW
(61%) (39%)
(100%)
Cell Leakage Power = 3.0961 mW
• Use the report_clock_gating command
Clock Gating Summary
D EN CLK
Q
High activity
EN CLK
D
Q
gclk
Low activity
6
Benefits of Clock Gating
• Dynamic power savings
– With low toggle rate on clock pin, internal power of registers is reduced
– By default, the fanout is unlimited
• Minimum bitwidth
– This is the minimum bitwidth of register banks that will be gated
– By default, the minimum bitwidth is 3 – No area or power benefit with register banks with bitwidth