Xilinx spartan3e FPGA掉电配置及应用程序引导

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FPGA应用程序烧写

FPGA掉电配置及应用程序引导Xilinx公司的spartan3e开发板上面有丰富的外围器件，就存储器来说有一个16M并行flash，一个4Mbits串行flash，还又一个64M的DDR，在嵌入式开发中，一般我们可能会在FPGA中嵌入cpu软核，让C语言程序在里面运行。

这就涉及到FPGA配置文件的引导，如果C语言程序太大，需要在DDR里面运行的话也涉及到应用程序的引导的问题。

我刚接触到xinlinx的spartan3e开发板时，只会将FPGA配置文件（.bit）直接通过JTAG口下载到芯片里。

后来编写的程序大了，如果将程序直接放到内部的RAM里面就装不下了，这时就只有将程序放到DDR里面运行，如果仅仅是调试应用程序不需要重启开发板后程序也可以运行，那么可以直接用EDK里面的XDM工具通过dow命令直接下载到DDR里面，然后就可以执行了。

但是我们的应用程序和硬件配置调试通过，达到了我们的要求以后我们就想到可不可以将让程序在板子上电时就可以自动运行呢。

因为FPGA是掉电要丢失的，重新上电就必须重新配置。

我们通过查找相关资料，找到了解决烧写问题的解决办法。

首先是配置文件的烧写。

spartan3e提供了3个掉电不丢失的外部存储器，就是上面提到的并行flash，串行flash和Flash PROM。

配置文件都可以烧写到其中任何一个储存器里面。

但是，在我看来，一般的配置问件都是烧写到Flash PROM里面。

烧写方法有很多，可以用Xilinx公司的专门的烧写.mcs文件的工程烧写，也可以用iMPACT烧写。

一般用iMPACT工具烧写，烧写过程如下：打开iMPACT，弹出新建工程时选择Cancle，然后双击窗口左边的PROM File Formater 如下图：弹出的窗口中选择Xilinx PROM文件格式选择mcs，PROM File name为：test.mcs，选择好保存路径点击下一步如下图：上步中点击Next，Select a PROM（bits）选择xcf->xcf04s,点击Add，然后点下一步如下图：上图中点击Next后出现窗口中点击filinsh，弹出消息框点OK，会有一个选择bit问件的窗口，选择一个已经编写好的EDK或者ISE工程生成的.bit文件，OK后提示是否加入其他器件，选择NO，然后双击窗口右边的Generate File，生成.mcs文件如下图所示：然后，双击Boundary Scan，在中间空白处，点击鼠标右键，选择Initialize chain，弹出的第一个窗口中选择Bypass，第二个选择刚才生成的.mcs文件，第三个也选择Bypass，然后选中中间那个模块，点击窗口左下角的program如下图：弹出窗口中选中OK就可以了，烧写完后会看到，Program Successful提示。

Xilinx_FPGA中文教程

Spartan-3E Starter Kit Board User GuideChapter 1: Introduction and OverviewChapter 2: Switches, Buttons, and KnobChapter 3: Clock SourcesChapter 4: FPGA Configuration OptionsChapter 5: Character LCD ScreenChapter 6: VGA Display PortChapter 7: RS-232 Serial PortsChapter 8: PS/2 Mouse/Keyboard PortChapter 9: Digital to Analog Converter (DAC)Chapter 10: Analog Capture CircuitChapter 11: Intel StrataFlash Parallel NOR Flash PROM Chapter 12: SPI Serial FlashChapter 13: DDR SDRAMChapter 14: 10/100 Ethernet Physical Layer Interface Chapter 15: Expansion ConnectorsChapter 16: XC2C64A CoolRunner-II CPLDChapter 17: DS2432 1-Wire SHA-1 EEPROMChapter 1：Introduction and OverviewSpartan-3E 入门实验板使设计人员能够即时利用Spartan-3E 系列的完整平台性能。

设备支持设备支持：：Spartan-3E 、CoolRunner-II关键特性关键特性：：Xilinx 器件: Spartan-3E (50万门，XC3S500E-4FG320C), CoolRunner™-II (XC2C64A-5VQ44C)与Platform Flash(XCF04S-VO20C)时钟时钟：：50 MHz 晶体时钟振荡器存储器: 128 Mbit 并行Flash, 16 Mbit SPI Flash, 64 MByte DDR SDRAM连接器与接口: 以太网10/100 Phy, JTAG USB 下载,两个9管脚RS-232串行端口, PS/2类型鼠标/键盘端口, 带按钮的旋转编码器, 四个滑动开关,八个单独的LED 输出, 四个瞬时接触按钮, 100管脚hirose 扩展连接端口与三个6管脚扩展连接器显示器: VGA 显示端口，16 字符- 2 线式 LCD电源电源：：Linear Technologies 电源供电，TPS75003三路电源管理IC 市场: 消费类, 电信/数据通信, 服务器, 存储器应用: 可支持32位的RISC 处理器，可以采用Xilinx 的MicroBlaze 以及PicoBlaze 嵌入式开发系统；支持DDR 接口的应用；支持基于Ethernet 网络的应用；支持大容量I/O 扩展的应用。

FPGA入门教程-Spartan-3A

一直装不Modelsim 或者装上了又用不了的同学，如果你的ISE 版本比较高的话，展开这栏选择Isim，是 ISE自带的仿真工具，这个也可以的。
如图右键点击xc3s500e-4fg320，选择New Source。
选择VHDL Module，右侧输入文件名（文件名不能由数字开头），点Next进入下一步。
NET "LED<10>" LOC = "K14" ; NET "LED<11>" LOC = "K15" ; NET "LED<12>" LOC = "J16" ; NET "LED<13>" LOC = "K16" ; NET "LED<14>" LOC = "H14" ; NET "LED<15>" LOC = "J14" ; NET "clk" LOC = "P9" ;
提醒一下还是找不到UCF文件的人，请注意你们选的是不是红色框框里Implementation 选择图中选的Simulation是用来仿真的，平时想Modelsim 上观察波形的时候才点这里。
什么是UCF？
UCF全称为User Constraints File，即用户约束文件。 ISE中有多种用户约束，如管脚位置约束，区域约束，时序约束以及电平约束。
NET "LED<0>" LOC = "M14" ; NET "LED<1>" LOC = "M13" ; NET "LED<2>" LOC = "K13" ; NET "LED<3>" LOC = "L13" ; NET "LED<4>" LOC = "M16" ; NET "LED<5>" LOC = "M15" ; NET "LED<6>" LOC = "L16" ; NET "LED<7>" LOC = "L14" ; NET "LED<8>" LOC = "J13" ; NET "LED<9>" LOC = "J12" ;

SPARTAN-3E说明书第13章

Spartan －3E 开发板包括一个Micron Technology 公司的512Mbit （32Mx16）容量16位接口DDR SDRAM （MT46VM16），如图13－1所示。

DDR SDRAM 的所有管脚都连接到FPGA 的I/O Bank3。

I/O Bank3和DDR RAM 需要的2.5V 电源由LTC3412稳压芯片从板上5V 电源得到。

FPGA 和DDR SDRAM 共用的1.25V 的参考电压由2.5V 经电阻分压得到。

图13－1：Micron 512Mbit DDR SDRAM 的FPGA 接口DDR RAM 接口的所有信号都接有终端电阻。

第十三章DDR SDRAM UG230_c13_01_022406差分时钟脚SD_CK_P被反馈到FPGA的I/O Bank0的B9脚，以使FPGA的数字时钟管理器（DCM）获得最好效果。

MicroBlaze处理器的OPB DDR控制器需要连接这个时钟路径。

MicroBlaze处理器的OPB DDR控制器的IP核的相关文档可从EDK8.1i开发软件内获得(见107页“相关资源”)。

DDR SDRAM的连接表13－1显示FPGA与DDR SDRAM的连接。

表13－1 FPGA与DDR SDRAM的连接类型DDR SDRAM信号名FPGA管脚号功能SD_A12 P2SD_A11 N5SD_A10 T2SD_A9 N4SD_A8 H2SD_A7 H1SD_A6 H3SD_A5 H4SD_A4 F4SD_A3 P1SD_A2 R2SD_A1 R3地址SD_A0 T1地址输入表13－1 FPGA与DDR SDRAM的连接（续）种类DDR SDRAM信号名FPGA管脚号功能SD_DQ15 H5SD_DQ14 H6SD_DQ13 G5SD_DQ12 G6SD_DQ11 F2SD_DQ10 F1SD_DQ9 E1SD_DQ8 E2SD_DQ7 M6SD_DQ6 M5SD_DQ5 M4SD_DQ4 M3SD_DQ3 L4SD_DQ2 L3SD_DQ1 L1数据SD_DQ0 L2数据IOSD_BA1 K6SD_BA0 K5Bank地址输入SD_RAS C1SD_CAS C2SD_WE D1命令输入SD_CK_N J4SD_CK_P J5差分时钟输入SD_CKE K3 时钟使能输入，高电平有效SD_CS K4 片选输入，低电平有效SD_UDM J1 SD_LDM J2 数据屏蔽。

Xilinx公司Spartan3系列配置电路

1.上电后，FPGA 芯片内部时钟开始工作；2.PROM 接收到FPGA 传来的时钟信号后，开始工作；3.PROM 把CF 脚拉低，也就是把FPGA 的PROG/PROG_B 拉低；4.FPGA 检测到PROG 信号有超过500纳秒的低脉冲后，FPGA 开始清除内部已有的配置（打扫房间），以待新的配置数据可以被接收。

PROG 由低返回高后，FPGA 立即把DONE 和INIT_B 都拉低，而这两个一个是PROM 的使能信号，一个是PROM 的RESET 信号，CLK 12CE13OE/RESET 11BUSY5EN_EXT_SEL25REV_SEL127REV_SEL026CF6CEO10CLKOUT9D028D129D232D333D443D544D647D748Configuring in FPGA Master Serial ModeMaster Serial configuration mode (shown in Figure2-1) is most commonly used withconfiguration PROMs, because it is simple to implement. Only a small number of signals arerequired to interface the PROM with the FPGA, and an external clock source is not requiredfor configuration. In FPGA Master Serial mode, the FPGA generates the configuration clock.In this mode, data is available on the PROM Data (D0) pin when CF is High, and CE and OEare enabled. New data is available a short access time after each rising clock edge.Figure 2-1:FPGA Master Serial Configuration SetupChoose a Configuration Mode: M[2:0]The mode select pins, M[2:0], define the configuration mode that the FPGA uses to load its bitstream, as shown in Table 2-1. The logic levels applied to the mode pins is sampled on the rising edge of INIT_B , immediately after the FPGA completes initializing its internal configuration memory.M[2:0] Functional Differences between Spartan-3 Generation FamiliesTable 2-2 summarizes the slight differences in functionality between the Spartan-3 generation families.Table 2-1:Mode Pin Settings and Associated FPGA Configuration Mode by FamilyM[2:0]FPGA FamilySpartan-3 Spartan-3ESpartan-3ASpartan-3A DSPSpartan-3AN<0:0:0>Master Serial (Platform Flash) Mode<0:0:1>Reserved Master SPI Mode<0:1:0>Reserved BPI Up <0:1:1>Master ParallelBPI DownReservedInternal MasterSPI<1:0:0>Reserved <1:0:1>JTAG Mode <1:1:0>Slave Parallel Mode <1:1:1>Slave Serial ModeTable 2-2:M[2:0] Mode Pin Differences between Spartan-3 Generation FPGAsSpartan-3 FPGASpartan-3E FPGAExtended Spartan-3A Family FPGAsAvailable as possible user I/O pin after configuration?No Yes Yes Dedicated internal pull-up resistor during configuration?YesNoYesMechanism to define post-configuration behaviorM2Pin , M1Pin , M0Pin bitstream options User I/O User I/OInput supply voltage V CCAUX V CCO_2V CCO_2Output supply voltageN/A V CCO_2V CCO_2Same voltage as other pins in the configuration interface?Only when interface is at2.5VYesYesProgram or Reset FPGA: PROG_BThe PROG_B pin is an asynchronous control input to the FPGA. When Low, the PROG_B pinresets the FPGA, initializing the configuration memory. When released, the PROG_B begins theconfiguration processes. The initialization process does not start until PROG_B returns High.Asserting PROG_B Low for an extended period delays the configuration process. The variousPROG_B functions are outlined in Table 2-7.At power-up or after a master reset, PROG_B always has a pull-up resistor to V CCAUX,regardless of the “Pull-Up Resistors During Configuration” control input. Afterconfiguration, the bitstream generator option ProgPin defines whether or not the pull-up resistoris remains active. By default, the ProgPin option retains the pull-up resistor.Table 2-7: PROG_B OperationAfter configuration, hold the PROG_B input High. Any Low-going pulse on PROG_B, lasting500 ns or longer (300 ns in the Spartan-3 FPGAs), restarts the configuration process.The PROG_B pin functionality is identical among all Spartan-3 generation FPGAs.Figure2-3 shows the basic point-to-point topology where the CCLK output from the Master FPGA drives one clock input receiver, either on the configuration PROM or on a slave FPGA.Caution!On Spartan-3E and Extended Spartan-3A family FPGAs, be sure to define a valid logic level on CCLK. Otherwise, the clock trace might float and cause spurious clocking to other devices in the system.Figure 2-3:Point-to-Point: Master CCLK Output Drives Single Clock Load Figure2-4 shows the basic multi-drop flyby topology where the CCLK output from the Master FPGA drives two or more clock input receivers. Constrain the trace length on any clock stubs.Figure 2-4:Multi-Drop: Master CCLK Output Drives Two Clock InputsFigure 2-5 shows a star topology where the Master FPGA CCLK transmission line branches to the multiple clock receiver inputs. The branch point creates a significant impedance discontinuity. Do not use this topology.ConfigRate: Bitstream Option for CCLKFor Master configuration mode, the ConfigRate bitstream generator option defines thefrequency of the internally-generated CCLK oscillator. The actual frequency isapproximate due to the characteristics of the silicon oscillator and varies by up to 50% over the temperature and voltage range. On Spartan-3E and Extended Spartan-3A family FPGAs, the resulting frequency for every ConfigRate setting is fully characterized and specified in the associated FPGA family data sheet. At power-on, CCLK always starts operation at its lowest frequency. Use the ConfigRate option to set the oscillator frequency to one of the other values shown in Table 2-8.Set this option graphically in “ISE Software Project Navigator,” page 42, as shown in Step 7 in Figure 1-7, page 44.The FPGA does not start operating at the higher CCLK frequency until the ConfigRate control bits are loaded during the configuration process.Persist: Reserve CCLK As Part of SelectMAP InterfaceBy default, any clocks applied to CCLK after configuration are ignored unless thebitstream option Persist :Yes is set, which retains the configuration interface. If Persist :Yes , then all clock edges are potentially active events, depending on the other configuration control signals. On Spartan-3E and Extended Spartan-3A family FPGAs, CCLK becomes a full-featured user-I/O pin after configuration.Figure 2-5:Star Topology Is Not RecommendedUG191_c2_07_112206Z 0ImpedanceDiscontinuityZ 0Clock Input 1Z 0Clock Input 2Clock In ock InpCCCLKMaster FPGAAs highlighted in Table 2-2, page 50, the Extended Spartan-3A family FPGAs add a few more dedicated internal pull-up resistors, as shown in Table 2-10. On Spartan-3E FPGAs, these pins do not have a dedicated internal pull-up resistor, but do have an optional pull-up resistor controlled when HSWAP =0.The Spartan-3 FPGA family uses dedicated configuration pins, as shown in Table 2-11. The post-configuration behavior is controlled by bitstream settings.Table 2-9:Pins with Dedicated Pull-Up Resistors during Configuration (All Spartan-3 Generation FPGAs)Pin Name Pull-Up Resistor SupplyRailPost Configuration ControlPROG_B V CCAUX ProgPin BitGen settingDONE V CCAUXDonePin and DriveDone BitGen settings Pull-up during Configuration control input,HSWAP , PUDC_B , or HSWAP_EN (see Table 2-12)VCCO_0Spartan-3E and Extended Spartan-3A family FPGAs: User I/O after configuration. Controlled by the FPGA applicationSpartan-3 FPGA: Controlled by HswapenPin BitGen settingINIT_BSpartan-3E/3A/3AN/ Spartan-3A DSP FPGAs:VCCO_2Spartan-3 FPGA:VCCO_4 or VCCO_BOTTOMUser I/O after configuration. Controlled by the FPGA applicationTDI V CCAUX TdiPin BitGen setting TMS V CCAUX TmsPin BitGen setting TCK V CCAUX TckPin BitGen setting TDOV CCAUXTdoPin BitGen settingTable 2-10:Pins with Dedicated Pull-Up Resistors during Configuration (Extended Spartan-3A Family FPGAs Only)Pin Name Pull-Up Resistor Supply RailPost Configuration ControlM[2:0]VCCO_2User I/O after configuration. Controlled by the FPGA applicationVS[2:0]VCCO_2Pull-up resistors only active when M[2:0]=<0:0:1>, Master SPI mode, or in Spartan-3AN FPGAs when M[2:0]=<0:1:1>, Internal Master SPI mode. User I/O after configuration. Controlled by the FPGA applicationPin DescriptionsTable 2-15 lists the various pins involved in the configuration process, including which configuration mode, the pin’s direction, and a summary description. The table also describes how to use the pin during and after configuration.Table 2-13:Pull-Up Resistor Ranges by Spartan-3 Generation FamilyVoltage RangeSpartan-3 FPGASpartan-3E FPGASpartan-3A/3ANSpartan-3A DSP FPGAUnitsV CCAUX or V CCO = 3.0 to 3.6V5.1 to 23.9k ΩV CCO = 3.0 to 3.45V 1.27 to 4.11 2.4 to 10.8V CCAUX or V CCO = 2.3 to 2.7V1.15 to 3.252.7 to 11.8 6.2 to 33.1V CCO = 1.7 to 1.9V2.45 to 9.104.3 to 20.28.4 to 52.6Table 2-14:Recommended External Pull-Up or Pull-down Resistor Values to Define Input Values during Configuration PUDC_B, HSWAP , orHSWAP_EN Desired Pull Direction I/O StandardSpartan-3 FPGASpartan-3E FPGASpartan-3A/3AN Spartan-3A DSPFPGA= 0(also applies to all pins that have a dedicated pull-up resistor during configuration, see “Pins with Dedicated Pull-Up Resistorsduring Configuration,”page 62)Pull-UpAll No pull-up required. Internal pull-up resistors areenabled. See Table 2-13 for resistor range.Pull-Down(required to overcome maximum I RPU current and guarantee V IL )LVCMOS33LVTTL ≤ 330 Ω≤ 620 Ω≤ 1.1k ΩLVCMOS25≤ 470 Ω≤ 820 Ω≤ 1.8k ΩLVCMOS18≤ 510 Ω≤ 820 Ω≤ 3.3k ΩLVCMOS15≤ 820 Ω≤ 1.2 k Ω≤ 5.4k ΩLVCMOS12≤ 1.5 k Ω≤ 1.5 k Ω≤ 9.6k Ω= 1(optional pull-up resistors are disabledduringconfiguration. Does not apply to pins with dedicated pull-up resistors during configuration)Pull-Up (required to overcome single-load, maximum I L leakage current and guarantee V IH )LVCMOS33LVTTL ≤ 40k Ω≤ 100k ΩLVCMOS25≤ 60k ΩLVCMOS18≤ 37k ΩLVCMOS15≤ 28k ΩLVCMOS12≤ 38k ΩPull-Down(required to overcome single-load, maximum I L leakage current and guarantee V IL )LVCMOS33LVTTL ≤ 32k Ω≤ 80k ΩLVCMOS25≤ 70k ΩLVCMOS18≤ 38k ΩLVCMOS15LVCMOS12≤ 59k ΩTable 2-15:Spartan-3 Generation Configuration Pins, Associated Modes, and FunctionPin Name Config.Mode(s)FPGADirectionDescription During Configuration After ConfigurationHSWAPor PUDC_Bor HSWAP_EN (depends on FPGA family)All Input User I/O Pull-Up Control.When Low duringconfiguration, enablespull-up resistors in all I/Opins to respective I/O bankV CCO input.0: Pull-ups duringconfiguration1: No pull-upsDrive at valid logiclevel throughoutconfiguration.Spartan-3:Dedicated pin (don’tcare afterconfiguration)Spartan-3ESpartan-3ASpartan-3ANSpartan-3A DSP:User I/OM[2:0]All Input Mode Select. Selects theFPGA configuration modeas defined in Table2-1.Must be at the logiclevels shown inTable2-1, page50.Sampled when INIT_Bgoes High.User I/O (dedicatedon Spartan-3 FPGAs)DIN SerialModes, SPI Input Serial Data Input. for allserial configuration modesReceives serial datafrom PROM serial dataoutput.User I/OCCLK MasterModes, SPI,BPIOutput(treat asI/O forsignalintegrity)Configuration Clock.Generated by FPGAinternal oscillator.Frequency controlled byConfigRate bitstreamgenerator option. See“Configuration Clock:CCLK,” page56.Drives PROM’s clockinput.User I/O (dedicatedon Spartan-3 FPGAs)Slave Modes Input Configuration clock input.Input configurationclock source.DOUT Output Serial Data Output. Not used in single-FPGA designs; DOUTis pulled up, notactively driving. In aserial daisy-chainconfiguration, this pinconnects to DIN inputof the next FPGA in thechain.User I/OINIT_B All Open-drainbidirec-tional I/O Initialization Indicator.Active Low. See“Initializing ConfigurationMemory, ConfigurationError: INIT_B,” page61.Drives Low afterpower-on reset (POR)or when PROG_Bpulsed Low while theFPGA is clearing itsconfiguration memory.If a CRC error detectedduring configuration,FPGA again drivesINIT_B Low.User I/O. If unusedin the application,drive INIT_B High orLow to avoid afloating value. SeeINIT_B “AfterConfiguration”.DONE All Open-drainbidirec-tional I/O FPGA ConfigurationDone. Low duringconfiguration. Goes Highwhen FPGA successfullycompletes configuration.Powered by V CCAUXsupply.0: FPGA not configured1: FPGA configuredSee “DONE Pin,” page52Actively drives Lowduring configuration.When High,indicates that theFPGA successfullyconfigured.PROG_B All Input Program FPGA. ActiveLow. When asserted Lowfor 500 ns or longer, forcesthe FPGA to restart itsconfiguration process byclearing configurationmemory and resetting theDONE and INIT_B pins. Ifdriving externally with a3.3V output, use an open-drain or open-collectordriver or use a currentlimiting series resistor. See“Program or Reset FPGA:PROG_B,” page56.Must be High duringconfiguration to allowconfiguration to start.Drive PROG_B Lowand release toreprogram FPGA.Spartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:VS[2:0]Master SPI Input Variant Select. Instructs theFPGA how to communicatewith the attached SPI FlashPROM.Must be at the logiclevels shown inTable4-2, page105.Sampled when INIT_Bgoes High.User I/OSpartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:MOSI Master SPI Output Serial Data Output. FPGA sends SPI Flashmemory readcommands andstarting address to thePROM’s serial datainput.User I/OSpartan-3E Spartan-3A Spartan-3AN Spartan-3A DSP FPGA:CSO_B Master SPI Output Chip Select Output. ActiveLow.Connects to the SPIFlash PROM’s SlaveSelect input. IfHSWAP/PUDC_B=1,connect this signal to a4.7 kΩ pull-up resistorto 3.3V.Drive CSO_B Highafter configuration todisable the SPI Flashand reclaim theMOSI, DIN, andCCLK pins.Optionally, re-usethis pin and MOSI,DIN, and CCLK tocontinuecommunicating withSPI Flash.Table 2-15:Spartan-3 Generation Configuration Pins, Associated Modes, and Function (Cont’d)Pin Name Config.Mode(s)FPGADirectionDescription During Configuration After ConfigurationSpartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:CSI_B Spartan-3FPGA:CS_B BPI, SlaveParallelInput Chip Select Input. ActiveLow.er I/O. If bitstreamoption Persist:Yes,becomes part ofSelectMap parallelperipheral interface.RDWR_B BPI, SlaveParallel Input Read/Write Control. ActiveLow write enable. Readfunctionality typically onlyused after configuration, ifbitstream optionPersist:Yes.Must be Lowthroughoutconfiguration. Do notchange logic levelwhile CSI_B is LowUser I/O. If bitstreamoption Persist:Yes,becomes part ofSelectMap parallelperipheral interface.Spartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:LDC0BPI Output PROM Chip Enable Connect to parallelPROM chip-selectinput (CS#). FPGAdrives this signal Lowthroughoutconfiguration.User I/O. If theFPGA does not accessthe PROM afterconfiguration, drivethis pin High todeselect the PROM.A[23:0], D[7:0],LDC[2:1], and HDCthen becomeavailable as user I/O.Spartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:LDC1BPI Output PROM Output Enable Connect to the parallelPROM output-enableinput (OE#). The FPGAdrives this signal Lowthroughoutconfiguration.User I/OSpartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:HDC BPI Output PROM Write Enable Connect to parallelPROM write-enableinput (WE#). FPGAdrives this signal Highthroughoutconfiguration.User I/OSpartan-3E Spartan-3A Spartan-3AN Spartan-3A DSPFPGA:LDC2BPI Output PROM Byte Mode This signal is not usedfor x8 PROMs. ForPROMs with a x8/x16data width control,connect to PROM byte-mode input (BYTE#).User I/O. Drive thispin High afterconfiguration to use ax8/x16 PROM in x16mode.Pin Name Config.Mode(s)FPGADirectionDescription During Configuration After ConfigurationPin Behavior During ConfigurationTable 2-16, Table 2-17, and Table 2-18 show how various pins on Spartan-3 generation FPGAs behave during the configuration process. The actual behavior depends on the settings applied to the M2, M1, and M0 (M[2:0]) mode select pins and the pin that controls the optional pull-up resistors, called HSWAP , PUDC_B , or HSWAP_EN depending on the specific Spartan-3 generation FPGA family. The M[2:0] mode select pins determine which of the I/O pins are active and borrowed during configuration and how they function. In JTAG configuration mode, no user-I/O pins are borrowed for configuration.The Dedicated Pull-Up Resistor column indicates pins that always have a pull-up resistor enabled during configuration, regardless of the PUDC_B , HSWAP , or HSWAP_EN input. After configuration, the behavior of these pins is either defined by specific bitstream generator options or by the FPGA application itself.Table 2-16, Table 2-17, and Table 2-18 show the FPGA pins that are either borrowed or dedicated during configuration. The specific pins are listed by FPGA configuration mode along the top. For each pin, the table also indicates the power rail that supplies the pin during configuration. A numeric value such as “2”, indicates that the associated pin is located in I/O Bank 2 and powered by the VCCO_2 supply inputs. Spartan-3E andExtended Spartan-3A family FPGAs have four I/O banks; the Spartan-3 FPGA family has eight I/O banks.The pin names are color-coded using the same colors used in the package pinout tables and footprint diagrams found in the respective Spartan-3 generation data sheet. Blackrepresents the dedicated JTAG pins; yellow represents the dedicated configuration pins; light blue represents the dual-purpose configuration pins that become user-I/O pins after configuration.Spartan-3E FPGA:A[23:0]Spartan-3ASpartan-3ANSpartan-3A DSPFPGA:A[25:0]BPIOutputParallel PROM Address outputsConnect to PROM address inputs.User I/O.D[7:0]Master Parallel, BPI, Slave Parallel,SelectMAPInput Data InputData captured by FPGAUser I/O. If bitstream option Persist :Yes , becomes part of SelectMap parallel peripheral interface.Spartan-3/Spartan-3E FPGA:BUSYBPI, Slave Parallel (SelectMAP )OutputFPGA Busy Indicator. Used primarily in Slave Parallel interfaces that operate at 50MHz and faster. Same function is on DOUT pin in the Extended Spartan-3A family.Not used during BPI mode configuration but actively er I/O. If bitstream option Persist :Yes , becomes part of SelectMap parallel peripheral interface.Pin Name Config. Mode(s)FPGA DirectionDescriptionDuring Configuration After ConfigurationSupported Platform Flash PROMsTable 3-4 shows the smallest available Platform Flash PROM to program one Spartan-3generation FPGA. A multiple-FPGA daisy-chain application requires a Platform Flash PROMlarge enough to contain the sum of the various FPGA bitstream sizes.Table 3-4: Number of Bits to Program a Spartan-3 Generation FPGA and SmallestPlatform Flash PROMFamily FPGANumber of Smallest Possible Configuration Bits Platform Flash PROMXC3S50A437,312XCF01SXC3S200A1,196,128XCF02S Spartan-3A XC3S400A1,886,560XCF02S (Spartan-3AN)XC3S700A2,732,640XCF04SXC3S1400A4,755,296XCF08Por XCF04S + XCF02SXC3SD1800A8,197,280XCF08PSpartan-3A DSP or two XCF04S PROMs XC3SD3400A11,718,304XCF16PXC3S100E581,344XCF01SXC3S250E1,353,728XCF02SSpartan-3E XC3S500E2,270,208XCF04SXC3S1200E3,841,184XCF04SXC3S1600E5,969,696XCF08Por XCF04S + XCF02SXC3S50439,264XCF01SXC3S2001,047,616XCF01SXC3S4001,699,136XCF02SXC3S10003,223,488XCF04S Spartan-3XC3S15005,214,784XCF08Por XCF04S + XCF02SXC3S20007,673,024XCF08Por 2 x XCF04SXC3S400011,316,864XCF16PXC3S500013,271,936XCF16PThere are two possible design solutions for FPGA designs that require 8 Mbit PROMs: use either a single 8 Mbit XCF08P parallel/serial PROM or two cascaded XCFxxS serial。

(ISE使用流程)逻辑设计实验

实验一ISE工具的使用流程--拨码开关控制LED实验1.1 实验目的1.学会ISE的基本开发流程和常用功能的使用，本实验直接使用新建一个拨码开关控制led 实验来作为设计文件，通过ise 综合、映射、布局布线后，生成FPGA位流配置文件，通过JTAG口对开发板上FPGA进行配置。

2学会最基本拨码开关和led 工作原理。

1.2 实验原理1.实验开发板的拨码开关向上拨动时处于低电平，向下处于高电平，用此来控制LED灯。

2.LED灯的的一端已经接高电平，另一端接FPGA的IO口，因此当IO输出低电平是便可点亮LED灯，否则LED为暗。

3.按键默认为高电平，按键按下时接地为低电平来检测按键的按下的复位信号。

1.3 实验步骤1.打开ISE应用程序，进入图形化界面图表 12.点击File－>New project,在弹出的对话框中设定工程和工程路径，用HDL源码,NEXT图表 23.选定器件和封装，点击NEXT.图表 34.在工程中创建源文件，选择New Source.,选中Verilog Module,输入源文件名称图表 45.可在弹出的对话框中输入信号的输入输出定义，也可暂时不定义图表 56.点击下一步，点击finish,然后自动回到creat a new source 对话框，点击下一步，再击下一步，然后点击finish 。

图表 66.点击设计的源文件，然后整个界面如图所示图表77.将鼠标置于输入输出的下方，点击工具栏中的，然后进入各子目录选择如下，这是一个快捷操作模板。

右键use in file,可在源文件中看到已经添加相应的模板，然后修改一些端口、添加内容完善整个工程设计。

图表88.写源文件的代码如下module key_led(clk, key, reset_n, led);input clk;input key;input reset_n;output led;reg led;// Usage of asynchronous resets may negatively impact FPGA resources// and timing. In general faster and smaller FPGA designs will// result from not using asynchronous resets. Please refer to// the Synthesis and Simulation Design Guide for more information.always @(posedge clk or negedge reset_n)if (!reset_n) beginled <= 1;endelse beginif(key==0)led <=0;elseled <=1;endendmodule可用design Utilities点击create schematic symbol下观看所生成的原理图来分析电路的性能。

FPGA的LVDS介绍和xilinx原语的使用方法中文说明

FPGA的LVDS介绍和xili‎n x原语的使用方法中文说明低压‎差分传送技术是基于低压差分信号(‎L ow Volt-agc Dif‎f erential signal‎i n g)的传送技术，从一个电路板‎系统内的高速信号传送到不同电路系‎统之间的快速数据传送都可以应用低‎压差分传送技术来实现，其应用正变‎得越来越重要。

低压差分信号相对于‎单端的传送具有较高的噪声抑制功能‎，其较低的电压摆幅允许差分对线具‎有较高的数据传输速率，消耗较小的‎功率以及产生更低的电磁辐射。

‎L VDS：Low Voltage‎Differential Si‎g naling，低电压差分信号。

‎LVDS传输支持速率一般在1‎55Mbps（大约为77MHZ）‎以上。

LVDS是一种低摆幅的‎差分信号技术，它使得信号能在差分‎P CB线对或平衡电缆上以几百Mb‎p s的速率传输，其低压幅和低电流‎驱动输出实现了低噪声和低功耗。

‎差分信号抗噪特性从差分信‎号传输线路上可以看出，若是理想状‎况，线路没有干扰时，在发送侧‎，可以形象理解为：IN= I‎N+ —IN-在接收侧，可以‎理解为：IN+ —IN- ‎=OUT所以：OUT = ‎I N在实际线路传输中，线路存在‎干扰，并且同时出现在差分线对上，‎在发送侧，仍然是：IN ‎=IN+ —IN-线路传输‎干扰同时存在于差分对上，假设干扰‎为q，则接收则：(IN+ +‎q) —(IN- + q) ‎=IN+ —IN- = OU‎T所以：OUT = IN‎噪声被抑止掉。

上述可以形象理‎解差分方式抑止噪声的能力。

‎F rom: 美国国家半导体的《L‎V DS用户手册》P9FPGA‎中的差分管脚为了适用‎于高速通讯的场合，现在的FPGA‎都提供了数目众多的LVDS接口。

‎如Spartan-3E系列FPG‎A提供了下列差分标准：LV‎D SBus LVDS‎m ini-LVDSRSDS‎Differential ‎H STL (1.8V, Type‎s I and III)D‎i fferential SSTL‎(2.5V and 1.8V,‎Type I)2.5V ‎L VPECL inputs‎所拥有的差分I/O管脚数目如‎下From:Spar‎t an-3E FPGA Fami‎l y:Complete Data‎Sheet p5I/O‎管脚的命名方式：Fr‎o m:Spartan-3E FP‎G A Family:Comple‎t e Data Sheet ‎p164From:S‎p artan-3E FPGA F‎a mily:Complete D‎a ta Sheet p18‎Spartan-3E系列FP‎G A器件差分I/O接口输入工作的‎特性参数:Fr‎o m:Spartan-3E FP‎G A Family:Comple‎t e Data Sheet ‎p126Spartan-3‎E系列FPGA器件差分I/O接口‎输出工作的特性参数:‎From:Spartan-3E‎FPGA Family:Com‎p lete Data Sheet‎p127Xilinx‎公司差分原语的使用（原语，其英‎文名字为Primitive，是X‎i linx针对其器件特征开发的一‎系列常用模块的名字，用户可以将其‎看成Xilinx公司为用户提供的‎库函数，类似于C+ +中的“cou‎t”等关键字，是芯片中的基本元件‎，代表FPGA中实际拥有的硬件逻‎辑单元，如LUT，D触发器，RA‎M等，相当于软件中的机器语言。

Spartan-3E开发板用户说明

附录：Spartan-3E开发板用户说明图1Spartan-3E多用途EDA实验开发平台（以下简称S3E实验平台），如图1所示，核心器件为XILINX公司的Spartan TM-3E器件XC3S500E，逻辑容量为50万门。

Spartan TM-3E借助于低成本的CPL，90nm工艺，满足了对大批量、I/O为核心的可编程逻辑解决方案的行业需求，是业界成本最低、性能最好的FPGA之一。

S3E实验平台在FPGA周围提供了丰富的资源，包括串口、PS/2接口、VGA接口、以太网接口、LED、LCD液晶显示、拨码旋钮开关和按钮、EPROM、A/D、D/A转换、电源、时钟等。

S3E的用户可以在PC机上通过USB JTAG电缆对FPGA进行配置，也可以通过SPI FLASH和NOR FLASH来配置。

1、S3E实验平台性能与特点●XILINX XC3S500E Spartan-3E FPGA：提供了最多232个I/O引脚和10000个逻辑单元。

●XILINX 4Mbit Flash配置PROM。

●XILINX XC2C64A CoolRunner系列CPLD：提供用户使用或辅助FPGA配置。

●64MByte、16位数据宽度、100MHz的DDR SDRAM接口。

●16MByte 并行INTEL公司的NOR FLASH：可存储FPGA配置信息或MicroBlaze指令序列。

●16Mbits ST半导体的SPI 串行FLASH：可存储FPGA配置信息或MicroBlaze指令序列。

●2行，每行可显示16个字符的LCD：用来显示FPGA输出信息。

●PS/2接口：用来外联键盘或鼠标，扩展输入设备●VGA接口：可显示64种颜色。

●10/100M以太网接口：提供了以太网物理层接口，便于MAC层IP的验证。

●两个标准RS232接口：可方便连接PC和其他工业设备进行数据传输。

●USB的下载接口配置接口。

●板载50MHz晶体振荡器。

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Xilinx spartan3e FPGA掉电配置及应用程序引导
Xilinx公司的spartan3e开发板上面有丰富的外围器件，就存储器来说有一个16M并行flash，一个4Mbits串行flash，还又一个64M的DDR，在嵌入式开发中，一般我们可能会在FPGA中嵌入cpu软核，让C语言程序在里面运行。

这就涉及到FPGA配置文件的引导，如果C语言程序太大，需要在DDR里面运行的话也涉及到应用程序的引导的问题。

我刚接触到xinlinx的spartan3e开发板时，只会将FPGA配置文件（.bit）直接通过JTAG口下载到芯片里。

但是但我们的应用程序和硬件配置调试通过，达到了我们的要求以后我们就想到可不可以将让程序在板子上电时就可以自动运行呢。

因为FPGA是掉电要丢失的，重新上电就必须重新配置。

我们通过查找相关资料，找到了解决烧写问题的解决办法。

首先是配置文件的烧写。

spartan3e提供了3个掉电不丢失的外部存储器，就是上面提到的并行flash，串行flash和Flash PROM。

配置文件都可以烧写到其中任何一个储存器里面。

但是，在我看来，一般的配置问件都是烧写到Flash PROM里面。

烧写方法有很多，可以用Xilinx公司的专门的烧写.mcs文件的工程烧写，也可以用iMPACT烧写。

一般用iMPACT工具烧写，烧写过程如下：
打开iMPACT，弹出新建工程时选择Cancle，然后双击窗口左边的
PROM File Formater如下图：
弹出的窗口中选择Xilinx PROM文件格式选择mcs，PROM File name为：test.mcs，选择好保存路径点击下一步如下图：
上步中点击Next，Select a PROM（bits）选择xcf->xcf04s,点击Add，然后点下一步如下图：
上图中点击Next后出现窗口中点击filinsh，弹出消息框点OK，会有一个选择bit问件的窗口，选择一个已经编写好的EDK或者ISE工程生成的.bit文件，OK后提示是否加入其他器件，选择NO，然后双击窗口右边的Generate File，生成.mcs文件如下图所示：
然后，双击Boundary Scan，在中间空白处，点击鼠标右键，选择Initialize chain，弹出的第一个窗口中选择Bypass，第二个选择刚才生成的.mcs文件，第三个也选择Bypass，然后选中中间那个模块，点击窗口左下角的program如下图：
弹出窗口中选中OK就可以了，烧写完后会看到，Program Successful 提示。

此时已经烧写成功。

开发板的引导模式跳线选择如下图所示：
此时，重启电路板就可以实现上电自动配置了。

上面只完成了FPGA配置文件的烧写，在嵌入式cpu时还需要将应用程序烧写，这样才能在上电自动配置，自动引导程序到DDR里面执行。

一般应用程序都是烧写到并行的flash中。

在EDK里面用BSB建立工程时要加入FLASH，要将应用程序分配到DDR里面，然后选择Device Configuration->Program Flash Memory，弹出窗口中，选择好软件工程所
生成的.elf文件，并选择“Auto-convert file to bootloadable SREC”，flash offset一般选择0x00000000，选中Create Flash Bootloader Aplication，然后点击OK即可如下图所示：
但如果是用EDK版本为9.2i的这样烧写一般不成功，但生成了相应的文件了的。

这时，应该选用命名行方式烧写。

在EDK中选择Project->Launch EDK Shell，在命令行方式下输入“xmd -tcl flashwriter.tcl”
回车就可以了。

此时应用程序已经烧写到flash中了，下一步就要引导应用程序。

上面的步骤昨晚了会看到software里面多了一个工程bootloader，将其初始化到bram里面，一定不要将其他的工程初始化到bram里面。

此时重新生成.bit文件，然后按照前面烧写配置文件的步骤将其烧写到flash prom 里面，重启电路板整个系统就可以自动的的完成配置，加载应用程序了。

如果串口连接好了，可以在超级终端里面看到，程序的引导过程。

至此，整个系统的固化就完成了。