时序裕量及信号完整性

1 4
2
Tco
3
Flight Time
D0 D1 D2
D0 D1 D2
Driving
Receiving
Setup
Hold
Clock Driver
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Flight Time
• Accounts for the electrical delay of interconnect (PCB etch) between the driving device and receivers Can be estimated for slow speed circuits; must be simulated (signal integrity) for high speed designs
440FX to Pentium Pro
Tflightmax = ClockPeriod Tcomax - Skew - Jitter - Crosstalk - Receiver(Setup) 4.55 ns 15.00 ns 7.25 ns 0.20 ns 0.40 ns 0.40 ns 2.20 ns Tflightmin = Receiver(Hold) - Tcomin + Skew + -0.20 ns 0.45 ns 1.25 ns 0.20 ns Crosstalk 0.40 ns
• Conditions under which this is measured
• •
– Setup / Hold requirements – PLL Jitter (if spec’d)
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Determining Flight Times: Example
• Tflightmax = 4.55 ns • Tflightmin = 0.05 ns
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What Is Signal Integrity Analysis?
• Analog analysis of digital switching behavior • Extracts routing information from PCB database • Use special analog models for device inputs / outputs – IBIS modeling standard
4
What is a “Clocked Timing Path”?
• A timing path consists of all of the logic between two clocked elements that operate off the same clock signal
Q D Qn D
A PCB Knowledge Set Online Seminar from Cadence
Signal Integrity
presented by Todd Westerhoff
Closing the loop in high speed design
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Agenda
• • • • • • • Basics of system timing analysis Basics of signal integrity analysis Flight time, buffer delay, standard loads and Tco Key process assumptions Checking and verifying model data Techniques for closing the loop Summary
• t=0
Driving
Receiving
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Measuring Interconnect Delay
• Accounts for electrical delay caused by interconnect (PCB etch) between the driving device and each receiver on the net Usually different for each driver – receiver combination
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The Signal Integrity Model
Internal Logic not modeled Internal Logic not modeled
•
SI models represent only the behavior of the device output and input buffers Internal component functions and associated timing are not modeled
•
Reference
D0 D1 D2
•
Odd Mode
D0 D1 D2
ห้องสมุดไป่ตู้
Closing the loop in high speed design
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Bus-Level Timing Budget
< Clock Period
Driver(Tcomax) Tflightmax +/- Skew +/- Jitter +/- Crosstalk Receiver(Setup)
Clock t = 0 Driver
•
t=1
D0 D1 D2
t=2
D0 D1 D2
Clock Skew changes the effective clock period depending on which devices are driving / receiving
Closing the loop in high speed design
Closing the loop in high speed design
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Determining Device Timing
Example - Pentium Pro • Timings taken from “AC (dynamic) Specifications” sections of datasheets Many datasheets available online via WWW Important parameters – Clock Data Valid
•
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Issues in Synchronous Design
Cycle 1 Cycle 2
•
Clock Jitter increases / decreases the individual clock cycle, decreasing the time left for data transfer
Q Qn
• The timing path is analyzed to ensure that setup and hold requirements are met at the input of each clocked element • The slack (delay margin) in the path can be used to derive SI flight time constraints
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Static Timing Analysis
• Systematic analysis of a synchronous ASIC, PCB or System design, that identifies:
– Logic hazards – Clocked timing paths – Timing errors
• Required inputs
– Functional description of circuit (netlist) – Component-level timing data – Circuit operating (clock) speeds
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Crosstalk - Impact on Bus Timing
D0 D1 D2
Even Mode
D0 D1 D2
•
Crosstalk between adjacent bus bits affects edge speed (and therefore flight time) Denser routing makes better use of board space, but at the expense of larger variations in flight time Pre-layout crosstalk analysis helps the designer make the best tradeoff between routing density and signal integrity
Closing the loop in high speed design
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Improving your process for high-speed PCB design
System Timing
“Closing the loop between timing analysis and signal integrity”