数字地和模拟地应怎样处理

数字地和模拟地应怎样处理
The name "DGND" on an IC tells us that this pin connects to the digital ground of the IC.
一个IC中的“DGND”表示这个脚是连接到该IC内部的数字地。

This does not imply that this pin must be connected to the digital ground of the syste m.
但这并不意味着该脚必须接到系统的数字地。

It is true that this arrangement may inject a small amount of digital noise onto the an alog
ground plane.
这样的安排，的确会将少量的数字噪声引入到模拟地平面中。

These currents should be quite small, and can be minimized by ensuring
that the converter output does not drive a large fanout (they normally can't, by desig n).
然而，IC的数字地电流应该是非常小的。

并且，通过确保（模数）转换器的（数字）输出不驱动重负载
可以使IC的数字地电流达到最小。

Minimizing the fanout on the converter's digital port will also keep the converter logi c
transitions relatively free from ringing and minimize digital switching currents, and thereby reducing any potential coupling into the analog port of the converter.
减少转换器的数字端口负载（注：原文为扇出，就是同时驱动多少个门的意思，我翻译为负载，
负载包括动态和静态的）还可以减少翻转电流和避免出现振铃，这就减少了任何潜在的耦合
混入到转换起的模拟端口中。

The logic supply pin (VD) can be further isolated from the analog supply by the inserti on
of a small lossy ferrite bead as shown in Figure 9.26.
如图9.26所示，通过插入一个有损耗的小铁氧体磁珠，数字电源（VD）可以进一步与模拟电源隔离。

The internal transient digital currents of the converter will flow in the small loop from VD through the decoupling capacitor and to DGND (this path is shown with a heavy li ne on
the diagram).
转换器内部的数字毛刺电流将从VD通过退耦电容到DGND这个小环路流过（该路径在图中用粗线标出）。

The transient digital currents will therefore not appear on the external analog ground plane,
but are confined to the loop.
因此，数字毛刺电流不会在外面的模拟地平面中出现，仅被限制在该小环内。

The VD pin decoupling capacitor should be mounted as close to the converter as possible to minimize parasitic inductance.
VD引脚的退耦电容应该尽可能的靠近转换器放置，以使寄生电感最小。

These decoupling capacitors should be low inductance ceramic types,
typically between 0.01 μF and 0.1 μF.
这些退耦电容应该是低感抗的陶瓷电容，容量通常在0.01uF到0.1uF之间。

Inside an IC that has both analog and digital circuits, such as an ADC or a DAC, the grounds are usually kept separate to avoid coupling digital signals into the analog circuits.
在既有模拟电路又有数字电路的IC内部（例如ADC或者DAC），数字地和模拟地通常是分开的以避免
数字信号耦合到模拟电路中。

Figure 9.26 shows a simple model of a converter.
图9.26给出了一个转换器的简易模型。

There is nothing the IC designer can do about the wirebond inductance and resistanc e
associated with connecting the bond pads on the chip to the package pins except to realize it's there.
IC设计人员对于连接芯片和封装引脚之间的绑定线的电感和电阻，除了知道它的存在之外，无计可施。

The rapidly changing digital currents produce a voltage at point B which will inevitabl y
couple into point A of the analog circuits through the stray capacitance, CSTRAY.
迅速变化的数字电流在B点产生一个电压，它将不可避免的通过寄生电容C STRAY 耦合到模拟电路的A点。

In addition, there is approximately 0.2-pF unavoidable stray capacitance between eve ry
pin of the IC package! It's the IC designer's job to make the chip work in spite of this. 另外，在IC封装的引脚之间，不可避免的存在着约0.2pF的寄生电容。

IC设计者有义务让芯片在这种条件下
也能很好的工作。

However, in order to prevent further coupling, the AGND and DGND pins should be j oined
together externally to the analog ground plane with minimum lead lengths.
然而，为了避免更多的耦合，AGND和DGND引脚应该在外部连在一起并通过最短的引线连接到模拟地平面。

Any extra impedance in the DGND connection will cause more digital noise to be dev eloped
at point B; it will, in turn, couple more digital noise into the analog circuit through the stray capacitance.
任何额外的DGND连接阻抗将会导致B点出现更多的数字噪声；通过寄生电容，这将会有更多的数字噪声
耦合到模拟电路中。

Note that connecting DGND to the digital ground plane applies VNOISE across the AGND and DGND pins and invites disaster!
注意，连接DGND到数字地平面将会把VNOISE引入到AGND和DGND并惹来天灾！。