a circular hough transform hardware for industrial circle detction applications

A Circular Hough Transform Hardware for Industrial CircleDetection ApplicationsJau Ruen Jen, Mon Chau Shie, and Charlie ChenDept. of Electronic Engineering,National Taiwan University of Science and Technology School of Electrical and Electronic Engineering,No.43, Sec.4, Keelung Rd., Taipei, Taiwan, R.O.C.AbstractThe Hough Transform (Hough, 1962) has been used to characterize analytic features. It was first applied to the recognition of straight lines, and later extended to circles, ellipses and arbitrary shaped objects. Its main disadvantage is the computational and storage requirements increase as a power of the dimensionality of the curve.It is not difficult to implement Circular Hough Transform (CHT) algorithm on modern personal computer. However, we intend to use FPGA or ASIC to perform CHT in this article. Modern FPGAs are capable of performing high speed operation and have large amount of embedded memory. The whole CHT circuitry with accumulator array excluded can be fitted into Altera® Stratix® 1S25 chip which has more than 1Mb RAM embedded.1IntroductionDetection of round objects is important in many areas of image analysis and is important in industrial application such automatic inspection and assembly. For many components are round shaped. Richard. O. Duda and Peter. E. Hart (1965) extent the Hough straight line detection to circle-finding concept. In their algorithm, the array is indexed by three parameters specifying the location and size of the circle: the circle center (x0,y0) and the circles radius r.Though FPGAs have large size of embedded memory , the embedded memory of FPGAs are not enough for our CHT application. In our design, the embedded memory served as image buffer only and the accumulator memories for storing parameter are off-chip components which can be any ordinary SRAM chip.2Hough Transform (HT) and Circulet Hough Transform (CHT)A straight line in 2 dimensional plane (X-Y plane) can be expressed as y=ax+b. All points satisfying y i=ax i+b determine a straight line. In the contrary, we may also claim that these points satisfy b=-ax i+y i equation. It means all collinear points on the X-Y plane correspond a point on the A-B (parameter) plan. Three dual property of the point-to-straight line transformation can be established :Property 1. A point in the X-Y plane corresponds a straight line in the parameter plane.Property 2. Three points in the X-Y plane correspond three straight lines in the parameter plane.Property 3. Three noncollinear points in the X-Y plane correspond three straight line intersecting at one point in the parameter plane.There is a serious drawback using this method to represent straight lines when lines are perpendicular to X- axis in the X-Y plane. We are not able to describe the lines using equation b=-ax i+y i .R. O. Duda and P. E. Hart used normal parameterization to describe the straight line in parameter space alternatively. The equation of a line corresponding to the geometry shown in Figure 2-1 isρ=xcosθ+ysinθ.A dual property of the point-to-curve transformation can also be established. Suppose we have a set {(ρ1, θ1), . . . , (ρn, θn)} of points in the ρ-θ plane, all lying on the curveρ=xcosθ+ysinθ.It is easy to show that all these points correspond to lines in the x-y plane passing through the point (x0,y0). We have the following four properties:(a)Property 1. A point in the X-Y plane corresponds toa sinusoidal curve in the parameter plane.(b)Property 2. A point in the parameter planecorresponds to a straight line in the picture plane.Y0-7803-9514-X/06/$20.00 ©2006 IEEE ICIEA 2006(c) Property 3. Points lying on the same straight line inthe X-Y plane correspond to curves through a common point in the parameter plane.(d) Property 4. Points lying on the same curve in theparameter plane correspond to lines through the same point in the X-Y plane.To examine all points in the X-Y plane and add one to the corresponding array in ρ-θ accumulator array, we will find a coordinate which has maximum accumulated value. The maximum value k found at coordinate (ρi , θi ) means k curves intersecting at point (ρi , θi ) in the parameter plane, i.e., there are k colinear points in the X-Y plane.Normally, a circle is represented by (x-x 0)2+(y-y 0)2=r 2, where x 0 and y 0 are the center coordinates, and r is the radius. As we mentioned, the three parameter form a 3 dimensional accumulator. We need a 5 dimensional accumulator array if we want to detect a ellipse. Obviously, it’s a bad idea to use FPGA embedded memory as accumulator to implement CHT, we need far more amount of memory than embedded memory.3Proposed Method3.1Gray Level ImageColor images are everywhere in the world. However, they are useless in straight line or circle detection. These colorful image should be transferred to gray level images for further operation. We use 256 gray levels image and adopt the RGB space to YIQ space conversion equation. Hence, we get Y =0.25R+0.57G+0.11B, where R, G, B is the corresponding color component value, and Y is the conversion result. We may simply average the three component values to generate the gray level image. Figure 3-1 shows a 24bit colored picture, and Figure 3-2 shows the corresponding 256 gray levels image.3.2Edge detectionAn edge detection is used to extract boundary from gray level images. It is a high pass filtering often used to enhance images. There are two ways to enhance images. One is done in spatial domain, and the other is done in frequency domain. In spatial domain filtering , we use a sliding mask for data processing. A new pixel value is calculated according the mask and corresponding pixel value. The equation can be expressed as:Where w is the mask , and f (x ,y ) is the image we want to perform operation.We often use Sobel edge detection to extract image boundary. It use discrete calculation to get gradient information. For a function f, the first order gradient over point (x ,y ) is defined asThe magnitude and direction areFor complexity issue, we often use the following equationy x G G f +≈∇to approximate the magnitude. Figure 3-3 shows the Horizontal Sobel mask. Figure 3-4 shows the verticalSobel mask.3.3 Laplace FilteringIn generally, the Sobel edge detection will generate images with good quality. For some gray level images, the extracted boundary appears to be filled with bright pixels as shown in Figure 3-5, and that consume a lot of computation. To further reduce the pixels we have to process, we use Laplace filtering again.The Laplace filtering is a second order gradient operation, which is defined asin the continuous domain. The discrete domain second order gradient is defined as The discrete two dimensional second order gradient is defined asHence the Laplace mask should be the one shown in Figure 3-6.Figure 3-7 shows the result of Laplace filtering. As we see, the image has fewer feature points than Figure 3-5.3.4Detecting center and radius of circle∂∂∂∂= =∇y f x f G G f y x []()yx -yx G G G G f)mag(12122tan =+=∇θ2222y fx ff ∂∂+∂∂=∇)()()(12122x-f x f -x f x f++=∂∂Figure 3-3Figure 3-4Figure 3-1Figure 3-2()()2020-y y -x x r i i +=We have mentioned, In Section 2, three noncollinear points determine a circle. And two of the HTmodification used this method to get center location. We adopt this method for it is easy to implement. A major difference is that we calculate the radiusin the same time, where (x i , y i ) is any of the three edge pixel considered to be on the circle.It is obvious, a digital circle has odd or even diameter. The resolution of radius hence will be 0.5 pixel. If we omit circles with radius smaller than 4 and set the resolution of radius to 1, we only have to calculate integer radius lager or equal to 4. This help reduce the computa tionrequired.Thecalculate d radius and center location are storedforaccumul ation tofind out local maximum. The maximum indicates a circle we detect. A radius histogram is shown in Figure3-8.4Hardware ArchitectureFor efficient coding, the image size is set to 256pixels * 256pixels, which means 16bit address are enough for X-axis and Y-axis arithmetic .We decide not to usetrigonometric function to implement fast and efficient CHT. Not to use trigonometric function means no tangent (gradient information) and no floating point arithmetic. We only need to compute the integer radius and center location and vote from 1D accumulator and 2D accumulator which are located outside the FPGA. An Altera ® Stratix ® 1S25 has more than 1 million bitembedded memory which can be used as our RAMbuffer. Three 256*256*8 bit embedded memory (RAM1, RAM2 and RAM3) are used for edge detection and Laplace filtering. They are arranged as synchronous two port memory having write and read signal independently. Synchronous memory in FPGA has better performance in writing than asynchronous memory. The block diagram of the system is shown in Figure 4-1The following paragraph describe the architecture more detailed4.1 UART InterfaceA UART interface is used to receive gray level image from host and send the drawn circle image to host. The interface supports 5,6,7 and 8 bit format. One-stop or two-stop bit can be adjusted. Even parity or odd parity can be adjusted too. All the features help the interface works fine with any other UART interface.An internal read or write signal is generate if the received signal sequence comply with predefined protocol. To start the read cycle of RAM1, the host must send the high byte address of RAM1 first, the low byte address secondly and a byte of data not equal to 0xff. A internal read cycle will then be initiated automatically and send out the captured data of RAM1 a few clocks later. To write RAM1, the host has to send the high byte address of RAM1 first, the low byte address secondly, command data 0xFF thirdly and the data to be written finally. Once the address 0xFFFF of RAM1 has been written to, the system will start the Sobel edge detection automatically.4.2 Sobel ModuleThe Sobel module performance Sobel edge detection. It read gray level image data from RAM1 and perform the horizontal convolution and vertical convolution. The result of horizontal convolution is stored at RAM2 , and vertical convolution result is stored at RAM3. Figure 4-3 shows the relationship among Sobel module and others. During these convolution, all the results greater than 255 are fixed at 255, and all the results smaller than 0 are fixed at 0. We do this because (1) we use 8bit embedded memory and (2) this will reduce the computation required in the future stage. Further, we decide not to perform the Sobel edge detection on image boundary , i.e., only 254x254 mask operation is enough in vertical and horizontal directions. After the two convolutions are finished, the magnitude of the gradient can be calculated and stored into RAM1. A threshold is again set to examine the magnitude which make the Sobel edge detection generate binary image.A roughly estimation of processing time of this stage is T R (13WH-12W-12H+2) + T W (3WH+2WH+2H-2), where W is the Width of image, H is the height of image, T R is read cycle time of RAM buffer, and T W isIn/OutFigure 3-5 Figure 3-7Figure 5-1Figure 5-2write cycle time of RAM. Both W and H are 256 in the paper.4.3 Laplace FilteringAs we mentioned, some image have better result if we performance the Laplace filtering after Sobel edge detection, and some don’t. We can set bit3 of control register2 to bypass the Laplace filtering.Similarly, only 254*254 convolution is performed to reduce to computation. The result of Laplace filtering is stored at RAM2.An estimated processing time of this stage is T W (WH+W+H-3)+T R (5WH+5W-5H+5).4.4 Compact ModuleThe extracted edge pixels are randomly located in the image buffer RAM1 or RAM2. Like the hard drive disk, we often perform a defragment when the performance of disk reading or writing is getting worse. In this project, we need to rearrange the edge pixels and place them in the RAM buffer in sequence to reduce searching time in the center and radius calculation stage.According to the simulation either RTL level or gate level we have done, we found the effect of compacting edge pixel locations remarkable. No more time is wasted during center and radius calculation stage. This will greatly reduce total detection time. If it is a valid edge pixel, the address of the data will be written into RAM3 and RAM2(RAM1) where RAM3 store the high byte address and RAM2(RAM1). The processing time of this stage is (256*256*T R +N*T W ) , where N is the number of edge pixels.4.5 Circle ModuleThe Circle module calculate radius and center location according to the address stored at RAM3 and RAM2(RAM1). To perform Cramer’s equation where we need some special arithmetic function such as square root and division. More than 20 adder are used, and their input vary from 16bits to 28bits. There are six 17bit by 18bit multipliers, twelve 17bit by 9bit multipliers and fourteen 8bit by 8bit multipliers. Two 28bit by 20bit division modules are used. One 17bit square root function is used.The total processing time of this stage is about T W *WH+ (T C +T W +T R )N 3, where T C is the time required to perform Cramer’s equation and T W *WH is the time we used to clear RAM buffer before writing address into.4.6 Draw ModuleThe Draw module draw circle according to the detected radius and center location. Only the circle with localmaximum radius and center histogram is drawn for demonstration purpose.To calculate the distance between every points of image and candidate circle center, we know if the distance of these two points equal to the detected radius. Mark those points in RAM1 have correct distance will show the circle we detected. The content of RAM1 can be read through UART interface. The time to draw a circle is (T R +T D )WH + 2πR T W . where R is the detected radius and T D is the time to calculate distance of two points.5Fitting and simulation resultThe logic cells used in our design are 3056, which are 11% of all logic cells we can us. 1253 registers are used, which are 4% of all registers we can use.128 M4Ks memory and 2 M-RAMs are used as RAM buffer. The three RAM buffers consume 1,572,864bit and some logic are implemented in embedded memory logic. Hence, the total amount of memory used are 1,769,472bit which are 90% of all embedded memory. The multiplication, addition, division are implemented in DSP block. 42 blocks are used.Some simulation result are presented here to show the functionality of circuit.Figure 5-1 shows the host writing gray level image into RAM buffer1.Figure 5-2 shows the waveforms of horizontal Sobel convolution and store the result into RAM buffer2. Figure 5-3 shows the waveforms of vertical Sobel convolution and store the result into RAM buffer3.Figure 5-3Figure 5-4Figure 5-5 Figure 5-6 Figure 5-7Figure 5-4 shows the waveforms of mearging vertical and horizontal Sobel convolution andstore the result into RAM buffer1Figure 5-5 shows the waveforms of Laplace filtering on RAM bufffer1.Figure 5-6 shows the waveforms of Compact addressed of edge pixels. Figure 5-7 shows the waveforms of centre and radius calculation in CIRCLE module.Figure 5-8 shows the detected radius is15 and detected center location is (0x76, 0x7d).6ConclusionThis paper propose a flexible hardware architecture for CHT using 1D accumulator and2D accumulator outside the FPGA. In the beginning, the gray level image is downloaded into FPGA to extract edge pixels. User may skip Laplace filtering if the image is worse than that after Sobel filtering. The location of edge pixels are then compacted to reduce the searching time. Cramer rule is applied to calculated the candidate radius and centers . Voting the maximum possibility, we get the detected circle.The time for center and radius calculation is the key factor in our design. In the Verilog simulation, if the clock speed is 50MHz and the Cramer equation calculator consume 13 cycles to get the radius and center, the total time detecting a circle with radius 21(decimal value) is 4.3s, however it takes 46 seconds in C language simulation on an AMD Athlon 2000+ system. Currently, a non-pipelined Cramer equation calculator is used. The future works is to design a pipeline one to speedup the performance.Figure 5-8To download or upload image from RAM1 through UART interface take much longer than the time required to detect a circle. We may use the USB interface for faster transmission in the future, too. Modularized design allow users to modify or add new circuitry to get better performance in recognition. References[1] N. Guil and E.L.Zapata “Lower Order Circle and Ellipse Hough Transform,'' Pattern Recognition, vol. 30, no. 10, October 1997, pp. 1729-1744.[2] X. Cao and F. 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