(原创)eCos驱动分析 之 ISR是如何与硬件中断联系起来的 ---转载文章

(原创)eCos驱动分析之ISR是如何与硬件中断联系起来的---转载文章要想知道ecos的中断ISR是怎么与硬件中断向量联系起来的，是怎么被调用的?那就要看下面这两个关键的函数:cyg_drv_interrupt_create()cyg_drv_interrupt_attach()这两个函数都声明在cyg/kernel/kapi.h中,其形式如下:void cyg_interrupt_create( cyg_vector_t vector, /* Vector to attach to */ cyg_priority_t priority, /* Queue priority */ cyg_addrword_t data, /* Data pointer*/ cyg_ISR_t *isr, /* Interrupt Service Routine */ cyg_DSR_t *dsr, /* Deferred Service Routine */ cyg_handle_t *handle, /* returned handle */ cyg_interrupt *intr /* put interrupt here */) __THROW;void cyg_interrupt_attach( cyg_handle_t interrupt )__THROW;(注: __THROW是在C++中用的,是用来抛出异常的,详见我的博文/blog/static/888807432011611193510/ 这里可以视而不见.)其中文意义对照如下:cyg_interrupt_create( 中断号, 中断优先级, 传递的中断参数, ISR函数,DSR函数, 被返回的中断句柄, 存放与此中断相关的内核数据的变量空间);cyg_interrupt_attach(中断句柄);这样实际上去研究一下cyg_interrupt_create函数的定义内容,应该就能搞明白我们的问题了!由于其函数声明在kapi.h中,很自然的就想到其定义应在kapi.c文件中,找到....\ecos\ecos-current\packages\kernel\current\src\common\kapi.cxx文件,找到这两个函数的定义如下:/*---------------------------------------------------------------------------*//* Interrupt handling*/externC void cyg_interrupt_create( cyg_vector_t vector, /* Vector to attach to */ cyg_priority_t priority, /* Queue priority*/ cyg_addrword_t data, /* Data pointer */ cyg_ISR_t*isr, /* Interrupt Service Routine */ cyg_DSR_t *dsr, /* Deferred Service Routine */ cyg_handle_t *handle,/* returned handle */ cyg_interrupt *intr /* put interrupt here */) __THROW{ CYG_ASSERT_SIZES( cyg_interrupt,Cyg_Interrupt );Cyg_Interrupt *t = new((void *)intr) Cyg_Interrupt( (cyg_vector)vector, (cyg_priority)priority, (CYG_ADDRWORD)data, (cyg_ISR *)isr,(cyg_DSR *)dsr ); t=t;CYG_CHECK_DATA_PTR( handle, "Bad handle pointer" ); *handle = (cyg_handle_t)intr;}voidcyg_interrupt_attach( cyg_handle_t interrupt )__THROW{ ((Cyg_Interrupt *)interrupt)->attach();}函数内容比想象中的简单,所有的操作又都传给了Cyg_Interrupt这个类来完成,那就来对Cyg_Interrupt探个究竟吧:(注意Cyg_Interrupt是个C++类, 可不要找成了struct cyg_interrupt,注意哟,cyg_interrupt_create函数的最后一个参数就是这个cyg_interrupt struct类型的,在cyg/kernel/kapidata.h中有个struct cyg_interrupt定义,虽然名字和内容都很相似,但实际上不是.)真正的class Cyg_Interrupt定义在cyg/kernel/intr.hxx中,这个头文件没干别的,就是声明这个class了,可见这是一个很大的class,如下:// -------------------------------------------------------------------------// Interrupt class. This both represents each interrupt and provides a static// interface for controlling the interrupt hardware.class Cyg_Interrupt{friend class Cyg_Scheduler; friend voidinterrupt_end( cyg_uint32,Cyg_Interrupt *,HAL_SavedRegisters *); friend voidcyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );friend void cyg_interrupt_call_pending_DSRs( void );cyg_vector vector; // Interrupt vector cyg_priority priority; // Queuing priority cyg_ISR *isr; // Pointer to ISR cyg_DSR *dsr; // Pointer to DSRCYG_ADDRWORD data; // Data pointer // DSR handling interface called by the scheduler// Check for pending DSRs static cyg_bool DSRs_pending();// Call anypending DSRs static void call_pending_DSRs(); static void call_pending_DSRs_inner();// DSR handling interface called by the scheduler and HAL // interrupt arbiters.void post_dsr(); // Post the DSR for this interrupt // Data structures for handling DSR calls. We implement two DSR // handling mechanisms, a list based one and a table based // one. The list based mechanism is safe with respect to temporary // overloads and will not run out of resource. However it requires // extra data per interrupt object, and interrupts must be turned // off briefly when delivering the DSR. The table based mechanism // does not need unnecessary interrupt switching, but may be prone // to overflow on overload. However, since a correctly programmed // real time application should not experience such a condition, // the table based mechanism is more efficient for real use. The // list based mechainsm is enabled by default since it is safer to// use during development.#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE static Cyg_Interrupt *dsr_table[CYGNUM_KERNEL_CPU_MAX][CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE] CYGBLD_ANNOTATE_VARIABLE_INTR;static cyg_ucount32dsr_table_head[CYGNUM_KERNEL_CPU_MAX]CYGBLD_ANNOTATE_VARIABLE_INTR;static volatile cyg_ucount32dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]CYGBLD_ANNOTATE_VARIABLE_INTR;#endif#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST // Number of DSR posts made volatilecyg_ucount32 dsr_countCYGBLD_ANNOTATE_VARIABLE_INTR;// next DSR in list Cyg_Interrupt* volatile next_dsr CYGBLD_ANNOTATE_VARIABLE_INTR;// static list of pending DSRs static Cyg_Interrupt* volatile dsr_list[CYGNUM_KERNEL_CPU_MAX]CYGBLD_ANNOTATE_VARIABLE_INTR;#endif#ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN// The default mechanism for handling interrupts is to attach just // one Interrupt object to each vector. In some cases, and on some // hardware, this is not possible, and each vector must carry a chain // ofinterrupts.Cyg_Interrupt *next; // Next Interrupt in list// Chaining ISR inserted in HAL vector staticcyg_uint32 chain_isr(cyg_vector vector, CYG_ADDRWORD data);// Table of interrupt chains static Cyg_Interrupt*chain_list[CYGNUM_HAL_ISR_TABLE_SIZE];#endif// Interrupt disable data. Interrupt disable can be nested. On // each CPU this is controlled bydisable_counter[cpu]. When the // counter is first incremented from zero to one, the //interrupt_disable_spinlock is claimed using spin_intsave(), the // original interrupt enable state being saved in// interrupt_disable_state[cpu]. When the counter is decremented // back to zero the spinlock is cleared using clear_intsave().// The spinlock is necessary in SMP systems since a thread // accessing data shared with an ISR may be scheduled on a // different CPU to the one that handles the interrupt. So, merely // blocking local interrupts would be ineffective. SMP aware // device drivers shouldeither use their own spinlocks to protect // data, or use the API supported by this class, via //cyg_drv_isr_lock()/_unlock(). Note that it now becomes// essential that ISRs do this if they are to be SMP-compatible.// In a single CPU system, this mechanism reduces to just // disabling/enabling interrupts.// Disable level counter. This counts the number of times // interrupts have been disabled. static volatile cyg_int32 disable_counter[CYGNUM_KERNEL_CPU_MAX] CYGBLD_ANNOTATE_VARIABLE_INTR;// Interrupt disable spinlock. This is claimed by any CPU that has // disabled interrupts via the Cyg_Interrupt API. static Cyg_SpinLock interrupt_disable_spinlockCYGBLD_ANNOTATE_VARIABLE_INTR;// Saved interrupt state. When each CPU first disables interrupts // the original state of the interrupts are saved here to be // restored later. staticCYG_INTERRUPT_STATEinterrupt_disable_state[CYGNUM_KERNEL_CPU_MAX] CYGBLD_ANNOTATE_VARIABLE_INTR;public:Cyg_Interrupt // Initialize interrupt ( cyg_vector vector, // Vector to attach to cyg_priority priority,// Queue priority CYG_ADDRWORD data,// Data pointer cyg_ISR *isr,// Interrupt Service Routine cyg_DSR *dsr // Deferred Service Routine );~Cyg_Interrupt(); // ISR return values enum { HANDLED = 1, // Interrupt was handled CALL_DSR = 2// Schedule DSR };// Interrupt management void attach();// Attach to vector void detach();// Detach from vector // Static Interrupt management functions// Get the current service routine static voidget_vsr(cyg_vector vector, cyg_VSR **vsr);// Install a vector service routine static voidset_vsr( cyg_vector vector, // hardware vector to replace cyg_VSR *vsr,// my new service routine cyg_VSR **old = NULL// pointer to old vsr, if required ); // Staticinterrupt masking functions// Disable interrupts at the CPU static voiddisable_interrupts();// Re-enable CPU interrupts static voidenable_interrupts();// Are interrupts enabled at the CPU? static inline cyg_bool interrupts_enabled() { return (0 == disable_counter[CYG_KERNEL_CPU_THIS()]); } // Get the vector for the following calls inline cyg_vectorget_vector() { return vector; } // Static PIC control functions // Mask a specific interrupt in a PIC static void mask_interrupt(cyg_vector vector); // The same but not interrupt safe static voidmask_interrupt_intunsafe(cyg_vector vector);// Clear PIC mask static voidunmask_interrupt(cyg_vector vector); // The same but not interrupt safe static voidunmask_interrupt_intunsafe(cyg_vector vector);// Acknowledge interrupt at PIC static void acknowledge_interrupt(cyg_vector vector);// Change interrupt detection at PIC static void configure_interrupt( cyg_vector vector,// vector to control cyg_bool level,// level or edge triggered cyg_bool up// hi/lo level, rising/falling edge );#ifdef CYGPKG_KERNEL_SMP_SUPPORT// SMP support for associating an interrupt with a specific CPU. static void set_cpu( cyg_vector,HAL_SMP_CPU_TYPE cpu ); static HAL_SMP_CPU_TYPE get_cpu( cyg_vector );#endif };这只是声明了这个class，这个class的构造/析构函数和成员函数的实现，还要找cyg/kernel/intr.hxx头文件相对应的C文件，在这里....\packages\kernel\current\src\intr\intr.cxx 找到了intr.cxx文件，因为cyg_interrupt_create函数实际上调用了classCyg_Interrupt的构造函数，我们就来看看这个构造函数: Cyg_Interrupt::Cyg_Interrupt( cyg_vector vec,// Vector to attach to cyg_priority pri,// Queue priority CYG_ADDRWORD d,// Data pointer cyg_ISR *ir,// Interrupt Service Routine cyg_DSR *dr// Deferred ServiceRoutine ){ CYG_REPORT_FUNCTION();CYG_REPORT_FUNCARG5("vector=%d, priority=%d,data=%08x, isr=%08x, ""dsr=%08x", vec, pri, d, ir, dr); vector = vec; priority = pri; isr = ir; dsr = dr; data = d;#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LISTdsr_count = 0; next_dsr = NULL;#endif#ifdef CYGIMP_KERNEL_INTERRUPTS_CHAINnext = NULL;#endifCYG_REPORT_RETURN();};也就是分配了一下成员变量，把cyg_interrupt_create函数传进来的中断号、ISR、DSR等分配给类的成员变量，好像也没什么特别的。