EDA数字秒表课程设计

EDA课程设计实验报告数字秒表班级：电1104姓名：***学号：********设计数字秒表一、实验要求：1.要求设置启/停开关。

当按下启/停开关，将启动秒表开始计时，当再按一下启/停开关时，将终止计时操作。

2.数字秒表的计时范围是0秒~59分59.99……3.要求计时精度为0.01s。

4.复位开关可以在任何情况下使用，即便在计时过程中，只要按一下复位开关，计时器就清零，并做好下次计时的准备。

二、实验分模块源程序及仿真结果：(一)时积分频模块的VHDL源程序（CB10.VHD）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CB10 ISPORT(CLK:IN STD_LOGIC;CO:OUT STD_LOGIC);END CB10;ARCHITECTURE ART OF CB10 ISSIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF RISING_EDGE(CLK) THENIF COUNT="1001"THENCOUNT<="0000";CO<='1';ELSECOUNT<=COUNT+1;CO<='0';END IF;END IF;END PROCESS;END ART;CB10仿真波形（二）控制模块的VHDL源程序（CTRL.VHD）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CTRL ISPORT(CLR,CLK,SP:IN STD_LOGIC;EN:OUT STD_LOGIC);END;ARCHITECTURE BEHA VE OF CTRL ISTYPE STATES IS ARRAY(1 DOWNTO 0) OF STD_LOGIC; CONSTANT S0: STATES:="00";CONSTANT S1: STATES:="01";CONSTANT S2: STATES:="11";CONSTANT S3: STATES:="10";SIGNAL CURRENT_STATE,NEXT_STATE:STATES; BEGINCOM:PROCESS(SP,CURRENT_STATE,NEXT_STATE) BEGINCASE CURRENT_STATE ISWHEN S0=>EN<='0';IF SP='1' THENNEXT_STATE<=S1;ELSENEXT_STATE<=S0;END IF;WHEN S1=>EN<='1';IF SP='1' THENNEXT_STATE<=S1;ELSENEXT_STATE<=S2;END IF;WHEN S2=>EN<='1';IF SP='1' THENNEXT_STATE<=S3;ELSENEXT_STATE<=S2;END IF;WHEN S3=>EN<='0';IF SP='1' THENNEXT_STATE<=S3;ELSENEXT_STATE<=S0;END IF;END CASE;END PROCESS;SYNCH:PROCESS(CLR,CLK,SP)BEGINIF CLR='1' THENCURRENT_STATE<=S0;ELSIF CLK'EVENT AND CLK='1' THENCURRENT_STATE<=NEXT_STATE;END IF;END PROCESS;END;CTRL仿真波形（三）计时模块的VHDL源程序（1）十进制计数器的VHDL 源程序(CDU10.VDH)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU10 ISPORT(CLK:IN STD_LOGIC;CLR:IN STD_LOGIC;EN:IN STD_LOGIC;CN:OUT STD_LOGIC;COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CDU10;ARCHITECTURE ART OF CDU10 ISSIGNAL SCOUNT10:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINCOUNT10<=SCOUNT10;PROCESS(CLK,CLR,EN)BEGINIF(CLR='1') THENSCOUNT10<="0000";CN<='0';ELSIF RISING_EDGE(CLK) THENIF(EN='1') THENIF SCOUNT10="1001" THENCN<='1';SCOUNT10<="0000";ELSECN<='0';SCOUNT10<=SCOUNT10+1;END IF;END IF;END IF;END PROCESS;END ART;CDU10仿真波形（2）六进制计数器的VHDL 源程序(CDU6.VDH)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU6 ISPORT(CLK,CLR,EN:IN STD_LOGIC;CN:OUT STD_LOGIC;COUNT6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CDU6;ARCHITECTURE ART OF CDU6 ISSIGNAL SCOUNT6:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINCOUNT6<=SCOUNT6;PROCESS(CLR,EN,CLK)BEGINIF (CLR='1') THENSCOUNT6<="0000";CN<='0';ELSIF RISING_EDGE(CLK) THENIF (EN='1') THENIF SCOUNT6="0101" THENSCOUNT6<="0000";CN<='1';ELSESCOUNT6<=SCOUNT6+1;CN<='0';END IF;END IF;END IF;END PROCESS;END ART;CDU6仿真波形（3）计时器的VHDL源程序(COUNT.VHD)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT ISPORT(CLK,CLR,EN:IN STD_LOGIC;S_1MS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);S_10MS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);S_100MS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);S_1S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);S_10S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);M_1MIN:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);M_10MIN:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);HOUR:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COUNT;ARCHITECTURE ART OF COUNT ISCOMPONENT CDU10PORT(CLK,CLR,EN:IN STD_LOGIC;CN:OUT STD_LOGIC;COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT CDU10;COMPONENT CDU6PORT(CLK,CLR,EN:IN STD_LOGIC;CN:OUT STD_LOGIC;COUNT6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT CDU6;SIGNAL A,B,C,D,E,F,G,H:STD_LOGIC;BEGINUL:CDU10 PORT MAP(CLK,CLR,EN,A,S_1MS);U2:CDU10 PORT MAP(A,CLR,EN,B,S_10MS);U3:CDU10 PORT MAP(B,CLR,EN,C,S_100MS);U4:CDU6 PORT MAP(C,CLR,EN,D,S_1S);U5:CDU10 PORT MAP(D,CLR,EN,E,S_10S);U6:CDU6 PORT MAP(E,CLR,EN,F,M_1MIN);U7:CDU10 PORT MAP(F,CLR,EN,G,M_10MIN);U8:CDU6 PORT MAP(G,CLR,EN,H,HOUR);END ART;COUNT仿真波形（四）显示模块的VHDL源程序数据选择器的VHDL源程序（MULX.VHD）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MULX ISPORT(CLK1,CLR,EN:IN STD_LOGIC;S_1MS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S_10MS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S_100MS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S_1S:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S_10S:IN STD_LOGIC_VECTOR(3 DOWNTO 0);M_1MIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);M_10MIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);HOUR:IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUTBCD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END MULX;ARCHITECTURE ART OF MULX ISSIGNAL COUNT: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLR,CLK1)BEGINIF CLR='1' THENCOUNT<="1111";ELSIF RISING_EDGE(CLK1)THENIF EN='1' THENIF COUNT="1001" THENCOUNT<="0000";ELSECOUNT<=COUNT+'1';END IF;END IF;END IF;END PROCESS;PROCESS(CLK1)BEGINIF CLK1'EVENT AND CLK1='1' THENCASE COUNT ISWHEN"0000"=>OUTBCD<=S_1MS; SEG<="00000001";WHEN"0001"=>OUTBCD<=S_10MS; SEG<="00000010";WHEN"0010"=>OUTBCD<=S_100MS; SEG<="00000100";WHEN"0011"=>OUTBCD<=S_1S; SEG<="00001000";WHEN"0100"=>OUTBCD<=S_10S; SEG<="00010000";WHEN"0101"=>OUTBCD<=M_1MIN; SEG<="00100000";WHEN"0110"=>OUTBCD<=M_10MIN; SEG<="01000000";WHEN"0111"=>OUTBCD<=HOUR; SEG<="10000000";WHEN"1000"=>OUTBCD<=S_1MS; SEG<="00000001";WHEN"1001"=>OUTBCD<=S_10MS; SEG<="00000010";WHEN OTHERS=>OUTBCD<="0000"; SEG<="00000000";END CASE;END IF;END PROCESS;END ART;MULX仿真波形（五）BCD七段译码驱动器的VHDL源程序（BCD7.VHD）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY BCD7 ISPORT(BCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0);LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END BCD7;ARCHITECTURE ART OF BCD7 ISBEGINLED<="1111110"WHEN BCD="0000" ELSE"0110000"WHEN BCD="0001" ELSE"1101101"WHEN BCD="0010" ELSE"1111001"WHEN BCD="0011" ELSE"0110011"WHEN BCD="0100" ELSE"1011011"WHEN BCD="0101" ELSE"1011111"WHEN BCD="0110" ELSE"1110000"WHEN BCD="0111" ELSE"1111111"WHEN BCD="1000" ELSE"1111011"WHEN BCD="1001" ELSE"0000000";END ART;BCD7仿真波形（六）分频模块的VHDL源程序（fenpin.VHD）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport(clk:in std_logic;second:BUFFER std_logic:='0');end;architecture beha of fenpin issignal s1:integer range 0 to 3000;beginprocess(clk)beginif (clk'event and clk='0') thenif(s1=2500) thensecond<=not second;s1<=0;else s1<=s1+1;end if;end if;end process;end;分频模块的仿真波形（七）顶层设计的原理图三、整体电路图原理说明：在电路图中，CLK是计时脉冲，由于硬件试验箱中没有合适的频率脉冲来准确计时，因此需要通过一个分频器将5000HZ的脉冲分频成毫秒计时，将已分频的脉冲输入进位元件，进位元件中包括十进制与六进制的进位功能，其中1毫秒、10毫秒、100毫秒、1秒、1分钟都为十进制进位，10秒、10分钟为六进制。