Lecture7_marked

Typical STI trench tilt: 70o ~ 85o
D. Shamiryan, SSE (2009)
Key requirements for bulk fin shape (process perspective): Isolation trench refilling High aspect-ratio fin patterning
10-9
L =20nm, W =9nm
g
Fin
10-10
10-11 -0.7 -0.6
10/16/2013
-0.5 -0.4 -0.3 -0.2
Gate Voltage (V)
-0.1 0.0
Nuo Xu
Even with the finite steepness of retrograde well doping (~15nm/dec in Si), it is still preferred to insert the doping peak around the fin base, causing some level of performance degradation in the fin.
Key requirements for bulk fin shape (device performance/reliability
perspective): Good electrostatic control Low corner electric field, to prevent TDDB or BTI
w/ Retrograde Well Doping w/o Retrograde Well Doping
Normalized Current (A/um)
10-3
10-4
I
10-5
ds
w/o Retrograde Well w/ Retrograde Well
10-6
10-7
•
10-8
I sub P-FinFET
Bulk FinFET
SOI FinFET (w/o BOX)
• Retrograde-well doping required as punch through-stop (PTS) layer.
• HALO is also often adopted. • Tapered fin shape due to STI process.
8
Fin Sidewall Damage Removal by H2 Annealing
Mobility Improvement by H2 Annealing
Equivalent Gate Input Noise
H2 annealing causes Si atoms remigration at fin sidewall surfaces provides smaller surface roughness and lower Dit. reduces shape corners to mitigate “corner effect”.
Y.-K. Choi, IEDM (2002)
• Spacer lithography technique provides more uniform fin width than the conventional lithography, due to σlitho > σCVD
10/16/2013
10/16/2013
Nuo Xu
EE 290D, Fall 2013
4
Fin Patterning
Spacer Lithography a.k.a. Sidewall Image Transfer (SIT) or Self-Aligned Double Patterning (SADP)
1. Deposit & pattern sacrificial layer 3. Etch back mask layer to form “spacers”
10/16/2013
Nuo Xu
A. Hokazono, VLSI-T(2008) & IEDM(2009)
14
Fin Shape Variations in Bulk FinFETs
Rectangular shape
Trapezoidal shape (Intel’s Tri-Gate)
“Hybrid”-shape
Chipworks, 2012
• Extra lithography steps required to etch the unused fins.
10/16/2013
Nuo Xu
EE 290D, Fall 2013
5
Benefit on Multiple Device Pitch
• By using spacer lithography technique, multiple fin pitches can be implemented using a single lithography step.
Nuo Xu
EE 290D, Fall 2013
3
Bulk FinFET Process Flow
• Fin heights are defined by the punchthrough stopping (PTS) layer position.
A. Yagishita (Toshiba), SOI Short Course (2009)
latchup effect.
10/16/2013
Nuo Xu
EE 290D, Fall 2013
13
Steep Retrograde Well Doping in Bulk FinFET
10/16/2013
H. Bu (IBM), SOI Workshop (2011)
Nuo Xu
EE 290D, Fall 2013
Source: Synopsys & Intel
Lecture 7
• Thin-Body MOSFET’s Process I
– SOI vs. Bulk FinFETs – Fin Patterning Techniques – High-κ/Metal Gate Technologies
Reading: multiple research articles (reference list at the end of this lecture)
• TEM picture shows more abrupt fin/oxide interface after NBE → Lower Dit
• Higher fin mobility w/ NBE
K. Endo, TED (2006)
Nuo Xu
EE 290D, Fall 2013
10
SOI vs. Bulk FinFET: Isolation
10/16/2013
Nuo Xu
EE 290D, Fall 2013
15
Impacts of Fin Shape on Electrostatics
assuming same top fin width:
A. Arsenov’s group, GSS Website (2012)
T. Hook (IBM), FDSOI Workshop (2013)
SOI vs. Bulk FinFET: Overall Structure
Bulk FinFET
SOI FinFET (w/o BOX)
T. Hook (IBM), FDSOI Workshop (2013)
10/16/2013
Nuo Xu
EE 290D, Fall 2013
2
SOI FinFET Process Flow
W HK
Gate First / MIPS
Si
(Metal-Inserted-
Poly-Si Gate)
HK
Poly-Si
Process Flow
MG
Poly-Si
MG W
High- First
Si
Gate Last / RMG (Replaced Metal Gate)
Poly-Si
HK
Si
High- Last
• 2n lines after nth lithography ! A. Yagishita (Toshiba), SOI Short Course (2009)
10/16/2013
Nuo Xu
EE 290D, Fall 2013
6
Benefit on Fin Edge Roughness
Y.-K. Choi, IEDM (2002)
• No doping process needed to avoid PT.
• Rectangular fin shape.
T. Hook (IBM), FDSOI Workshop (2013)
10/16/2013
Nuo Xu
EE 290D, Fall 2013
11
Impacts of Retrograde Well Doping
10/16/2013
Nuo Xu
EE 290D, Fall 2013
16
Impacts of Fin Shape on Current
Charge concentration across a FinFET X-section as increasing gate voltage
A. Arsenov’s group, GSS Website (2012) Considering Quantum Mechanical + Strain Effect