北航研究生Verilog硬件描述语言讲义(第六节)

Design and Process Recommendations
Aviod asynchronous feedback Remove any race conditions Split large counters Make the circuit easy to initialize to a known state Use test vector comparison techniques during simulation to ensure test insertion does not alter the functionality of the design
Synthesized Circuit Structure
A1[2:0] + B1[2:0] C1[2:0] D1[2:0] D2[2:0] + Y1[4:0] + B2[2:0] Y2[4:0] C2[2:0] + + A2[2:0] +
2
Multiplexers(2-1)
module MUX_2_1(Sel1,A1,B,Y1,Sel2,A2,B2,Y2,Sel3,A3,B3,Y3); input Sel1,A1,B,Sel2,A2,B2,,Sel3,A3,B3; output Y1, Y2,Y3;
Modeling Combinational Logic Circuits
The type of combinational logic circuit
Logical/arithmetic equations Logical structure control Multiplexers Encoders Decoders Comparators ALUs
Decoder
module DECODER3_8(A,Y); input [2:0] A; output [7:0] Y; reg[7:0] Y; always@(A) begin If(A==3’b0)Y<=8’b00000001; else if(A==3’b001)Y<=8’b00000010; … else if(A==3’b111)Y<=8’b10000000; else Y<=8’b10000000; end endmodule module DECODER3_8(A,Y); input [2:0] A; output [7:0] Y; reg[7:0] Y; always@(A) begin case (A) 3’b000:Y<=8’b00000001; 3’b001:Y<=8’b00000010; … 3’b111:Y<=8’b10000000; default:Y<=8’bx; endcase end endmodule
Encoder
module ENCODER (A,Y); input [7:0] A; output [2:0] Y; reg[2:0] Y; interger N; always@(A) begin Y<=2’b00; for(N=0;N<=7;N=N+1) if(A[N]) Y<=N; end endmodule
Synthesized CiHale Waihona Puke Baiducuit Structure
S
S Y S 0 0 1 1 A 0 1 x x B x x 0 1 Y 0 1 0 1 A Y B
wire Y1= Sel1?A1:B1; or
wire Y1;
assign Y1= Sel1?A1:B1;
A B
always@(Sel2 or A2, or B2 or Sel3 or A3 or B3) begin Y2<=B2; if(Sel2) Y2<=A2; if(Sel3) Y3<=A3; else Y3<=B3; end endmodule
3
Decoder
input A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Y7 0 0 0 0 0 0 0 1 Y6 0 0 0 0 0 0 1 0 Y5 0 0 0 0 0 1 0 0 output Y4 0 0 0 0 1 0 0 0 Y3 0 0 0 1 0 0 0 0 Y2 0 0 1 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 Y0 1 0 0 0 0 0 0 0
Encoder
input A7 0 0 0 0 0 0 0 1 A6 0 0 0 0 0 0 1 0 A5 A4 A3 A2 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 A1 0 1 0 0 0 0 0 0 output A0 Y2 Y1 Y0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Logical/arithmetic equations
module simple_data_flow (A1,A2,B2,Y1,Y2,Y3); input [7:0]A1; input [2:0] A2,B2; output Y1; output Y2; output [3:0] Y3; reg Y1; reg [3:0] Y3; always@(A1[3:0]) begin Y1 <= ((A1[0] &A1[1])| (A1[2]&A1[3]))) end assign Y2=((A1[4]|A1[5])& (A1[6]|A1[7]) always@(A2[2:0] or B2[2:0]) begin Y3 <= A2[2:0]+B2[2:0]; end endmodule
the hardware intent The synthesis modeling style and its associated restrictions
General HDL modeling recommendations
Make models generic as far as possible for model reuse Be aware that Verilog is case sensitive so identifiers “A” and “a” are different Make use of abstract data types to make models easier to read and maintain Use meaningful signal names Use comments liberally
Verilog HDL Chip Design
Design and Modeling Recommendations
Design and Process Recommendations
Adopt a top-down design and modeling methodology Define a design’s requirement specification as tightly as practically possible It is a good design practice to use global clock and reset signals where possible Consider testability issues early in the total system design process
General HDL modeling recommendations
Before attempting to code a model at the register transfer level, determine a sound architecture and partition accordingly When writing HDL code keep in mind:
Encoder
module ENCODER_8_3_IF_ELSE(A,Y); input [7:0] A; output [2:0] Y; reg[2:0] Y; always@(A) begin If(A==8’b00000001)Y<=3’b0; else if(A==8’b00000010)Y<=3’b001; … else if(A==8’b10000000)Y<=3’b111; else Y<=3’bx; end endmodule module ENCODER_8_3_CASE(A,Y); input [7:0] A; output [2:0] Y; reg[2:0] Y; always@(A) begin casex(A) 8’b00000001:Y<=3’b0; 8’b00000010:Y<=3’b001; … 8’b10000000:Y<=3’b111; default:Y<=3’bx; endcase end endmodule
Use subprograms wherever possible to help structure a design making the code shorter and easier to read
1
Structuring a Design
Models are less cluttered and easier to read Previously designed and verified submodels can be used repeatedly within a design Previously designed and verified models can be quickly and easily incorporated into new design A well partitioned design,having structure corresponding to its functional operation,and breaks the total design and verification task into smaller, more manageable pieces
Logical structure control
module comb_logic_struct(A1,B1,C1.D1,A2,B2,C2,D2,Y1,Y2); input[2:0] A1,B1,C1,D1,A2,B2,C2,D2; output[4:0] Y1,Y2; reg [4:0] Y1,Y2; Always @(A1 or B1 or C1 or D1 or A2 or B2 or C2 or D2) begin Y1 <= A1+B1+C1+D1; Y2 <= (A2+B2)+(C2+D2); end endmodule
Multiplexers(4-1)
module Mux4_1(Sel,A,B,C,D,Y); input [1:0] Sel; input A,B,C,D; output Y; reg Y; always@(Sel or A or B or C or D) If(Sel==2’b00) Y<=A; else if(Sel==2’b01) Y<=B; else if(Sel==2’b10) Y<=C; else Y<=D; endmodule module Mux4_1(Sel,A,B,C,D,Y); input [1:0] Sel; input A,B,C,D; output Y; reg Y; always@(Sel or A or B or C or D) case(Sel) 2’b00:Y<=A; 2’b01:Y<=B; 2’b10:Y<=C; 2’b11:Y<=D; default: Y<=A; endmodule