VHDL数字钟设计报告

VHDL数字钟设计报告一. 数字钟总体设计方案：1.1设计目的①正确显示时、分、秒；②可手动校时，能分别进行时、分的校正；③整点报时功能；1.2设计思路数字钟的设计模块包括：分频器、去抖动电路、校时电路、“时、分、秒”计数器、校时闪烁电路、整点报时和译码显示电路。

每一个功能模块作为一个实体单独进行设计，最后再用VHDL的例化语句将各个模块进行整合，生成顶层实体top。

该数字钟可以实现3个功能：计时功能、设置时间功能和报时功能。

二．数字钟模块细节2.1 分频器（fenpin）本系统共需3种频率时钟信号（1024Hz、512Hz、1Hz）。

为减少输入引脚，本系统采用分频模块，只需由外部提供1024Hz基准时钟信号，其余三种频率时钟信号由分频模块得到。

分频原理：为以1024Hz基准时钟经1024分频得到512Hz,1Hz频率时钟信号。

分频器管脚代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin isport(clk1024:in std_logic;clk1,clk512:out std_logic);end fenpin ;architecture cml of fenpin isbeginprocess (clk1024)variable count1: integer range 0 to 512; variable q1: std_logic;beginif clk1024' event and clk1024='1' then if count1=512 thenq1:=not q1;count1:=0;elsecount1:=count1+1;end if;end if;clk1<=q1;end process;process(clk1024)variable count512: integer range 0 to 1; variable q512: std_logic;beginif clk1024' event and clk1024='1' thenif count512=1 thenq512:=not q512;count512:=0;elsecount512:=count512+1;end if;end if;clk512<=q512;end process;end cml;2．2 校时电路（jiaoshi）本模块要实现的功能是：正常计时、校时、校分在每个状态下都会产生不同控制信号实现相应的功能。

校时管脚图代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jiaoshi isport(rst,rvs,select_rvs,mtime,mclkin,hclkin:in std_logic;hclkout,mclkout:out std_logic);end jiaoshi;architecture cml of jiaoshi issignal h_m:std_logic;beginp1:process(rst,rvs,hclkin,mclkin,h_m,mtime)beginif rst='0' thennull;elsif rvs='1' thenhclkout<=hclkin;mclkout<=mCLKin;elsif h_m='0' thenhclkout<=hclkin;mclkout<=mtime;elsehclkout<=mtime;mclkout<=mclkin;end if;end process;p2:process(select_rvs)beginif select_rvs'event and select_rvs='1' thenh_m<=not h_m;end if;end process ;end cml;管脚图仿真图2.3 时计数器（hour）分计数器(mine)秒计数器(second)时计数器管脚图时代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport(rst,hclk:in std_logic;hour0,hour1:buffer std_logic_vector(3 downto 0 ));end hour;architecture cml of hour isbeginprocess(rst,hclk,hour0,hour1)beginif rst='0' thenhour0<="0000";hour1<="0000";elsif hclk'event and hclk='1' thenif hour0="0011" and hour1="0010" thenhour0<="0000";hour1<="0000";elsif hour0="1001" thenhour0<="0000";hour1<=hour1+1;elsehour0<=hour0+1;end if;end if;end process ;分计数器管脚图分代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mine isport(rst,mclk:in std_logic;mco:out std_logic;min0,min1:buffer std_logic_vector(3 downto 0 ) );end mine;architecture cml of mine issignal min0_t,min1_t:std_logic_vector(3 downto 0 ); beginprocess(rst,mclk,min0,min1)beginif rst='0' thenmin0<="0000";min1<="0000";elsif mclk'event and mclk='1' thenif min0="0101" and min1="1001" thenmin0<="0000";min1<="0000";mco<='1';elsif min0="0010" and min0="1001" thenmin1<="0011";min0<="0000";mco<='0';elsif min0="1001" thenmin1<=min1+1;min0<="0000";elsemin0<=min0+1;end if;end process ;end cml;秒计数器管脚图秒代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport(rst,sclk:in std_logic;sco:out std_logic;sec0,sec1:buffer std_logic_vector(3 downto 0 ) );end second;architecture cml of second issignal sec0_t,sec1_t:std_logic_vector(3 downto 0 ); beginprocess(rst,sclk,sec0,sec1)beginif rst='0' thensec0<="0000";sec1<="0000";elsif sclk'event and sclk='1' thenif sec0="0101" and sec1="1001" thensec0<="0000";sec1<="0000";sco<='1';elsif sec0="0010" and sec0="1001" thensec1<="0011";sec0<="0000";sco<='0';elsif sec0="1001" thensec1<=sec1+1;sec0<="0000";elsesec0<=sec0+1;end if;end if;end process ;end cml;2.4 校时闪烁电路（flashnjiaoshi）如果正在进行校时，flashjiaoshi将实现使当前正在校时项（小时或分钟）以1Hz的频率闪烁，以便于操知道正在被校正。

校时闪烁电路管脚图代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity flashjiaoshi isport(rst,sclk,rvs,select_rvs:in std_logic;hour0in,hour1in,min0in,min1in:in std_logic_vector(3 downto 0 );hour0out,hour1out,min0out,min1out :out std_logic_vector(3 downto 0 ));end flashjiaoshi;architecture cml of flashjiaoshi issignal h_m:std_logic;beginp1:process(rst,sclk,rvs,hour0in,hour1in,min0in,min1in,h_m)beginif rst='0' thennull;elsif rvs='1' thenhour0out<=hour0in;hour1out<=hour1in;min0out<=min0in;min1out<=min1in;elsif h_m='0' thenhour0out<=hour0in;hour1out<=hour1in;if sclk='1' thenmin0out<=min0in;min1out<=min1in;elsemin0out<="1111";min1out<="1111";end if;elsemin0out<=min0in;min1out<=min1in;IF sCLK='1' thenhour0out<=hour0in;hour1out<=hour1in;elsehour0out<="1111";hour1out<="1111";end if;end if;end process p1;p2:process(select_rvs)beginif select_rvs'event and select_rvs='1' then h_m<=not h_m;end if;end process p2;end cml;2.5 整点报时电路整点报时管脚图代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity baoshi isport( clk1024,clk512 : in std_logic;min0,min1 , sec0,sec1 : in std_logic_vector (3 downto 0);speak : out std_logic);end baoshi;architecture cml of baoshi isbeginspeak<=clk512when (min1="0101" and min0="1001" and sec1="0101") and (sec0="0011" or sec0="0101" or sec0="0111") elseclk1024when( min1="0101" and min0="1001" and sec1="0101" and sec0="1001") else '0';end cml;2.6 译码显示电路该显示用的是动态扫描电路译码显示管脚图波形图代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport(clk512:in std_logic;h1,h0,m1,m0,s1,s0:in std_logic_vector(3 downto 0 ); seg7:out std_logic_vector(6 downto 0 );select_sig:out std_logic_vector(5 downto 0 ));end xianshi;architecture cml of xianshi issignal data:std_logic_vector(3 downto 0 );signal order:std_logic_vector(2 downto 0 );beginprocess(clk512)beginif clk512' event and clk512='1' thencase order iswhen "000"=>data<=h1;select_sig<="011111";when "001"=>data<=h0;select_sig<="101111";when "010"=>data<=m1;select_sig<="110111";when "011"=>data<=m0;select_sig<="111011";when "100"=>data<=s1;select_sig<="111101";when "101"=>data<=s0;select_sig<="111110";when others=>data<="1000";select_sig<="111111"; end case;if order="101" then order<="000";else order<=order+1;end if;end if;end process ;process(data)begincase data iswhen "0000" =>seg7 <= "0000001";when "0001" =>seg7 <= "1001111";when "0010" =>seg7 <= "0010010";when "0011" =>seg7 <= "0000110";when "0100" =>seg7 <= "1001100";when "0101" =>seg7 <= "0100100";when "0110" =>seg7 <= "0100000";when "0111" =>seg7 <= "0001111";when "1000" =>seg7 <= "0000000";when "1001" =>seg7 <= "0000100";when others =>seg7 <= "1111111";end case;end process ;end cml ;2.7数字钟整体设计（top）本数字钟的设计包括分频器、去抖动电路、校时电路、“时、分、秒”计数器、校时闪烁电路和译码显示电路。